048918 VLSI Backend CAD Konstantin Moiseev – Intel Corp. & Technion Shmuel Wimer – Bar Ilan...

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Lecture 6 Dynamic Programming: Slicing Floorplans and Technology Mapping 048918 VLSI Backend CAD Konstantin Moiseev – Intel Corp. & Technion Shmuel Wimer – Bar Ilan Univ. & Technion

Transcript of 048918 VLSI Backend CAD Konstantin Moiseev – Intel Corp. & Technion Shmuel Wimer – Bar Ilan...

Page 1: 048918 VLSI Backend CAD Konstantin Moiseev – Intel Corp. & Technion Shmuel Wimer – Bar Ilan Univ. & Technion.

Lecture 6Dynamic Programming: Slicing

Floorplans and Technology Mapping

048918VLSI Backend CAD

Konstantin Moiseev – Intel Corp. & Technion Shmuel Wimer – Bar Ilan Univ. & Technion

Page 2: 048918 VLSI Backend CAD Konstantin Moiseev – Intel Corp. & Technion Shmuel Wimer – Bar Ilan Univ. & Technion.

VLSI design flow overview Introduction to algorithms and optimization Backend CAD optimization problems:

◦ Design partitioning◦ Technology mapping◦ Floorplanning◦ Placement◦ Routing

Introduction to layout Layout optimization and verification

◦ Layout analysis◦ DRC and LVS checks◦ Finding objects in the layout

Course outline

Page 3: 048918 VLSI Backend CAD Konstantin Moiseev – Intel Corp. & Technion Shmuel Wimer – Bar Ilan Univ. & Technion.

Dynamic programming◦ Formal definition ◦ Simple examples

Slicing floorplans◦ General description◦ Dynamic programming algorithm

Technology mapping◦ Problem definition◦ Solution stages◦ Dynamic programming algorithm

Lecture outline

Page 4: 048918 VLSI Backend CAD Konstantin Moiseev – Intel Corp. & Technion Shmuel Wimer – Bar Ilan Univ. & Technion.

Dynamic Programming is a bottom-up technique that can be applied to solving optimization problems that are decomposable

A minimization problem is decomposable if each instance of the problem can be decomposed (perhaps in multiple ways) into “smaller” problem instances such that we can obtain a solution (not necessary an optimal one) of by combining optimal solutions of the

Each sub-problem has a positive decomposition size (d-size) that decreases in each decomposition step

Problem instances whose d-size is below some threshold are required to be directly solvable

In order to be solved by DP the problem has to exhibit optimal substructure

Dynamic Programming (DP)

p

1, , kp pps p

1, , kp p1, ,

kp ps s

Page 5: 048918 VLSI Backend CAD Konstantin Moiseev – Intel Corp. & Technion Shmuel Wimer – Bar Ilan Univ. & Technion.

Principle of optimality states that:1. There is a monotonically increasing function such that:

Reminder: is a cost of solution (not necessarily an optimal one) is monotonically increasing if for ,

2. There must be at least one way of breaking up into such that an optimal solution of results from combining arbitrary optimal solutions of the sub-problems and

3. We must be able to compute each such quickly by combining the The problem decomposable in this way exhibits optimal

substructure

Optimal substructure and principle of optimality

: kf

1, ,

kp p pc s sf c c s

pc s ps 1, , nf x x

1 1' , , 'n nx x x x 1 1', , ' , ,n nf x x f x x

1, , kp pps p

1, , kp p

1, ,

kp psc cf s c s

sips

Page 6: 048918 VLSI Backend CAD Konstantin Moiseev – Intel Corp. & Technion Shmuel Wimer – Bar Ilan Univ. & Technion.

Solution by DP can be seen as a sequential decision process◦ A stage is a set of all solutions to sub-problems with the same

d-size:

◦ Individual solutions in each stage are called states◦ The sequence of stages is built bottom-up, starting with stage

containing solutions to atomic sub-problems and ending with stage containing solutions to the whole problem

◦ Only the states in stage are used to create states in stage ◦ Most of newly created states in stage are pruned, leaving

only optimal (non-redundant) solutions◦ The optimal states are saved and re-used for next stage states

generation – this is called memoization◦ After stage n is reached, optimal solution itself is reconstructed

by top-down backtracking

Sequential decision process

1, , | ,1k ji p i jp kp d_size

i 1i 1i

Page 7: 048918 VLSI Backend CAD Konstantin Moiseev – Intel Corp. & Technion Shmuel Wimer – Bar Ilan Univ. & Technion.

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Floorplan Graph representation

Back to floorplanning

B2B1

B3 B5

B4

B6

B12

B9

B8 B7

B10

B11

B2

B1

B1

0

B5

B12B6

B3

B9

B8

B7

B11B4

Vertices - vertical lines. Arcs - rectangular areas where blocks are embedded.

Floorplan is represented by a planar graph.

A dual graph is implied.

Page 8: 048918 VLSI Backend CAD Konstantin Moiseev – Intel Corp. & Technion Shmuel Wimer – Bar Ilan Univ. & Technion.

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Actual layout is obtained by embedding real blocks into

floorplan cells.

◦ Blocks’ adjacency relations are maintained

◦ Blocks are not perfectly matched, thus white area (waste)

results

Layout width and height are obtained by assigning blocks’

dimensions to corresponding arcs.

◦ Width and height are derived from longest paths

Different block sizes yield different layout area, even if

block sizes are area invariant.

From Floorplan to Layout

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Optimal Slicing Floorplan

hh

vv vv

B2B1

B3 B5

B4

B6B11B3 B4 B5 B6 B8 B9 B10

B1 B2 B7

hhhh

B12

B12

B9

B8 B7

B10

B11

Slicing tree. Leaf blocks are associated with areas.

v

Top block’s area is divided by vertical and horizontal cut-lines

Page 10: 048918 VLSI Backend CAD Konstantin Moiseev – Intel Corp. & Technion Shmuel Wimer – Bar Ilan Univ. & Technion.

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Let block , 1 , have possible implementations , ,

1 , having fixed area .

In the most simplified case , 1 , have 2 implementations

corresponding to 2 orientations.

:

i i

i j j j

i i

i j j i

i

B i b h w

j n h w a

B i b

Problem Find among the 2 possible block orientations , 1 2 ,

the one of smallest area.

b b

i i

(L. Stockmeyer): Given slicing floorplan of blocks whose

slicing tree has depth , finding the orientation that yields the smallest

area takes time and storage.

b

d

O bd O bd

Theorem

Page 11: 048918 VLSI Backend CAD Konstantin Moiseev – Intel Corp. & Technion Shmuel Wimer – Bar Ilan Univ. & Technion.

Notation , is a cost function - non-decreasing in both arguments and computable

in constant time.

h w

slicing floorplan

corresponding binary slicing tree

F

T

and dimensions of floorplan with orientation F F Fh w

floorplan described by the subtree routed at node

set of leaves in that subtree

u uF

uL

The problem: ,F Fh w

min

Page 12: 048918 VLSI Backend CAD Konstantin Moiseev – Intel Corp. & Technion Shmuel Wimer – Bar Ilan Univ. & Technion.

By induction

Proof

1 1 2 2

1 1

For each node of the algorithm constructs a list of pairs

with the following properties:

.

. and for with

. For each with th

, , , ,

ere is

1

3

,

11

,

2

1

m m

i i i i

h w h w h w

m L u

h h w w i i m

i i m

u T

( ) ( )

( ) ( )

an orientation of the cells in such

that:

. For each orientation of the cells in there is a pair in the

list with:

,

and

,

4 ,

i i F u F u

i i

i F u i F u

L u

h w h w

L u h w

h h w w

Page 13: 048918 VLSI Backend CAD Konstantin Moiseev – Intel Corp. & Technion Shmuel Wimer – Bar Ilan Univ. & Technion.

ProofThe algorithm constructs lists bottom up.

For each of with dimensions and w ,l ith the list is e ,af ,T a b a b a b b aThe conditions 1-4 are satisfied lfor eaf.

1 1

1 1

'

, , , ,

', ' , ,

nonLet be a vertical slice node of with children and and let

be the lists constructed for and respectively, where

', '

' 1

-l

eaf

1

and

'

k k

m m

u T v v

h w h w

h w h w

v v k L v

m L v

Let us assume by induction that properties 2-4 are satisfied for these lists.

Page 14: 048918 VLSI Backend CAD Konstantin Moiseev – Intel Corp. & Technion Shmuel Wimer – Bar Ilan Univ. & Technion.

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v1 v2 v3 v4

v1’ v2’ v3’ + =

+ =

+ =

u

''

max ,u v v

u v v

h h h

w w w

ProofThe pairs in list for are created by procedure:u maxplus merge

Page 15: 048918 VLSI Backend CAD Konstantin Moiseev – Intel Corp. & Technion Shmuel Wimer – Bar Ilan Univ. & Technion.

1 1// vertical cut-line

// lists are sorted in descending

HorizontalMerging ( , , , ) {

1; 1;

while (( ) && ( )) {

max ' , ;

'

order of he

;

ight

ts

i i j ji j

u i j

u i j

w h w h

i j

i s j t

h h h

w w w

if ( ' ) { }

else if ( ' ) { }

else { ; // ' }

}

}

i j

i j

i j

h h i

h h j

h hi j

u

Size of new width-height list equals sum of lengths of children lists, rather than their product (redundant solutions are pruned).

Proof

Page 16: 048918 VLSI Backend CAD Konstantin Moiseev – Intel Corp. & Technion Shmuel Wimer – Bar Ilan Univ. & Technion.

Understanding pruning

w

h

Pareto frontier (irredundant solutions) - saved

Redundant solutions - pruned

For continuous problems Pareto frontier is always convex

Page 17: 048918 VLSI Backend CAD Konstantin Moiseev – Intel Corp. & Technion Shmuel Wimer – Bar Ilan Univ. & Technion.

Proof. The new list created for satisfies properties 1-4.uClaim

. The maximum number of loop iterations is .

Therefore:

1

1 1

Property 1

' 1 1 1

k m

k m L v L

wh

v

il

L u

e

. Assume last created pair in list is .

For any and

max , ' , '

' ' , , ' '

max , ' max , ' w ' '

, , therefo

Property

re

and

2 i j i j

k i l j k i l j

k l i j k l i j

u h h w w

k i l j h h h h w w w w

h h h h w w w

. Satisfied by construction - each pair in the list represents some

ori

Pro

ent

perty 3

ation.

. Satisfied by construction. Only non-redundant pairs are saved in Pro theperty 4

list.

Page 18: 048918 VLSI Backend CAD Konstantin Moiseev – Intel Corp. & Technion Shmuel Wimer – Bar Ilan Univ. & Technion.

Since is non-decreasing, the optimal solution can be obtained by minimizing

over all pairs in the list constructed for the roo, t, i i i ih w h w T

Proof

: there are in total pairs in all lists at each level

of the tree and there are levels. Each pair is processed only once at each

level. Therefore, run-t

Run-

ime

time complex

complexity i

ity

s

O n

d

O nd

: the same. Space to keep atStorage each oncomplexity e of levels.O n d

: each partial solution holds two pointers to its

"parents". Top-down backtracking is used to find orie

Optimal solution reconstr

ntations of individual bl

u

o

ction

cks.

A question for self-check how algorithm and proof would change if each basic

block had implementations? What would be run-time and space complex

:

ity?p

Page 19: 048918 VLSI Backend CAD Konstantin Moiseev – Intel Corp. & Technion Shmuel Wimer – Bar Ilan Univ. & Technion.

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Another example - Optimal Tree Covering

A problem occurring in mapping logic circuit into new cell library

Given:◦ Rooted binary tree T(V,E) called subject tree (cone of logic

circuit), whose leaves are inputs, root is an output and internal nodes are logic gates with their I/O pins.

◦ A family of rooted pattern trees (logic cells of library), each associated with a non-negative cost (area, power, delay). Root is cell’s output and leaves are its inputs.

A cover of the subject tree is a partitioning where every part is matching an element of library and every edge of the subject tree is covered exactly once.

Find:◦ A cover of subject tree whose total sum of costs is minimal.

Page 20: 048918 VLSI Backend CAD Konstantin Moiseev – Intel Corp. & Technion Shmuel Wimer – Bar Ilan Univ. & Technion.

Optimal Tree Covering

The problem: ◦ Find covering of subject graph (tree) with minimal area

?Pattern treesSubject tree

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r

s t

u

t1 (2) t2 (3) t5 (5)t4 (4)t3 (3)

t2

t1 t1

t3

3+2+2+3=10

t4t1

t3

4+2+3=9

t2

t5

3+5=8

Page 22: 048918 VLSI Backend CAD Konstantin Moiseev – Intel Corp. & Technion Shmuel Wimer – Bar Ilan Univ. & Technion.

Tree coveringBrute force approach Brute force solution, recursive exploration:

Start from root, try all possible patternsFor each root pattern, try all possible patterns for its

descendants, etc. Run-time:

◦ For each node try all possible patterns◦ For tree with nodes and patterns in library run time is ~

◦ Should look for another approach

n p

pO n

Page 23: 048918 VLSI Backend CAD Konstantin Moiseev – Intel Corp. & Technion Shmuel Wimer – Bar Ilan Univ. & Technion.

Tree coveringDynamic programming Revealing optimal substructure:

◦ If pattern P is min cost match at some node of subject tree…◦ then it must be that each leaf of pattern tree is also the root of some min cost

matching pattern Assume three different patterns match at root of subject tree

◦ Pattern P1 has 2 leaf nodes: a and b◦ Pattern P2 has 3 leaf nodes: x, y and z◦ Pattern P3 has 4 leaf nodes: j, k, l and m◦ Which is the cheapest pattern if we know cost of each pattern?

Based on R. Rutenbar slides

Page 24: 048918 VLSI Backend CAD Konstantin Moiseev – Intel Corp. & Technion Shmuel Wimer – Bar Ilan Univ. & Technion.

Tree coveringDynamic programming

Min cost tree cover◦ Cheapest cover of root of subject tree is mincost(root) =

min(patterncost(P1) + + ,patterncost(P2) + + + ,patterncost(P3) + + + + )

- Each rectangle means recursive call to mincost (subtree) This shows optimal substructure of covering problem

Based on R. Rutenbar slides

mincost(a) mincost(b)

mincost(x) mincost(y) mincost(z)

mincost(j) mincost(k) mincost(l) mincost(m)

Page 25: 048918 VLSI Backend CAD Konstantin Moiseev – Intel Corp. & Technion Shmuel Wimer – Bar Ilan Univ. & Technion.

Tree coveringDynamic programming Revealing overlapping sub-problems

◦ Assume we calculate tree cost top-down◦ For picture below: node “y” in the subject tree

Will get its mincost cover computed (mincost(y)) when we put P2 at the root of the subject tree

… and again, when we put P3 at the root

◦ Instead, calculate tree cost bottom-up Will have to calculate mincost(y) only once and store – memoization

◦ This reminds Fibonacci numbers example …

Based on R. Rutenbar slides

Page 26: 048918 VLSI Backend CAD Konstantin Moiseev – Intel Corp. & Technion Shmuel Wimer – Bar Ilan Univ. & Technion.

Tree coveringDynamic programming Assume table[node] = ∞ for all nodes at the beginning The algorithm:

Based on R. Rutenbar slides

Page 27: 048918 VLSI Backend CAD Konstantin Moiseev – Intel Corp. & Technion Shmuel Wimer – Bar Ilan Univ. & Technion.

Tree coveringDynamic programming The algorithm works bottom up For each node, checks all possible patterns that can

be rooted at this node and combines each pattern’s cost with optimal solutions of sub-trees rooted at leafs of the pattern

Only optimal solution is saved in each node Complexity:

◦ In each one of nodes patterns are checked: The run-time complexity is Space complexity is

n p

O pn O n

Page 28: 048918 VLSI Backend CAD Konstantin Moiseev – Intel Corp. & Technion Shmuel Wimer – Bar Ilan Univ. & Technion.

Tree coveringDynamic programming - Example Cover following circuit using DP approach:

Page 29: 048918 VLSI Backend CAD Konstantin Moiseev – Intel Corp. & Technion Shmuel Wimer – Bar Ilan Univ. & Technion.

Tree coveringDynamic programming - Example

- NAND2 is only match for node a

Page 30: 048918 VLSI Backend CAD Konstantin Moiseev – Intel Corp. & Technion Shmuel Wimer – Bar Ilan Univ. & Technion.

Tree coveringDynamic programming - Example

- NAND2 is only match for node c- INV is only match for node b

Page 31: 048918 VLSI Backend CAD Konstantin Moiseev – Intel Corp. & Technion Shmuel Wimer – Bar Ilan Univ. & Technion.

Tree coveringDynamic programming - Example

- NAND2 is only match for node e- INV is only match for node d

Page 32: 048918 VLSI Backend CAD Konstantin Moiseev – Intel Corp. & Technion Shmuel Wimer – Bar Ilan Univ. & Technion.

Tree coveringDynamic programming - Example

-INV is possible match for node f- AOI21 is possible match for node f- NAND2 is only match for node g

Page 33: 048918 VLSI Backend CAD Konstantin Moiseev – Intel Corp. & Technion Shmuel Wimer – Bar Ilan Univ. & Technion.

Tree coveringDynamic programming - Example

-INV is only match for node h- NAND2 is possible match for node i- NAND3 is only match for node i

Page 34: 048918 VLSI Backend CAD Konstantin Moiseev – Intel Corp. & Technion Shmuel Wimer – Bar Ilan Univ. & Technion.

Tree coveringDynamic programming - Example

-NAND2 is only match for node j- NAND3 is possible match for node j

Page 35: 048918 VLSI Backend CAD Konstantin Moiseev – Intel Corp. & Technion Shmuel Wimer – Bar Ilan Univ. & Technion.

Tree coveringDynamic programming - Example Now backtrack to reveal optimal cover

Page 36: 048918 VLSI Backend CAD Konstantin Moiseev – Intel Corp. & Technion Shmuel Wimer – Bar Ilan Univ. & Technion.

Tree coveringDynamic programming - Example

Page 37: 048918 VLSI Backend CAD Konstantin Moiseev – Intel Corp. & Technion Shmuel Wimer – Bar Ilan Univ. & Technion.

Backup

Page 38: 048918 VLSI Backend CAD Konstantin Moiseev – Intel Corp. & Technion Shmuel Wimer – Bar Ilan Univ. & Technion.

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Representing slicing floorplans using shape functions

Legal shapes Legal shapes

w

h

w

h

Block with minimum width and height restrictions

ha*aw A

Page 39: 048918 VLSI Backend CAD Konstantin Moiseev – Intel Corp. & Technion Shmuel Wimer – Bar Ilan Univ. & Technion.

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Shape functions

w

h

Hard library block

w

Discrete (h,w) values

h

Page 40: 048918 VLSI Backend CAD Konstantin Moiseev – Intel Corp. & Technion Shmuel Wimer – Bar Ilan Univ. & Technion.

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Corner points

52

2

5

2 5

2

5

w

h

Page 41: 048918 VLSI Backend CAD Konstantin Moiseev – Intel Corp. & Technion Shmuel Wimer – Bar Ilan Univ. & Technion.

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Algorithm

This algorithm finds the minimum floorplan area for a given slicing floorplan in polynomial time. For non-slicing floorplans, the problem is NP-hard.

Construct the shape functions of all individual blocks

Bottom up: Determine the shape function of the top-level floorplan from the shape functions of the individual blocks

Top down: From the corner point that corresponds to the minimum top-level floorplan area, trace back to each block’s shape function to find that block’s dimensions and location.

Page 42: 048918 VLSI Backend CAD Konstantin Moiseev – Intel Corp. & Technion Shmuel Wimer – Bar Ilan Univ. & Technion.

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4

2

2

4

Block B:

Block A:

5

5

3

3

Step 1: Construct the shape functions of the blocks

Page 43: 048918 VLSI Backend CAD Konstantin Moiseev – Intel Corp. & Technion Shmuel Wimer – Bar Ilan Univ. & Technion.

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4

2

2

4

Block B:

Block A:

5

5

3

3

Step 1: Construct the shape functions of the blocks

2

4

h

6

w2 64

5

3

Page 44: 048918 VLSI Backend CAD Konstantin Moiseev – Intel Corp. & Technion Shmuel Wimer – Bar Ilan Univ. & Technion.

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4

2

2

4

Block B:

Block A:

5

5

3

3

Step 1: Construct the shape functions of the blocks

2

4

h

w2 64

6

3

5

Page 45: 048918 VLSI Backend CAD Konstantin Moiseev – Intel Corp. & Technion Shmuel Wimer – Bar Ilan Univ. & Technion.

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4

2

2

4

Block B:

Block A:

5

5

3

3

w2 6

2

4

h

4

6

hA(w)

Step 1: Construct the shape functions of the blocks

Page 46: 048918 VLSI Backend CAD Konstantin Moiseev – Intel Corp. & Technion Shmuel Wimer – Bar Ilan Univ. & Technion.

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4

2

2

4

Block B:

Block A:

5

5

3

3

hB(w)

w2 6

2

4

h

4

6

hA(w)

Step 1: Construct the shape functions of the blocks

Page 47: 048918 VLSI Backend CAD Konstantin Moiseev – Intel Corp. & Technion Shmuel Wimer – Bar Ilan Univ. & Technion.

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w2 6

2

4

h

4

6

hB(w)hA(w)

8

w2 6

2

4

h

4

6

hB(w)hA(w)

hC(w)

8

Step 2: Determine the shape function of the top-level floorplan (vertical)

Page 48: 048918 VLSI Backend CAD Konstantin Moiseev – Intel Corp. & Technion Shmuel Wimer – Bar Ilan Univ. & Technion.

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w2 6

2

4

h

4

6

w2 6

2

4

h

4

6

hB(w)hA(w)

hB(w)hA(w)

hC(w)

3 x 9

4 x 7

5 x 5

88

Minimimum top-level floorplanwith vertical composition

Step 2: Determine the shape function of the top-level floorplan (vertical)

Page 49: 048918 VLSI Backend CAD Konstantin Moiseev – Intel Corp. & Technion Shmuel Wimer – Bar Ilan Univ. & Technion.

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2 x 4 3 x 5

5 x 5

Step 3: Find the individual blocks’ dimensions and locations

w2 6

2

4

h

4

6

(1) Minimum area floorplan: 5 x 5

(2) Derived block dimensions : 2 x 4 and 3 x 5

8

Horizontal composition