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Transcript of 040606-Nishi
EE402s, Skilling Auditorium, April 6, 2006
Nanoelectronic Materials and Devices for Integrated Electronics
Yoshio Nishi, ProfessorDepartment of Electrical Engineering
Department of Material Science and EngineeringCenter for Integrated Systems
Stanford UniversityStanford, California 94305-4070
Outline
• Si-Based CMOS Scaling and Challenges
• Exploration of Non-Silicon Channel MOS
• Opportunity for Nanoelectronic Materials and Devices
• Non-Volatile Memory
• Summary
Key questions to evolutionary “nano”
• How far can “scaled CMOS” go?
• Would the rate of increase in Idsat hold?
• What can possibly allow us to break “the curse of universal mobility”?
• Is there any trick to maintain s-factor for low Ioff and avoid parasitic capacitances, e.g. drain-gate electrode capacitive coupling?
• Can we manufacture at less $/gate or bit?
30 nm prototype
(IEDM 2000)
20 nm prototype
(VLSI 2001)
25 nm
15nm
15 nm prototype
(IEDM 2001)
50 nm length
(IEDM 2002)
65 nm node
2005
45 nm node
2007
90 nm node
2003
32 nm node
2009
22 nm node
2011
10 nm prototype
(DRC 2003)
Evolutionary Silicon CMOS along ITRS
Planar Si CMOS will scale down to ~10 nm LGATEWill performance and leakage be what we need?
Mark Bohr
High Resolution TEM showing 0.03 µµµµm Channel LengthRichard Chapman
Polysilicon Gate
30 nm Channel Length78 columns of Si atoms
Source Drain
13 layers
of Si atoms
consumed
to create
3.5nm SiO2
4 nm
3.5nm SiO2
polysilcon gate
electron
mean free path
two decades
in 10 nm
donor atom
acceptor atom
inversion charge
0.1
1
10
100
0.01 0.1 1LGATE (um)
Gate
Delay
(ps)
0.1
1
10
100
1000
Ioff
(nA/um)
NMOS
Transistor CV/I Delay and Leakage Trends
Continued gate delay reduction, but at the expense of leakage current
P.P. Gelsinger, “Microprocessor for the New Millennium: Challenges, Opportunities, and New
Frontiers,” Dig. Tech. 2001 ISSCC, San Francisco, pp.22-23, February, 2001
Microprocessor scaling trends, if we do not do anything different
2002 (Intel)
Lg sub-70 nm
Tox 1.4 nm
f 2.53 GHz
P several 10 W
2008 (Intel)
Lg sub-25 nm
Tox 0.7 nm
f 30 GHz
P 10 kW
N 1.8B
Heat Generation – Naïve Extrapolation
2002 10W/cm2 Hot Plate
2006 100W/cm2 Nuclear Reactor
2010 1000W/cm2 Rocket Nozzle
2016 10000W/cm2 Sun Surface
1972 (Intel)
Lg 10,000 nm
Tox 1200 nm
f 0.00075 GHz
(75 kHz)
Possible Alternative Materials & Structures
Electrostatics
Double gate, FINFET, UTBSOI, Metal gate
Transport
Band splitting of Si: (1) strained device, (2) quantum confinement with UTBSOI
New materials with high mobility: (1) Ge, (2) III-V
Leakage currentGate leakage: high k dielectrics with metal gate
Source to drain leakage: DIBL control
Drain to substrate: Band to Band Tunneling
S/D parasitic resistance
Metal source/drain for reduced series resistance
Mobility degradation of high K gate MOS, and
reliability/variability??
S. Saito, et al., IEEE IEDM, Washington, DC, Dec., 2003.
Extensive research is needed to understand these mechanisms and
how to minimize their impact on device performance
E’0E0
∆E0 = E’0 - E0
2-foldvalleys
4-foldvalleys
E0
2-fold
E’0
4-fold
Increase ∆E0 in due to strain-induced band splitting
E1E’0
2-fold 4-fold
E0
Increase in both ∆E0and ∆E01 due to
quantum confinement effect of thin SOI films
E1
∆E01 = E1 - E0
∆Esplit
Conventional MOSFET
Ultrathin Body MOSFET
Strained-Si MOSFET
E1
S. Takagi, May 2003 at Stanford
Band Engineering for Electron Mobility Enhancement
Outline
• Si-Based CMOS Scaling and Challenges
• Exploration of Non-Silicon Channel MOS
• Opportunity for Nanoelectronic Materials and Devices
• Non-Volatile Memory
• Summary
As the channel length becomes in the range
of ballistic transport:“Charge transport mechanism will
change”
• Initial velocity is more important than the saturation velocity: “low field mobility”plays major role leading to possible introduction of Ge, GaAs, GaInAs etc
• Charge injection efficiency from the source: ultra-shallow and steep junctions and zero-barrier Schottky junctions
Motivation for Non-Silicon Channel
Transport in ballistic MOSFET Properties of Semiconductor materials
�For electrons, low mt* vinj ↑ in III-V
�Low mt* in Ge for holes
Low EG – higher BTBT
High εr – worse SCE
Strained-Ge Bulk PMOS on Relaxed SiDevice structure Si/Ge/Si Growth Band diagram
High mobility due to:
� Strain in Ge
� Reduced scattering due to
– reduced E-field in Ge
– channel being away from the interface
Low S/D leakage due to:
� Reduced E-field in Ge
� Eg ⇑⇑⇑⇑ due to confinement of Ge film
Krishnamohan, Krivokapic, Uchida, Nishi and Saraswat, IEEE Symp. on VLSI Tech., June 2005.
Band-To-Band-Tunneling
E-field contours
Increasing Eg,eff in strained-Ge with decreasing Tge
Lower E-field in strained-Ge with increasing TSi
E-Field
Tge BTBT
ID-VG
Krishnamohan, Krivokapic, Uchida, Nishi and Saraswat, IEEE Trans. Elec Dev. (To be published as invited paper)
Charge Quantization in Thin Films
Sub-band Occupancies in thin semiconductor films with Qinv=5x1012 cm-2.
� Quantization due to thin films
and high surface E-field
� Sub-band energies increase
∝∝∝∝ mz-1. ΓΓΓΓ levels rise fast
because of very small m
� Charge occupies high DOS
heavy valleys in L and X
Pethe, Krishnamohan, Kim, Oh, Wong, Nishi and Saraswat, IEDM 2005
E
k<111><100>
Indirect Tunneling(Phonon assisted) Indirect Tunneling
(Phonon assisted)Direct
Tunneling
Quantized
Levels
X-valleyL-valley-valley
Heavy holesLight
Spin off
(mA
/µm
)
• III-V materials much lower intrinsic delays than Si
• InAs has lowest intrinsic delays.
• GaAs provides slightly higher delays but at much reduced Off state leakage
• Ge and III-V materials have higher IDSthan Si.
• BTBT increases with smaller bandgap
• Thin body causes quantization and pushes available states away ⇒effective increase in band gap
Need innovative structure to combine advantages of a high-µ
material for transport and a large bandgap material for leakage
Pethe, Krishnamohan, Kim, Oh, Wong, Nishi and Saraswat, IEDM 2005
Performance vs Scaling
Outline
• Si-Based CMOS Scaling and Challenges
• Exploration of Non-Silicon Channel MOS
• Opportunity for Nanoelectronic Materials and Devices
• Non-Volatile Memory
• Summary
Revolutionary “nano”
• Still charge controlled device?
• Better electrostatics?
• Better transport properties?
• Control of every parameters which has been “pre-requisite” of evolutionary “nano”?
• Do we still focus on traditional “integrated electronics” or broaden our scope with new potential capability?
Nanotube
Gate
HfO2
10 nm SiO2
p++ Si
S D
Ballistic Nanotube Transistors
-25
-20
-15
-10
-5
I DS (µA)
-0.4 -0.3 -0.2 -0.1 0.0VDS (V)
0.2 V
-0.1 V
-0.4 V
-0.7 V
-1.0 V
-1.3 V
L ~ 50 nm
-
-
I DS(µA)
VDS = -0.1,-0.2,-0.3 V10
-9
10-8
10-7
10-6
10-5
-IDS (A)
-1.5 -1.0 -0.5 0.0 0.5VG (V)
I DS(µA)
L ~ 50 nmDai (Stanford)McIntyre (Stanford) Gordon (Harvard)Lundstrom (Purdue)
Catalyst Support
CnHm
CnHm
Fe
Key Challenge: Low thermal budget controlled growth
Growth MOS Transistor
Controlling Nanowire SynthesisControlling Nanowire Synthesis
Orientation ControlOrientation Control
An array of ordered perpendicular germanium nanowires on silicon (111)
surface
Position ControlPosition Control
Nanowires restricted to areas with patterned gold. Gold patterns defined using e-beam lithography and
liftoff
Cross section SEM Plane view SEM
1 µm500 nm
Jagannathan, Kim, Deal, McIntyre, Nishi, SSDM 2005
Ambipolar conduction of CNT
midgap CNT MSDFETVVD 4.0=
VG < VD/2hole conduction
EC
EV
VG > VD/2electron conduction
EC
EV
Questions for CNT electronics
• How to obtain 100% Semiconducting SWNTs?
- Best: 90% S-SWNTs thus far (by PECVD)
• Small SWNTs are not useful for electronics
- Unless ohmic contacts are made for d < ~1.2nm tubes
- Popular materials: d ~1 nm, excellent for optical spectroscopy, not for electronics
(e.g., Hipco and other materials)
→ Make diameter just right or make ohmic contacts for 1nm SWNTs
H. Dai, CNT Devices and Applications Workshop, Stanford, Sept., 2005
Organic Semiconductor Materials
N
N
N
N
N
N
N
N
Cu
F
F
F
F
F
F
FFF
F
F
F
F
F
FF
NN
O
O
O
O
C7F15
C7F15
S
S
S
S
S
S
N
N
N
N
N
N
N
N
Cu
S
C6H13
Copper hexadecafluorophthalocyanine
Dialkyl-naphthalenetetracarboxylic diimide
αααα−−−−Sexithiophene
Copper phthalocyanine n
Regioregular poly(3-hexylthiophene)
Pentacene
NHHN
O
O
O
O
Perylenetetracarboxylic diimide
•Delocalized ππππ electrons
•A high degree of molecular ordering is necessary
•Excellent film forming ability is necessaryN. Melosh, Nonvolatile Memory Workshop, Stanford, 2004
Large area, low cost, flexible electronics:
Displays, memories, solar cells
Electronic book, electronic paper, RF-ID tags, sensors, flexible solar cells
Nano electronics: Au Au
McEuen et al, Nature, 417, 722 (2002)
Lucent/E-InkPhilips
Philips
Key Challenges in Nanoelectronics
Kuekes et al., J App Phys, 2005
Lau et al. Appl. Phys A, 2005Ramachandran et al., Science, 2003
Cui et al., APL, 2001
…but cannot control their arrangement
?
S S
?
… but don’t understand what is happening
I
V
-1000
-500
0
500
1000
1500
2000
-1 -0.5 0 0.5 1
6-10_27-10_2
8-10_29-10_2
8-9_2
Cu
rre
nt
(nA
)
Voltage (V)
•We have good nanowires
• We observe molecular switching behavior
• We have active nanoscale devices… but their properties are highly variable
Off 1 Off 2
Silicon Based CMOS as “Dominant
design” in microelectronics due to
lowest power consumption
However, both active and passive power consumptions becoming the
most challenging issues in nanoelectronics era*
* We did have this situation in late 70’s, driving bipolar out, and in middle 80’s again pushing nMOS out.
Outline
• Si-Based CMOS Scaling and Challenges
• Exploration of Non-Silicon Channel MOS
• Opportunity for Nanoelectronic Materials and Devices
• Non-Volatile Memory
• Summary
Nonvolatile Memory Opportunities
• Growing needs for embedded memory fueled by consumer electronics applications
• Power consumed by embedded memory will become substantial factor
• Nonvolatile memory, coupled with better scalability, would provide possible solution for this in addition to nanoparticle based flash, ferroelectric polarization, MRAM,
Ferroelectric resistance changePhase changeConductance bridge Organic/molecular
Cross-Point Memory with Nanowire
DiodeInitial target:• Ge nanowire for better growth control
– Practice device integration with nanowire
Future plan:• Explore better diode materials Ge nanowire encapsulated
by SiO2
SL
m-1
SL
m+1SL
WL
n-1
WL
n+1
Diode plus
memory element
Wordline
(W/L)
WL
n
WL
n
WL
n
WL
n
WL
n
WL
n
WL
n
WL
n
WL
n
Bitline (B/L)
Nanowire diode
Memory element
Top electrode
Bottom electrode
Philip Wong, Stanford
Conducting paths between the device’s two terminals in a reversible process that changes electrical resistance by orders of magnitude
– Filament effect (contributed by metal ions,charged defects, soft breakdown, storage/release of charge carriers, etc)– small applied voltage levels and energy– large non-volatile resistance changes– simple, highly scalable structure
Resistive Switching Memory Cell-V
Ground
Metal
Metal
Semiconductor
Ag/ZnCdS/Pt Devices Cu/CuxS/Pt Devices
On-resistance is independent of contact size → filament conductionOff-resistance is proportional to contact size → bulk leakageOn/Off ratio improves with scaling
Switching MechanismON Transition - Voltage Driven OFF Transition - Current Driven
Z. Wang, Y. Nishi
Logic
Logic
NVM
. . . . . .. . . .. ……. ….. ……. ….….. ..
.. ….. …. …
Circuit/Architecture of Non-Volatile System
Typical Implementation :
A separate NVM chipSeparately optimized technologiesTradeoffs : cost; communication bottleneck between chips
NV
M
Logic
NVM
Circuit
Embedded Implementation :
Single chip with NVM blockTradeoffs : process complexity; poor array efficiency due to excessive peripheral decoders, and read/write circuits; communication bottleneck between NVM and logic blocks.
Distributed Implementation :
Single chip with distributed NVM circuitsChallenge : need low cost, simple, low voltage NVM elements, and novel efficient circuits; could enable block power-down.
....
3-D Integration: Motivation
• Reduce Chip footprint
• Interconnect length and therefore R, L, C can be minimized
– Power reduction
– Delay reduction
• Integration of heterogeneous technologies possible, e.g., memory & logic, optical I/O
2-D System 3-D System
Summary
• Scaling of Si-based CMOS encounters a variety of challenges, which has ignited much in-depth study of materials, device structure and physics
• Opportunity for non-Si based CMOS, including revolutionary “nano” is on the horizon, though the magnitude of challenge would be almost similar to vacuum tube to transistor transition
• Multi-disciplinary research collaborations must be one of the pre-requisites for further progress, including exploration for “right devices for right application”