02_Chapter2_FPGA Fundaments-9501

8/2/2019 02_Chapter2_FPGA Fundaments-9501

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Chapter 2 FPGA Fundaments


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Overview -- Categories of

Programmable Logic Devices (PLDs)

Simple Programmable Logic Devices (SPLDs) Complex Programmable Logic Devices (CPLDs)

Field Programmable GateArrays (FPGAs)


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PLD Categories


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Design Factors Affecting PLD

Architectural Selection


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PLD Design


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SPLD Device Overview

Simplest PLD (SPLD) devices PAL: Programmable Array Logic

PLA: Programmable Logic Array

Two logic gate array architectures

Boolean ANDs and ORs


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Simplified PAL Architecture


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SPLD Characteristic


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CPLD Device Overview

CPLD: Complex programmable LogicDevice

Complexity and density:

FPGAs > CPLDs >SPLDs


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Basic CPLD Structure

Macro Macro

Macro Macro Macro

Macro

Switch FabricInput/OutputInput/Output

Input/Output

Input/Output


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CPLD Decision Tree


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CPLD Characteristics


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CPLD to FPGA Comparison


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A Mapping of Functionality for

CPLD and FPGAs


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Operational Categories of

FPGA Devices


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FPGA Device Overview

FPGA were introduced in 1985 by Xilinx FPGA were developed to address the

gap between CPLD and Application-Specific Integrated Circuits (ASIC)devices


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Typical FPGA Characteristics


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FPGA Types


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One-time-programmable FPGAOTP: One-Time-Programmable

ISP: In-System-Programming


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FPGA Manufacture


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SRAM-Based FPGA Architecture


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Fundamental FPGA Structure

Logic blacks Routing matrix and global signals

I/O blocks Clock resources

Multiplier Memory

Advance features


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FPGA Logic Block Structure

Logic block: logic cell, slice, macrocell, andlogic element (LE)


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Look-Up-Tables (LUTs) Element

A LUT is simply a memory element


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Combine Logic Block

Some example names for these combined logicblock groups are: tile, configurable logic block(CLB), logic array block (LAB) and MegaLAB

d


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FPGA Routing Matrix and

Global Signals


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Carry Chain Logic

Gl b l L Sk R ti


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Global Low-Skew Routing

Resources

These resources are typically Limited in quantity

Be reserved for high-performance and

high-load signals

Global routing resources

Clock Control signals


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FPGA I/O Blocks

The ring of I/O banks is used to interface theFPGA device to external components


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I/O Block (IOB) Structure

An IOB includes input and outputregisters, control signals, muxes andclock signals

Unused FPGA inputs should not be leftfloating


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I/O Block (IOB) Structure (cont)


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I/O Interface Standards

Single-ended and differentialoperational modes are typicallysupported

Single-ended standards

PCI, LVTTL

Differential standards LVDS, LVPECL


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IOB Configurable Feature

Pull-up or Pull-down Status ofunused I/O

I/O slew rate I/O drive strength

Supported I/O standards

Characteristic impedance termination


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FPGA Clock Resource

Clock manipulation can be implementedbased on Phase-locked loop (PLL)

Delay-locked loop (DLL) PLLs generate the desired phase or

frequency output by a voltage-controlled oscillator

PLLs are inherently analog circuits


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FPGA Clock Resource (cont)

DLLs access signals from a calibratedtapped delay line circuit internal to theFPGA to produce the desired clock

phase or frequency

DLLs are digital circuits


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PLL and DLL Clocking

Global Clocking and Regional


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Global Clocking and Regional

Clocking


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FPGA Memory

Two primary types of memory within FPGAs Distributed memory

Takes advantage of the fact that LUT elementsare implementation of SRAM memory blocks

Block memory

The implementation ofdedicated SRAM memoryblocks within the FPGA


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FPGA Memory (cont)

Memory elements embedded withinFPGA are usually refereed to as

Block RAM,

Embedded system block (ESB),

System RAM and

Content Addressable Memory (CAM)


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Advance FPGA Features

Enhanced clock features Intellectual property (IP)

Embedded processors (Hard and Soft)

Digital signal processing (blocks, tools,design flow)


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Generic FPGA Architecture


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Q & A

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