01 1 16 - Higher Education | Pearson

1

C H A P T E R 1

Structured Design Concepts

In this chapter we present basic definitions that relate tothe design process. It is necessary to introduce them now so that other concepts can beexplained. The reader should study them carefully in order to comprehend material introducedlater. It will also be useful to revisit this chapter as one proceeds through the text since the fullmeaning of the terms will only become clear through use and example.

1.1 THE ABSTRACTION HIERARCHY

In this section we present the abstraction hierarchy employed by digital designers. Abstractioncan be expressed in the following two domains:

Structural domain. A domain in which a component is described in terms of an inter-connection of more primitive components.

Behavioral domain. A domain in which a component is described by defining its input/output response.

Figure 1.1 shows structural and behavioral descriptions for a logic circuit, which detectstwo or more consecutive 1’s or two or more consecutive 0’s on its input X. The structuraldescription is an interconnection of gate and flip-flop primitives. The behavioral description isexpressed textually in a hardware description language (HDL).

An abstraction hierarchy can be defined as follows:

Abstraction hierarchy. A set of interrelated representation levels that allow a system tobe represented in varying amounts of detail.

Figure 1.2 shows a picture of a typical abstraction hierarchy. For each level i in the hierar-chy there exists a transformation to level i+1. The level of detail usually increases monotonicallyas one moves down in the hierarchy.

01_1_16.fm Thursday, January 13, 2000 9:22 AM

2 Chapter 1 • Structured Design Concepts

Structural Description

entity TWO_CONSECUTIVE isport(CLK,R,X: in BIT;Z: out BIT);

end TWO_CONSECUTIVE;

architecture DATAFLOW of TWO_CONSECUTIVE issignal Y1,Y0: BIT;

beginSTATE: block((CLK = '1'and not CLK'STABLE) or R = '0')begin

Y1 <= guarded '0' when R = '0' else X;Y0 <= guarded '0' when R = '0' else '1';

end block STATE;Z <= Y0 and ((not Y1 and not X) or (Y1 and X));

end DATAFLOW;

Behavorial Description

Figure 1.1 Structural and behavioral descriptions of a sample circuit.

Figure 1.2 Abstraction hierarchy.

V


The Abstraction Hierarchy 3

This book uses a design hierarchy that has six levels: silicon, circuit, gate, register, chip,and system. Table 1.1 illustrates this hierarchy. The silicon level is the lowest level in the hierar-chy, the system level the highest. One can represent a design at any of these levels. As onemoves down in the hierarchy, one is closer to a physical implementation and the design repre-sentation is less abstract. Correspondingly, the amount of detail required to represent a designincreases as one descends in the hierarchy. As will be emphasized throughout the text, it isimportant that a particular design activity be carried out at a level which has sufficient but notexcessive detail. A level with insufficient detail yields inaccurate results; whereas, a level withexcessive detail can make the design activity too expensive.

Table 1.1 shows the nature of this hierarchy in terms of the structural primitives andbehavioral representation for each level. Structural primitives are interconnected to form a struc-tural model at a given level. Figure 1.3 shows examples of the structural primitives at each level.The behavioral representation is the textual or pictorial form of a device’s I/O response at thatlevel.

At the lowest level, the silicon level, the basic primitives are geometric shapes that repre-sent areas of diffusion, polysilicon, and metal on the silicon surface. The interconnection ofthese patterns models the fabrication process from the designer’s point of view. Behavioraldescription at this level are the physical equations that describe electron and hole motion in elec-trical materials. At the next level up, the circuit level, the representation is that of an interconnec-tion of traditional passive and active electrical circuit elements: resistors, capacitors, and bipolarand MOS transistors. The interconnection of components is used to model circuit behavior interms of voltage and current. The behavioral content at this level can be expressed in terms ofdifferential equations.

The third level up, the gate level, has traditionally been the major design level for digitaldevices. The basic primitives are the AND, OR, and INVERT operators and various types offlip-flops. Interconnection of these primitives forms combinational and sequential logic circuits.Boolean equations define the behavior at this level.

The level above the gate level is the register level. Here the basic primitives are such thingsas registers, counters, multiplexers, and ALUs. These primitives are sometimes referred to asfunctional blocks. They also correspond to VLSI design macros. Thus, this level is also referredto as the functional or macro level. Although the register-level primitives can be expressed in

Table 1.1 Design abstraction hierarchy.

Level ofDetail

Behavioral DomainRepresentation Structural Domain Primitive

System Performance specifications (English) Computer, disk, unit, radar

Chip Algorithm Microprocessor, RAM, ROM, UART, par-allel port

Register Data flow Register, ALU, COUNTER, MUX, ROM

Gate Boolean equations AND, OR, XOR, FF

Circuit Differential equations Transistor, R, L, C

Layout/silicon Equations of electron and hole motion Geometrical shapes



terms of an interconnection of gates, when working at this level, one does not take this view-point. Register-level primitives are expressed in terms of truth tables and state tables; thus, thesetwo forms can be used to represent the behavioral content at this level. Behavioral descriptions atthis level are termed data flow, i.e., they reflect the way data is actually distributed in a realimplementation. In this book, we will show how these data flow descriptions can be imple-mented in a hardware description language.

The level above the register level is the chip level. At this level, the structural primitivesare such things as miroprocessors, memories, serial ports, parallel ports, and interrupt control-lers. Although chip boundaries are typically the model boundaries, other situations are possible.

Figure 1.3 Examples of structural domain primitives.

SILICON LEVEL

S

V+

P

D

D

G

G

S

VoutVin

Inverter

CIRCUIT LEVEL

S

R

Q

Q

S

R

Q

Q

GATE LEVEL

REG

MUXREG

INC

Select

CLK B

CLK A

REGISTER LEVEL

Microprocessor

RAM

ParallelPort

USART

InterruptController

8

8

8

CHIP LEVEL

A/B

Computer

IMU

RADAR

C/D

SYSTEM LEVEL


Textual vs. Pictorial Representations 5

For example, collections of chips, which together form a single functional unit, can be modeledas a single entity. Or alternatively, sections of a chip design could be modeled as separate entitiesduring this design phase. The key aspect is that a large block of logic is to be represented inwhich long and frequently convergent data paths from inputs to outputs must be modeled. In thebehavioral domain, at each level in the hierarchy, the primitives are behavioral descriptionswhich are not structural models that are created from more basic primitives. Each primitive is adistinct model entity. Thus, if a serial I/O port (UART) is to be modeled, the model is not createdby interconnecting simpler functional models of such things as registers and counters—theUART itself is the basic model entity. Behavioral domain models are important to system manu-facturers who buy a chip from another manufacturer but have no knowledge of its proprietarygate-level structure. Chip level models of complicated circuits are viewed as Intellectual Prop-erty (IP) and are frequently sold by one company to another. The behavioral content of a chip-level model is defined in terms of the I/O response of the device—the algorithm that the chipimplements. In this book, a hardware description language is used to code these algorithmicdescriptions.

The top level in the structural hierarchy is the system level. The primitive elements of thislevel are computers, bus interface units, disk units, radar units, etc. The behavioral content ofthis level is frequently expressed in terms of performance specifications, which give, for exam-ple, the MIPS rating (million instructions per second) of a processor or the bandwidth in bits persecond of a bus, or use a statistical model to determine the percent utilization of a part of the sys-tem. If a deterministic model is used at this level, it employs very high-level data types to repre-sent information being passed between systems. For example, if a radar system were modeled,information of type "frequency" would be passed between units in the system.

1.2 TEXTUAL VS. PICTORIAL REPRESENTATIONS

Design representations can be either pictorial or textual. Figure 1.1 shows a pictorial logic sche-matic for the circuit, which detects two consecutive 1’s or two consecutive 0’s (referred to asTWO_CON). Figure 1.4 shows a block diagram, a state diagram, a timing diagram, a state table,state assignment, and truth tables (Kmaps) for the same circuit.

These are all examples of pictorial forms. Common textual methods of representation arenatural languages (e.g., English), equations (e.g., Boolean or differential), and computer lan-guages. In this text we use a specialized computer language called a hardware description lan-guage, which can be defined as follows:

Hardware description language. A high-level programming language with specializedconstructs for modeling hardware.

The behavioral description in Figure 1.1 illustrates a hardware description language textualdescription for TWO_CON.

An important consideration in developing a design process is whether to use pictures ortext. Historically, pictures have been the preferred representation for digital design, i.e., block,timing, and logic diagrams (schematics) were the principal forms of representation. However,with the advent of hardware description languages, textual design descriptions have gained inpopularity. From inspecting Figures 1.1, 1.3, 1.4, and Table 1.1, one can see that structural



descriptions are primarily pictorial, and that behavioral representations are primarily textual.Some exceptions to this classification scheme are state tables, state diagrams, and timing dia-grams, which are pictorial but represent behavior. As to the general question of when picturesshould be employed or when text should be used, one can make the following generalization:Text is better for representing complex behavior; pictures are better for illustrating interrela-tionships. Excessive use of either text or pictures results in a loss of perspective, i.e., “one cannotsee the forest for the trees.” Thus, real design systems balance the use of text and pictures—thisis the approach we use in this text.

Truth Tables (Kmaps)

Figure 1.4 Pictorial representations of logic circuits.

Block Diagram State Diagram

Timing Diagram

X0 1

00 0 101 0 111 0 110 - -

Y1

X0 1

00 1 101 1 111 1 110 - -

Y2

X0 1

00 0 001 1 011 0 110 - -

Z

X0 1

S0 S1/0 S2/0S1 S1/1 S2/0S2 S1/0 S2/1

State Table

codey1y0

S0 00S1 01S2 11

StateAssignment

codey1y0

codey1y0

codey1y0


Types of Behavioral Descriptions 7

1.3 TYPES OF BEHAVIORAL DESCRIPTIONS

Behavioral descriptions in hardware description languages are frequently divided into two types:algorithmic and data flow.

Algorithmic. A behavioral description in which the procedure defining the I/O responseis not meant to imply any particular physical implementation.

Thus, an algorithmic description is merely a procedure or program written to model the behaviorof a device, to check that it is performing the correct function, without worrying about how it isto be built.

Data flow. A behavioral description in which the data dependencies in the descriptionmatch those in a real implementation.

Data flow descriptions show how data moves between registers. Figure 1.1 gave a data flowdescription for the circuit which detects two or more consecutive 1’s or two or more consecutive0’s. Figure 1.5 shows an algorithmic description for the same circuit.

Architecture ALGORITHMIC of TWO_CONSECUTIVE istype STATE is (S0,S1,S2);signal Q: STATE := S0;

beginprocess(R,X,CLK,Q)begin

if (R'EVENT and R = '0') then --reset eventQ <= S0;

elsif (CLK'EVENT and CLK = '1') then --clock eventif X = '0' thenQ <= S1;

elseQ <= S2;

end if;end if;If Q'EVENT or X'EVENT then --output functionif (Q=S1 and X='0') or (Q=S2 and X='1') thenA <= '1';

elsez <= '0';

end if;end if;

end process;and ALGORITHMIC;

Figure 1.5 Algorithmic description of the example circuit in Figure 1.1.



1.4 DESIGN PROCESS

We will describe a structured design process in this text beginning with the following defini-tions.

Design. A series of transformations from one representation of a system to another untila representation exists that can be fabricated.

Our approach to design involves synthesis, which the dictionary defines as “the combining ofabstract entities into a single or unified entity.” Thus, to synthesize is “to put somethingtogether.” For our context we make a more specialized definition.

Synthesis. The process of transforming one representation in the design abstraction hier-archy into another representation.

Each step in the design process is referred to as a synthesis step. Since the design process usuallystarts in the behavioral domain at a high level and ends in the structural domain at a low level,each synthesis step is a transformation from level i to level j with i≤ j. Therefore, what we are“putting together” is a representation of a design at level j. The representation at level i is used asa guide in the synthesis process, in that the implementation at level j must implement the samefunction as that at level i. In most cases, j=i+1, or j=i, i.e., either the levels are adjacent, or thetransformation is from the behavioral domain to the structural domain at the same level. How-ever, there are situations where levels are skipped in the synthesis process.

Figure 1.6 A typical design track.


Structural Design Decomposition 9

The design cycle consists of a series of transformations (synthesis steps). Common synthe-sis steps include:

1. Transformation from English to an algorithmic representation (natural language syn-thesis).

2. Translation from an algorithmic representation to a data flow representation (algorith-mic synthesis) or to a gate level representation (referred to in the industry as behavioralsynthesis). Note: In this second case one moves from the behavioral to the structuraldomain.

3. Translation from data flow representation to a structural logic gate representation (logicsynthesis). Note: In this process one also moves from the behavioral to the structuraldomain and skips the register level.

4. Translation from logic gate representation to layout representation (layout synthesis).In this synthesis step the circuit level is skipped. This completes the synthesis processsince the layout information can be fabricated.

The complete design cycle is sometimes referred to as design synthesis.Figure 1.6 shows a typical design track through the design hierarchy. The track begins in

the behavioral domain and descends through the system and chip levels to the register level. Atthe register level the transformation is made from a behavioral data flow representation at thislevel to a structural gate level description. Or, the transformation can be made directly from analgorithmic representation to a structural gate level description. This gate-level description isthen transformed to the circuit level or perhaps directly to the layout or silicon level.

The design cycle steps can be carried out automatically in all stages in descending order,except the first, which is currently an active area of research. It is the purpose of this book toshow students and design engineers how to carry out the steps themselves, and therefore, under-stand which functions are actually performed by automatic synthesis programs. Also, in someengineering organizations, manual transformations are still the only means employed.

1.5 STRUCTURAL DESIGN DECOMPOSITION

The structural form of the design hierarchy implies a design decomposition process. This isbecause at any level we choose, the system model is composed by interconnection of the “prim-itives” defined for that level. In the structural domain, primitives are defined in terms of inter-connections of primitives at the next lower level. Thus, as shown in Figure 1.7 a design can berepresented as a tree, with the different levels of the tree corresponding to levels in the abstrac-tion hierarchy. Eventually, even in structural models, primitives at the leaves of the tree must berepresented by behavioral models.

As defined above, a behavioral model is a primitive model in which the operation of themodel is specified by a procedure as opposed to redefining it in terms of other components.Since a behavioral model can exist at any level in the design hierarchy, different parts of thedesign can have behavior specified at different levels. In Figure 1.7(a) the design tree is “full,”and all behavior is, therefore, specified at the same level. In Figure 1.7(b) a design that has theform of a partial tree is shown, where behavior is specified at different levels. This situation is



encountered because one frequently wants to evaluate the relationships between system compo-nents before they have all been completely designed. For example, multilevel simulation can beused to evaluate the interaction of one component whose design has reached the gate level withother components whose design is currently still at the system level. Thus, it is not required thatall system components be specified at the gate-level in order to evaluate the gate level design ofa specific component. The checking is done by employing a simulation in which the behavioralcontent of the component models occurs at different levels in the hierarchy. In fact, it may beimpossible to fully simulate a large system with all components modeled at the gate level. Sucha simulation might take months to execute using current gate-level simulators. Instead, onewould do multiple simulations, with different sets of components modeled at the gate level ineach simulation. The other components would be modeled at the systems level. These simula-tions would take much less time to execute because system level simulations are more efficient.A few hundred simulations with each simulation taking several hours is preferable to one giantsimulation that takes several months.

Two concepts related to the design tree are those of top-down and bottom-up design. Herethe word “top” refers to the root of the tree; whereas, “bottom” refers to the leaves. In top-downdesign, the designer begins with knowledge of only the function of the root. He or she then par-titions the root into a set of lower-level primitives. Each of these lower-level primitives is thenpartitioned into an interconnection of primitives at still lower levels. This process continues untilthe leaf nodes of the design are reached. At the leaf nodes, the models are always behavioral. Animportant point to make about top-down design is that the partitioning is optimized at each levelaccording to some objective criterion, e.g., cost, speed, and chip area. The partitioning is notconstrained by “what's available.”

Figure 1.7 Structural decomposition.


The Digital Design Space 11

The term bottom-up design is somewhat of a misnomer in that the process of design stillbegins with the definition of the root, but in this case the partitioning is conditioned by what isavailable. Lower parts of the tree will have been designed previously, perhaps on another project,and the designer is constrained (perhaps ordered!) to use them. Top-down design usage appearsto be the most ideal situation, but its disadvantage is that it produces components that are not“standard,” thus, increasing the cost of the design. Bottom-up designs are more economical, butthey may not meet the objective performance criterion as well as top-down designs. Most realdesigns are a combination of top-down and bottom-up techniques.

A final concept related to the hierarchy is that of a design window. By this we mean arange of levels over which the designer works in developing a design-tree structure. The VLSIchip designer’s window extends over the range of silicon, circuit, gate, register, and chip levels.The computer system designer, on the other hand, is currently concerned with a window consist-ing of the gate, register, chip, and system levels. Thus, the designer selects the window which isappropriate to his or her design activity and works at those levels of abstraction, which providethe necessary information for that activity, without involving unnecessary detail. CAD systemsused to support design should allow easy movement between levels in the design window.

1.6 THE DIGITAL DESIGN SPACE

In the preceding discussion on top-down design, we said that partitioning was carried out inorder to meet some objective criteria. These criteria are the major factors one has to consider inarriving at a design. These factors can be considered to be dimensions in a space. Some usefuldimensions for the Digital Design Space are: speed, chip area, and cost. Figure 1.8 illustratessuch a design space. Various designs have different tracks through the space as they evolve. Thedesigner trades off one factor for another. For example, in his quest for speed he may increasethe chip area and cost of a design. Figure 1.9 gives a concrete example of this. Circuits A and Bimplement the same logic function. Circuit A uses fewer gates (area) than Circuit B but isslower. Circuit B is faster than Circuit A but requires more gates (area). Thus we are trading offarea for speed.

Figure 1.8 A typical design space.



PROBLEMS

1.1 Draw a structural model of a 16-bit ripple carry adder as an interconnection of full adders.Develop a behavioral description of the 16-bit adder in C, C++, or JAVA.

1.2 Draw a gate-level diagram of a full adder in terms of AND, OR, and INVERT primitives. Con-sult books on electronics and VLSI design and develop a CMOS circuit for the adder in termsof transistors, resistors, and capacitors. Compare the two circuits as follows:

a. Count the number of primitives and wires required for each representation.b. Simulate both circuits on the same computer using a logic simulator and SPICE. Drive

both circuits with all possible 8-input patterns. Compare simulation times.1.3 Track the representation of a digital system through the abstraction hierarchy. Use the small

computer example in Morris Mano’s book, Computer System Architecture, 2nd Edition(Englewood Cliffs: Prentice Hall, 1982). Track the description of this system through the hier-archy as follows:

a. Develop a one page, single-spaced, English, system-level description of the machine.b. Using your favorite graphics package, draw a chip-level diagram of a system that uses

the Mano machine, RAM memory, and an I/O logic section.c. Draw a complete register-level diagram of the Mano machine.d. Using gates and J-K flip-flop primitives, draw a complete gate-level diagram of the Pro-

gram Counter.e. Select a gate from the Program Counter, and draw its CMOS circuit equivalent.f. Draw the layout for the gate you described in the previous step.

Which of the representations you developed are structural and which are behavioral?1.4 Figure 1.10 shows a structural model of a simple RC series circuit. Write a behavioral descrip-

tion which involves current, i(t). Plot i(t).1.5 Shown is a behavioral description for a gate-level circuit.

F = AB or or (1.1)

Develop two different, structural gate-level models that implement this function.1.6 A textual description of the fabled family relationship from N. Wirth’s Algorithms + Data

Structures = Programs, (Englewood Cliffs: Prentice Hall, 1976) follows:

I married a widow (let’s call her W) who had a grown-up daughter (call her D). Myfather (F), who visited us quite often, fell in love with my stepdaughter and marriedher. Hence, my father became my son-in-law and my stepdaughter became my

Figure 1.9 An example of a design space trade-off.

CD EF



mother. Some months later, my wife gave birth to a son (S1), who became thebrother-in-law of my father, as well as my uncle. The wife of my father, that is, mystepdaughter, also had a son (S2). Question: Am I my own grandfather?

Draw a pictorial representation of the relationship by means of a directed graph in which thenodes are the persons’ names and the arcs are the relationships between persons, e.g., “fatherof.” Which representation is easier to understand? Can you answer the question?

1.7 Figure 1.11 is a logic diagram of a counter circuit from Morris Mano’s Computer SystemArchitecture, 2nd Edition (Englewood Cliffs: Prentice Hall, 1982). Outline a behavioraldescription in either C or C++ which describes the behavior. Which description gives a morereadily understandable description of the circuit function?

1.8 Figure 1.12 shows a system interface between two devices: a sending device (Device 1) and areceiving device (Device 2). The interface between the two devices consists of a DATA lineand three control signals READY, VALID, and ACCEPT. A communications protocol betweentwo asynchronous devices functions as follows:

a. Device 2 asserts READY.b. Device 1 detects the positive going change on READY, and places data on the DATA line

and asserts VALID.c. Device 2 detects the positive going change on VALID, copies the data and resets

READY, and asserts ACCEPT.Draw a timing diagram for DATA, READY, VALID, and ACCEPT. Use arrows between sig-nals to show how one signal transition triggers another.

1.9 Given the following algorithmic description:

for I=1 to 3 loopA(I) = B(I) + C(I)D(I) = E(I) * A(I)

end for;

Draw a data-flow graph in which the nodes are operations (+,*) and the arcs are inputs or com-puted values.

1.10 From your own experience, describe a design synthesis process that you are familiar with.Identify distinct synthesis steps, abstraction levels, and whether a representation is behavioralor structural. Draw a design track similar to Figure 1.6.

1.11 Design decomposition implies what kind of VHDL model?1.12 Compare top-down and bottom-up design in two areas (a) cost and (b) whether the design is

optimum or not.1.13 Explain the difference between top-down and bottom-up design. What is the main advantage

and disadvantage of each approach?

Figure 1.10 RC circuit.

R = 1k

C = 1 uf+5 v i(t)



Figure 1.11 Counter circuit.

Figure 1.12 Interface protocol.

Device 1 Device 2

READY

ACCEPTDATA

DVALID



1.14 Characterize microprocessor system design and design with application-specific integrated cir-cuits (ASICs) as being top-down or bottom-up. Explain your answer.

1.15 Explain how top-down and bottom-up design concepts can be used for software design.1.16 Use the design of a 16-bit adder to illustrate trade-offs in the design space.

a. Design a 16-bit carry ripple adder.b. Design a 16-bit carry look-ahead adder.c. Compare gate counts and delay for the two adder implementations.d. Develop a general expression for the gate count and delay for the two adder implementa-

tions that is a function of n, the input word size to the adder.


01 1 16 - Higher Education | Pearson

Documents

Transcript of 01 1 16 - Higher Education | Pearson