file · Web viewFigure 2.2, Subrack Controller (DFEC) Status Word. 7. 2.1.2 Read from Subrack...

Fermi National Accelerator Laboratory

D-Zero Detector Central Fiber Tracker (CFT) Axial ProjectReadout Electronics

Central Tracker Trigger (CTT) Mixer SystemDiagnostic Procedures

Date: April 1st, 2002Revision Date: March 18th, 2003

N. George Wilcer, S. Marco Rapisarda, M. Tomoto

Document # ESE-D0-020401

Central Tracker Trigger (CTT) Mixer System Diagnostic Procedures March 18th, 2003

Page 1


Table of contents

1. Introduction........................................................................................................................................52. Subrack Controller..............................................................................................................................6

Figure 2.1, Subrack controller simplified block diagram.............................................................................62.1 Use of board Controller 1553 Interface............................................................................7

2.1.1 Read Subrack Controller Status Word..............................................................................7Table 2.1, Read Subrack Controller status word..........................................................................................7Figure 2.2, Subrack Controller (DFEC) Status Word...................................................................................7

2.1.2 Read from Subrack Controller Memory...........................................................................7Table 2.2, Read from Subrack Controller memory......................................................................................7

2.1.3 Write to Subrack Controller Memory...............................................................................8Table 2.3, Write to Subrack Controller memory..........................................................................................8

2.1.4 Writing and executing a sequence of Subrack Controller Commands.............................8Table 2.4, Write and executing a sequence of Subrack Controller commands............................................8

3. Diagnostic Procedure..........................................................................................................................93.1 Use of slow monitoring serial bus....................................................................................9

Table 3.1, Slow Monitoring information read back procedure....................................................................9Figure 3.1, Mixer Board Slow Monitoring information...............................................................................9Table 3.2, Example of Board Status Block read back................................................................................10Figure 3.2, Slow Monitoring Diagnostic Procedure flow...........................................................................11

4. Procedures........................................................................................................................................124.1 Board procedures............................................................................................................12

4.1.1 Read a board-controller register......................................................................................12Table 4.1, Read a Board Controller register...............................................................................................12

4.1.2 Write to a board-controller register.................................................................................12Table 4.2, Write to a Board Controller register..........................................................................................12Figure 4.1, broadcast control for writes operations....................................................................................13

4.1.3 Board devices access structure........................................................................................13Figure 4.2, Board device access structure..................................................................................................13

4.1.4 Read device registers......................................................................................................14Figure 4.3, Read from device registers.......................................................................................................15

4.1.5 Write to device registers.................................................................................................16Figure 4.4, Write to device registers...........................................................................................................18

4.1.6 Board reset......................................................................................................................19Table 4.5, Mixer board reset command sequence......................................................................................19Figure 4.5, Mixer board reset.....................................................................................................................19

4.1.7 Reset Board Controller History Information..................................................................19Figure 4.6, Reset board controller history information..............................................................................19

4.1.8 Read Mixer Board configuration status and device's firmware ID.................................20Figure 4.7, Read configuration status and device's firmware ID................................................................20

4.1.9 Erase Mixer Board Configuration...................................................................................20Figure 4.8, Erase mixer board configuration..............................................................................................20

4.1.10 Configure mixer board....................................................................................................21Figure 4.9, configure mixer board..............................................................................................................21Table 4.6, Configuration Files denomination.............................................................................................21Table 4.7, Mixer# and Subrack slot#..........................................................................................................22

4.1.11 Read board controller firmware revision date and board serial number.........................22Figure 4.10, Read board controller firmware revision date and board serial number................................22

4.1.12 Read/Write test................................................................................................................23

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Figure 4.11, Read/write test........................................................................................................................234.1.13 Reset Board History Information....................................................................................23

Figure 4.12, Reset Board History Information...........................................................................................234.1.14 Taking a snapshot of Mixer Board status.......................................................................24

Figure 4.13, Mixer Board status snapshot..................................................................................................244.2 Input Links procedures...................................................................................................25

4.2.1 Read input links error status...........................................................................................25Figure 4.14, Read input links error status...................................................................................................25

4.2.2 Read input links status....................................................................................................26Figure 4.15, read input links status.............................................................................................................26

4.2.3 Reset Mixer Board input links status history..................................................................27Figure 4.16, Reset input links status history...............................................................................................27

4.2.4 Input Links Control.........................................................................................................28Figure 4.17, Input Links control procedure................................................................................................28Figure 4.18, Input Links Control register...................................................................................................28

4.2.5 Input Links Control bits masking...................................................................................29Figure 4.19, Input Link Control Bits Mask Register..................................................................................29Figure 4.20, Command bits generation, timing and denomination............................................................29Table 4.8, Example of command sequence to mask control bits on the input links...................................30Figure 4.21, input links control bits masking.............................................................................................31

4.2.6 Monitoring mode 7 masking...........................................................................................32Figure 4.22, monitoring mode 7 masking...................................................................................................32

4.2.7 Input Links Control bits status........................................................................................33Figure 4.23, read input links control bits status..........................................................................................33

4.2.8 Embedded Command Bits Status....................................................................................34Figure 4.24, Read Embedded Command Bits status..................................................................................34

4.3 Backplane Devices Procedures.......................................................................................354.3.1 Reset Backplane Devices History...................................................................................35

Figure 4.25, reset backplane devices history..............................................................................................354.3.2 Readback Mixer Board clock/SYNC status....................................................................36

Figure 4.26, Read Clock/SYNC Status and History...................................................................................364.3.3 Reset Mixer Board clock/SYNC status history..............................................................36

4.4 Output links devices procedures.....................................................................................374.4.1 Output link FIFO read.....................................................................................................37

Figure 4.27, Read content of an output link FIFO......................................................................................374.4.2 Output link FIFO Write..................................................................................................38

Figure 4.28, Write content of an output link FIFO.....................................................................................384.4.3 Output Link FIFO reset...................................................................................................384.4.4 Output link FIFO Configuration.....................................................................................39

Figure 4.29, Output link FIFO configuration.............................................................................................394.4.5 Triggering of Output Links FIFO...................................................................................40

Figure 4.30, Triggering of Output Link FIFO............................................................................................404.4.6 Use of Output Links FIFOs.............................................................................................40

Figure 4.31, Use of Output Links FIFOs....................................................................................................404.4.7 Reset Output Links History Information........................................................................41

Figure 4.32, Reset output links history information...................................................................................414.4.8 Output links Control Bits Masking.................................................................................42

Table 4.9, Example of command sequence to mask control bits on the output links.................................42Figure 4.33, Output links control bits masking..........................................................................................43

4.4.9 Output Links Control......................................................................................................44Figure 4.34, Output links control................................................................................................................44

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4.5 System procedures..........................................................................................................454.5.1 Mixer System reset.........................................................................................................45

Figure 4.35, Mixer System reset.................................................................................................................454.5.2 Mixer System Extended Reset........................................................................................46

Figure 4.36, Mixer System extended reset.................................................................................................464.5.3 Mixer System power-up initialization............................................................................47

Figure 4.37, Mixer System Power-up initialization....................................................................................474.5.4 Mixer System configuration erasing...............................................................................47

Figure 4.38, Mixer System configuration erasing......................................................................................474.5.5 Broadcast configuration of the mixer system.................................................................48

Figure 4.39, broadcast configuration of the mixer system.........................................................................485. Use of the LEDs Monitoring Mode..................................................................................................49

Figure 5.1, Front panel LEDs and LEDs monitoring mode.......................................................................49Figure 5.2, Mode of Operation register......................................................................................................49Figure 5.3, Monitoring Mode Register.......................................................................................................50Figure 5.4, Monitoring Status Registers.....................................................................................................50Figure 5.5, Monitoring Status History Registers........................................................................................50Table 5.1, Monitoring Mode change..........................................................................................................51Figure 5.6, Monitoring Mode change.........................................................................................................51Figure 5.7, Enable/Disable LEDs to show monitoring mode.....................................................................51Figure 5.8, Read monitoring status and status history................................................................................52

6. Problem reporting.............................................................................................................................536.1 Report a problem to mixer system support.....................................................................536.2 Report a problem to AFE system support.......................................................................53

7. References........................................................................................................................................54

Page 4


1. Introduction

This document describes the use of the diagnostic features and provides the recommended procedures to operate the mixer system.

More information on the D0 CTT Mixer System is provided in a separate document [Ref.4d].

Page 5

R e m o teTe rm in a lA d d ress

15 5 3 In terface

a d d ress F u nc tio n0 0 0 0 h0 0 0 1 h

0 0 7 F h

D F E C sta tu s w o rdco m m a nd b u ffer

S u ba d d re ss

1 6 (1 0 h )1 7 (11 h )1 8 (1 2 h )

a d d ress p o in te r (re ad /w r ite )d a ta re g is te r (rea d /w r ite )D F E C S ta tu s W o rd (re ad ), ex ec u te co m m a n d s (w r ite )

0 0 8 0 h

0 0 FA h0 0 F 9 h

0 1 0 0 h0 0 F F h

0 1 F F h

b o a rd sta tu s b lo c k

se c to r b u ffe r

M em o ry m ap

T h e ad d re s s p o in te ris in c rem e n ted

e ac h tim e th e d a tare g is te r is a cc esse d

128MB

MEMORY CARDCompactFlash TM

B ackp lan eS low M o n ito rin g

In te rface

B ackp lan eG ene ra l P u rp ose B u s

In te rface

g e n e ra l p u rp o se m e m o ry

M icro co n tro lle r


2. Subrack Controller

Details provided in separate document [Ref. 4d].

Figure 2.1, Subrack controller simplified block diagram.

Page 6


2.1 Use of board Controller 1553 Interface

2.1.1 Read Subrack Controller Status Word

Table 2.1 provides the command sequence to read the Subrack Controller (DFEC) status word. The status word contains the information on the current status of the subrack controller (BUSY, HALT, IDLE) and the type of error in the case an error occurred in executing the last command.

Command to 1553 Remote Terminal

1553 Remote Terminal

subaddress

Number of

wordsNotes

Read 18 (0x12) 1 Readback Subrack Controller Status Word.

Table 2.1, Read Subrack Controller status word.

Figure 2.2, Subrack Controller (DFEC) Status Word.

2.1.2 Read from Subrack Controller Memory



subaddress

Number of

wordsNotes

Write 16 (0x10) 1 Write the memory address in the subrack controller address pointer register.

Read 17 (0x11) nRead the subrack controller data register. The content of the address pointer register is automatically incremented each time the data register is accessed.

Table 2.2, Read from Subrack Controller memory.

Page 7

| 1 5 1 4 1 3 1 2 | 11 1 0 9 8 | 7 6 5 4 | 3 2 1 0 |

D F E C S ta tu s W ord

F U L : C o m p ac t F la sh F U L L

H A LT: co m m an d o r co m m an d a rg u m en t e rro r

B U S Y: p ro cess in g co m m an d sID L E : co m m an d s e x ecu ted w ith n o e rro rs

2.1.3 Write to Subrack Controller Memory



subaddress

Number of

wordsNotes

Write 16 (0x10) 1 Write the memory address in the subrack controller address pointer register.

Write 17 (0x11) nWrite to the subrack controller data register. The content of the address pointer register is automatically incremented each time the data register is accessed.

Table 2.3, Write to Subrack Controller memory.

2.1.4 Writing and executing a sequence of Subrack Controller Commands

Command to 1553 Remote

Terminal

1553 Remote

Terminal subaddress

Number of

wordsData Notes

Write 16 (0x10) 1 0x0080 Write the address of the top location of the command buffer in the address pointer register.

Write 17 (0x11) n

<command 1>

<…>

<command m>

Write to the subrack controller data register. The data will be written in the command buffer starting from location 0x0080.

Write 17 (0x11) 1 0xA1

Write to the subrack controller data register.0xA1 is the “End of List” command and must always be placed at the end of a command sequence to stop the subrack controller from fetching and executing commands.

Write 16 (0x10) 1 0x0080Optional step (command sequence verification) Write the address of the top location of the command buffer in the address pointer register.

Read 17 (0x11) n …Optional step (command sequence verification)Verify that the read back sequence matches the sequence of commands <command 1> … <command m>.

Write 18 (0x12) 1 0x00Write to subaddress 18 (0x12) to have the Subrack Controller to execute the command sequence stored in the command buffer.

Read 18 (0x12) 1 <status word>

Read back Subrack Controller status word.Verify the Subrack Controller status is IDLE or BUSY.Continue read back until the state is IDLE to confirm the execution of the entire sequence of commands without errors.

Table 2.4, Write and executing a sequence of Subrack Controller commands.

Page 8


3. Diagnostic Procedure

3.1 Use of slow monitoring serial bus

Detailed information on the mixer system subrack controller is provided in [Ref.1f].

The mixer board status information is continuously collected from the mixer boards by the Mixer System subrack controller over a custom serial bus. The information is stored in the subrack controller memory space and is made accessible through the MIL-STD-1553 Remote Terminal interface. The mixer board status information read back from each mixer board is shown in Figure 3.3.

Table 3.5 provides the command sequence to read back the slow monitoring board status information from the Mixer System subrack controller memory.

Figure 3.3 shows the information provided in the Mixer Board slow monitoring word, detailed description of the word is provided in a separate document [Ref.4d].



subaddress

Number of words Notes

Write 0x0080 16 (0x16) 1 Point the address pointer to the top of the Board Status Block memory space (0x0080-0x00F9)

Read 17 (0x11) 20Read back Board Status Block Memory. The first word provide the status information of the mixer board in slot# 2, the 20th word of the mixer board in slot# 21.

Table 3.5, Slow Monitoring information read back procedure.

Figure 3.3, Mixer Board Slow Monitoring information

Page 9

| 1 5 1 4 1 3 1 2 | 11 1 0 9 8 | 7 6 5 4 | 3 2 1 0 |

S lo w M o n ito r in g B u s R e g is te r: (R E A D )

L E D s M o n ito rin g M o d e (fro m M o n ito rin g M o d e reg is te r)

G lo b a l C lo ck /S Y N C E rro r ( )fro m B o a rd S ta tu s /C o ntro l re g is te r

B o a rd Ty p e ( )fro m B o a rd S ta tu s /C o n tro l re g is te rG lo b a l C lo ck /S Y N C E rro r h is to ry ( )fro m B o a rd S ta tu s /C o n tro l reg is te r


Subrack Controller Memory Address

(Board Status Block)

Mixer Subrack

Slot#Read back data Notes

0x0080 2 0xD22Cb1101_0010_0010_1100 The board type is 0xD (mixer board).

0x0081 3 0xD22Cb1101_0010_0010_1100 The board is fully configured (all 16 devices).

0x0082 4 0xD22Cb1101_0010_0010_1100

All the bit in the LED Status Register are high (the logic AND is ‘1’)

0x0083 5 0xD22Cb1101_0010_0010_1100

The board is in LED monitoring mode 12 (0xC, default at power up).

0x0084 6 0xFFFFb1111_1111_1111_1111

The board type is not correct (should always be 0xD => the board is not responding correctly or is missing.

0x0085 7 0xDE2Cb1101_1110_0010_1100

The board has a Global Clock/SYNC error => the board is not using the correct source for the global Clock/SYNC or the SYNC used doesn’t respect the correct protocol.

0x0086 8 0xDF2Cb1101_1111_0010_1100

Beside having a Global Clock/SYNC error as the board in slot #7 this board has also an input link error => at least one of the 16 input links has a clock/sync error.

0x0087 9 0xDE60b1101_1110_0110_0000

The board has a Global Clock/SYNC error, is in LED monitoring mode 0 (input links clock and DLL status), the bits in the LED Status registers are all high but there is a change in LED status reported in the LED Error Status History registers. No input link error is reported.

0x0088 10 0xD9CCb1101_1001_1100_1100

The board is not fully configured (READY bit is low).

… … … …

0x0093 21 0xDb1101_0000_0000_0000

Table 3.6, Example of Board Status Block read back.

Figure 3.4 shows the suggested diagnostic procedure flow. The flow is based on the information collected from the slow monitoring system; this data is used to define two levels of error (critical and severe) and one level of warning (alert). The flow diagram reports for each error and alert an ordered list containing, in order of precedence, the possible procedures to be used to investigate the problem. The procedures marked with an (+) are specified in this document.A critical error is defined as one that affects the system in disrupting both the data flow and the system diagnostic. A severe error is one that just disrupts the data flow and makes the data unreliable. Alerts are used to warn about the board being accessed, being operated in a mode which can impair the data flow and when errors are reported form the input links diagnostic.

Page 10


Figure 3.4, Slow Monitoring Diagnostic Procedure flow

Page 11

R ead b ack M ix er B o a rd S ta tu s

Is th e B o a rd Ty p e 0 x D ? C R IT IC A L E R R O RT h e b o ard is n o t re sp o n d in g

N o

Yes

1 ) Verify co m m u n ica tio n s a re a d d re ssed to th e co rre c t (M ix er) su b rac k2 ) Verify 1 5 5 3 c o m m u n ica tio n s a re o p era tio n a l3 ) Verify m ix e r su b rac k co n tro lle r is re sp o n d in g4 ) Verify sy s te m is p o w e red5 ) Verify b o a rd p resen ce6 ) R e se t M ix e r B o ard (+ )7 ) R e co n fig u re M ix e r S y stem (+ )8 ) R e cy c le sy s tem p o w e r9 ) R ep o rt p ro b lem to M ix e r S y stem su p p o rt (+ )

Is th e b o a rd R E A D Y ? C R IT IC A L E R R O RT h e b o ard is n o t co n fig u red

N o

Yes

1 ) a ) R ese t th e M ix er B o a rd (+ ) b ) R ea d bac k M ix er B o a rd F P G A s co n fig u ra tio n s ta tu s (+ ) c ) E ra se M ix e r B o a rd c o n fig u ra tio n (+ ) d ) R ec o nfig u re M ix er B o ard (+ )2 ) R e co n fig u re M ix e r S y stem (+ )3 ) R e cy c le S y s tem P o w er4 ) R ep o rt p ro b lem to M ix e r S y ste m su p p o rt (+ )

G lo b a l C lo ck /S Y N CE rro r?

S E V E R E E R R O RT h e b o ard is n o t o p e ra tin g w ith

th e co rrec t tim in g re fe ren cesN o

Yes

1 ) a ) R ead b ack M ix e r B o a rd c lo ck /S Y N C s ta tu s (+ ) b ) R ea d bac k M ix er B o a rd in p u t lin k s s ta tu s (+ ) c ) R ese t M ix e r B o a rd (+ )2 ) I f th e M ix e r B o ard is a s la v e b o a rd rep ea t p ro ced u re (1 ) fo r th e M ix e r S u b sy stem m aste r b o a rd3 ) I f th e re is a C lo ck /S Y N C e rro r o n in p u t lin k # 0 o f th e su b sy s tem m as te r b o a rd rep o rt th e p ro b le m to A F E S y stem su p p o rt (+ )4 ) R e p o rt p ro b lem to M ix er S y stem s u p p o rt (+ )

G lo b a l C lo ck /S Y N CE rro r H is to ry ?

S E V E R E E R R O RT h e b o ard h as b een

tem p o ra rily o p e ra t in g w ith in co rrec t tim in g re fe ren c es

N o

Yes

1 ) a ) R ead b ack M ix e r B o a rd c lo ck /S Y N C s ta tu s (+ ) b ) R ea d bac k M ix er B o a rd in p u t lin k s s ta tu s (+ ) c ) R ese t M ix e r B o a rd C lo ck /S Y N C sta tu s h is to ry (+ ) d ) R ese t M ix e r B o ard in p u t lin k s s ta tu s h is to ry (+ )2 ) I f th e M ix e r B o ard is a s la v e b o a rd rep ea t p ro ced u re (1 ) fo r th e M ix e r S u b sy stem m aste r b o a rd3 ) I f th e M ix e r B o ard reco rd ed C lo ck /S Y N C e rro r o n in p u t lin k # 0 o f th e su b sy ste m m aste r b o a rd rep o rt th e p ro b lem to A F E S y stem su p p o rt (+ )4 ) R e p o rt p ro b lem to M ix er S y stem s u p p o rt ( + )

N o n S tan d a rd M o d e o f O pe ra t io n ?

A L E RTT h e b o ard d ia g n o stic is b e in g

accessed o r th e b o a rd is o p era tin g in a m o d e w h ich

ca n im p a ir th e n o rm a ld a ta f lo wN o

Yes 1 ) I f th e b o a rd d iag n o stic is n o t b e in g acc essed re ad b ack M ix e r B o a rd s ta tu s (+ ) an d re s to re s tan d ard o p era t io n a l s ta tu s .2 ) R e se t th e M ix e r B o a rd (+ )3 ) R e p o rt p ro b lem to M ix er S y stem s u p p o rt (+ )

In p u t L in k s E rro r?A L E RT

A t le a s t o n e o f th e in p u t lin k sis m alfu n c tio n in g

N o

Yes

1 ) R e ad b ack M ix e r B o ard in p u t l in k s e rro r s ta tu s (+ )2

4 ) R e se t th e M ix er B o a rd (+ )5 ) To v er ify A F E -M ix e r lin ks in teg rity ru n th e A F E -M Ix e r lin k tes t (+ )6 ) R e p o rt p ro b lem to M ix er S y stem s u p p o rt (+ )

) R ead b ack M ix e r B o a rd in p u t lin k s s ta tu s o n fa ilin g lin k s (+ )3 ) R e p o rt p ro b lem to A F E S y stem su p p o rt (+ )

4. Procedures

4.1 Board procedures

4.1.1 Read a board-controller register

Subrack Controller command (0x) Notes

<22><00><offset><slot>

Read the content of the board controller register having address <offset> on the mixer board in slot <slot>.

<22>: subrack controller command "read byte from backplane".

<00>: unused byte.

<offset>: board register address, from 0x00 to 0x1F.

<slot>: mixer subrack slot number, from 0x02 to 0x15.

The read data byte will be available in the subrack controller General Purpose Memory at location 0x00FA.

Table 4.7, Read a Board Controller register

4.1.2 Write to a board-controller register

Subrack Controller command (0x) Notes

<12><data><offset><slot>

Write the byte <data> to the board controller register having address <offset> on the mixer board in slot <slot>.

<12>: subrack controller command "write byte to backplane".

<data>: data byte to be written.

<offset>: board register address, normal addressing range from 0x00 to 0x1F.

The most significative three bit of the <offset> byte are using for broadcasting control (see Figure 4.5).


Table 4.8, Write to a Board Controller register

Page 12

7 6 5 4 | 3 2 1 0

R eg is te r A d d re ssB ro ad c as tin g co n tro l0 0 0 : n o rm a l a d d re ss in g0 0 1 : S u b sy stem /S u p e rsec to r ad d re ssin g (a ll th e b o a rd s in a S u b sy stem /S u p e rsec to r)0 1 0 : M ix e r b o a rd # ad d ress in g (a ll b o a rd w ith th e sam e p o s itio n in a S u b sy stem /S up ersec to r)1 0 0 : S u b rac k b ro a d castin g (a ll th e b o a rd s in th e m ix e r sy s tem )

< o ffse t>

| 7 6 5 4 | 3 2 1 0 |

D ev ic e S tatu s /C o n tro l R eg is te rA d dress: ox 0 1 (R E A D /W R IT E )

D E V IC E S E L E C T (re ad /w rite )

| 7 6 5 4 | 3 2 1 0 |

D ev ic e A c ce ss A d dre ss R e g is te r. A d dress : o x0 7 (R E A D /W R IT E )

D ev ice A ccess A d d re ss

| 7 6 5 4 | 3 2 1 0 |

D e v ice A cc e ss D ataA d d re ss : o x 0 8 (R E A D /W R IT E )

D ev ic e A c ce ss D a ta

D ev ic e 0

D ev ic e 1

D ev ic e N

D ev ice 1 5

S E L

M

N

R eg is te r1

R eg is te rM

R eg is te r0

| 7 6 5 4 | 3 2 1 0 |

M o d e o f O p era tio n R e g is te rA d dress:o x 0 4 (R E A D /W R IT E )

E n ab le D e v ice A c cess R eg is te rs


The write operation can also be targeted to a particular set of mixer boards using the broadcasting control (see Figure 4.5).

Figure 4.5, broadcast control for writes operations

4.1.3 Board devices access structure

Figure 4.6, Board device access structure

Page 13

4.1.4 Read device registers

Step# Subrack Controller command (0x) Notes

1 <22><00><04><slot>

Read the content of the Mode of Operation register.


<00>: unused byte.

<04>: <offset> byte, Mode of Operation register address.


The read data byte <MOreg_data> will be available in the subrack controller General Purpose Memory at location 0x00FA.

2 <12><data_a><04><slot>

Enable Device Access Registers (default is disabled) in the Mode of Operation register.


<data_a>: <MOreg_data> OR <04>.Is the logic OR of the byte obtained from the previous operation (<MOreg_data>) and the mask used to enable the Device Access Registers (<04>).

<04>: <offset> byte, Mode of Operation register address. The most significative three bit of the <offset> byte can be used for broadcasting control (see Figure 4.5).


3 <12><0x0,device><01><slot>

Point the Device Status/Control Register to a specific device. No masking is required.


<0x0,device>: 0x0 followed by 4 bit device address, from 0x00 to 0x0F.

<01>: <offset> byte, Device Status/Control register address. The most significative three bit of the <offset> byte can be used for broadcasting control (see Figure 4.5).


4 <12><register><07><slot>

Point the Device Access Address Register to a specific register inside the device. No masking is required.


<register>: Device’s internal register address.

<07>: <offset> byte, Device Access Address register address. The most significative three bit of the <offset> byte can be used for broadcasting control (see Figure 4.5).


5 <22><00><08><slot> Read the content of the Device Access Data register.


<00>: unused byte.

Page 14

<08>: <offset> byte, Device Access Data address. If broadcasting control was used in the preceding writing operations this step should be repeated for each of the boards belonging the subset of boards accessed by the broadcasting.


The read data byte <devreg_data> will be available in the subrack controller General Purpose Memory at location 0x00FA.

7 <12><data_c><04><slot>

Disable Device Access Registers in the Mode of Operation register.


<data_c>: <MOreg_data> AND <bxxxxx0xx>.Is the masking of the byte obtained from step#1 (<MOreg_data>) and the mask used to disable the Device Access registers (<bxxxxx0xx>).



Table 4.9, Read from device registers

Figure 4.7, Read from device registers

Page 15

R ea d M o d e o f O p e ra tio n re g is te rco m m a n d : < 2 2 > < 0 0 > < 0 4 > < s lo t>

< M O reg _ d a ta> = > S b rck C tl M e m o ry 0 x 0 0 FA

P o in t th e D e v ic e S ta tu s /C o n tro l re g is te r to a sp e c ific d e v ic e

co m m a n d : < 1 2 > < 0 x 0 ,d ev ice > < 0 1 > < slo t>

E n a b le D e v ic e A c ce ss re g is te rs< d a ta _ a> < = < M O re g _ d a ta> O R < 0 4 >co m m an d : < 1 2 > < d a ta _ a> < 0 4 > < s lo t>

P o in t th e D ev ice A cc ess A d d re ss re g is te r to a sp e c ific reg is te r in s id e a d e v ic e

co m m a n d : < 1 2 > < reg is te r> < 0 7 > < s lo t>

R e a d th e co n ten t o f th e D ev ice A ccess D a ta re g is te rco m m a n d : < 2 2 > < 0 0 > < 0 8 > < s lo t>

< d e v re g _ d a ta> = > S b rc k C tl M e m o ry 0 x 0 0 FA

D isab le D ev ice A c cess re g is te rs< d a ta _ c> < = < M O re g _ d a ta> A N D 

co m m an d : < 1 2 > < d a ta _ c> < 0 8 > < s lo t>

1

3

2

4

5

6

d ev ice reg is te rs lo o p< reg is te r> = su b se t o f < 0 0 > ..< F F >

d ev ice s lo o p< 0 x 0 ,d ev ice> = < 0 x 0 0 > ..< 0 x 0 F >

4.1.5 Write to device registers

The write operation follows all the steps of the read operation. The difference is that the result of the read is OR-ed with the desired mask and then used in one more step to write back the desired content to the device register.


1 <22><00><04><slot>

Read the content of the Mode of Operation register.


<00>: unused byte.

<04>: <offset> byte, Mode of Operation register address.


The read data byte <rdbk_dataA> will be available in the subrack controller General Purpose Memory at location 0x00FA.

2 <12><data_a><04><slot>

Enable Device Access Registers (default is disabled) in the Mode of Operation register.


<data_a>: <rdbk_dataA> OR <04>.Is the logic OR of the byte obtained from the previous step (<rdbk_dataA>) and the mask used to enable the Device Access registers (<04>).



3 <12><0x0,device><01><slot>

Point the Device Status/Control Register to a specific device. No masking is required.


<0x0,device>: 0x0 followed by 4 bit device address, from 0x00 to 0x0F.

<01>: <offset> byte, Device Status/Control register address. The most significative three bit of the <offset> byte can be used for broadcasting control (see Figure 4.5).


4 <12><register><07><slot>

Point the Device Access Address Register to a specific register inside the device. No masking is required.


<register>: Device’s internal register address.

<07>: <offset> byte, Device Access Address register address. The most significative three bit of the <offset> byte can be used for broadcasting control (see Figure 4.5).


5 <22><00><08><slot> Read the content of the Device Access Data register.

Page 16

<00>: unused byte.

<08>: <offset> byte, Device Access Data address. If broadcasting control was used in the preceding writing operations this step should be repeated for each of the boards belonging the subset of boards accessed by the broadcasting.


The read data byte < devreg_data > will be available in the subrack controller General Purpose Memory at location 0x00FA.

6 <12><data_b><08><slot>

Write to the Device Access Data register.


<data_b>: <devreg_data_new>.devreg_data_new is the byte obtained from the previous operation (<devreg_data>) after having applied the desired changes.

<08>: <offset> byte, Device Access Data register address. The most significative three bit of the <offset> byte can be used for broadcasting control (see Figure 4.5).


7 <12><data_c><04><slot>

Disable Device Access Registers in the Mode of Operation register.


<data_c>: <rdbk_dataA> AND <bxxxxx0xx>.Is the masking of the byte obtained from step#1 (<rdbk_dataA>) and the mask used to disable the Device Access registers (<bxxxxx0xx>).



Table 4.10, Write to device registers

Page 17

Figure 4.8, Write to device registers

Page 18

R ea d M o d e o f O p e ra tion re g is te rco m m a nd : < 2 2 > < 0 0 > < 0 4 > < slo t>

< M O re g_ d a ta> = > S b rck C tl M e m o ry 0x 0 0 FA

P o in t th e D ev ic e S ta tu s/C on tro l reg is te r to a sp ec if ic de v ic e

co m m a nd : < 1 2 > < 0 x 0 ,d ev ice > < 0 1 > < slo t>

E n a b le D ev ic e A cc ess re g is te rs< d a ta _ a > < = < M O re g _ da ta > O R < 0 4 >com m a n d : < 1 2 > < d a ta_ a > < 0 4 > < slo t>

P o in t th e D ev ic e A cce ss A d dress re g is ter to a sp ec if ic reg is te r in side a d e v ice


R ea d th e c o n te n t o f th e D ev ic e A cce ss D a ta reg is te rco m m a nd : < 2 2 > < 0 0 > < 0 8 > < slo t>

< d ev reg _ da ta > = > S b rc k C tl M em o ry 0 x 0 0FA

W rite to th e D ev ic e A c c es s D a ta re g is te r< d a ta _ b > < = < d ev re g_ d a ta_ n e w >

co m m a nd : < 1 2 > < d a ta _ b > < 0 8 > < slo t>

D isa b le D e v ice A c ce ss re g is te rs< d a ta _ c> < = < M O re g _d a ta > A N D < bx x x x x 0x x >

com m a n d : < 1 2 > < d a ta_ c > < 0 8 > < slo t>

1

3

2

4

5

7

6

dev ic e reg is ters lo o p< reg is te r> = su b se t o f < 0 0 > ..< F F >

d ev ic es loo p< 0x 0 ,d ev ice > = < 0 x0 0 > ..< 0 x 0 F >

4.1.6 Board reset

This procedure will reset to the default value/state all the registers and state machines on the mixer board. Due to the fact that some state machines may take several clock cycles to go to normal operation not all the history information after a board reset is reliable. After a reset it is suggested to reset history information (procedure described in paragraph 4.1.13). When a master board is reset the operation should be followed by the reset of all the slave boards in the same supersector. Paragraph 4.5 describe the procedure to reset the mixer system.


1 <12><02><00><slot>


<02>: <data> byte, set high the reset bit in the board status/control register.

<00>: <offset> byte, board status/control register address. The most significative three bit of the <offset> byte can be used for broadcasting control (see Figure 4.5).


2 <12><00><00><slot>


<00>: <data> byte, set low the reset bit in the board status/control register.

<00>: <offset> byte, board status/control register address. The most significative three bit of the <offset> byte can be used for broadcasting control (see Figure 4.5).


Table 4.11, Mixer board reset command sequence

Figure 4.9, Mixer board reset

4.1.7 Reset Board Controller History InformationThis procedure will reset the history information on the board controller FPGA.

Figure 4.10, Reset board controller history information

Page 19

slo t lo o p< s lo t> = < 0 x 15 > ..< 0 x 0 2> 1

2

W rite to b o a rd s ta tu s/co n tro l re g is terco m m a nd : < 12 > < 0 2> < 00 > < slo t>

W rite to b o a rd s ta tu s/co n tro l re g is terco m m a nd : < 12 > < 0 0> < 00 > < slo t>

1 W rite to b o ard s ta tu s /co n tro l reg is te r Bco m m an d : < 1 2 > < 0 1 > < 1 0 > < slo t>

4.1.8 Read Mixer Board configuration status and device's firmware ID

Figure 4.11, Read configuration status and device's firmware ID

4.1.9 Erase Mixer Board Configuration

Figure 4.12, Erase mixer board configuration

Page 20

P o in t th e D e v ice S ta tu s /C o n tro l re g is te r to a sp ec if ic d e v ic e

co m m an d : < 1 2 > < 0 x 0 ,d ev ice> < 0 1 > < slo t>

d ev ice s lo o p< 0 x 0 ,d ev ice> = < 0 x 0 0 > ..< 0 x 0 F >

R e ad th e D ev ice S ta tu s /C o n tro l reg is te rco m m an d : < 2 2 > < 0 0 > < 0 1 > < slo t>

< D S C reg _ d a ta > = > S b rck C tl M em o ry 0 x 0 0 FA

R ead th e D ev ice F irm w are ID reg is te rco m m an d : < 2 2 > < 0 0 > < 0 3 > < slo t>

< D F ID reg _ d a ta > = > S b rck C tl M em o ry 0 x 0 0 FA

1

3

2

1

2

R e ad M o d e o f O p e ra tio n re g is te rco m m an d : < 2 2 > < 0 0 > < 0 4 > < slo t>

< M O reg _ d a ta > = > S b rck C tl M em o ry 0 x 0 0 FA

W rite to M o d e o f O p e ra tio n re g is te r< d a ta_ a > = < M O re g _ d a ta > O R < M O re g _ m as k >

co m m a n d : < 1 2 > < d ata _ a > < 0 4 > < slo t> < M O reg _ m ask > = E n ab le E ras in g D ev ice C o n fig u ra tio n

3 W rite to D e v ic e S ta tu s /C o n tro lreg is te rco m m a n d : < 1 2 > < 4 0 > < 0 1 > < slo t>

S e ttin g th e b it “P R O G ” to “1 ” o n d ev ice # 0fo rc e th e e ra s in g o f c o n fig u ra tio n o n a ll d e v ic es

4 W rite to D e v ic e S ta tu s /C o n tro lreg is te rco m m a n d : < 1 2 > < 0 0 > < 0 1 > < slo t>

S e ttin g th e b it “P R O G ” to “0 ” o n d ev ice # 0en a b le d ev ice s to ac ce p t n e w co n fig u ra tio n

5 W rite to M o d e o f O p e ra tio n re g is te rco m m an d : < 1 2 > < > < 0 4 > < s lo t>M O reg _ d a ta

D isab le E ra s in g D ev ice C o n fig u ra tio nres to rin g i ts c o n te n t to th e v a lu e rea d ins tep # 1 .

C o n fig u re D ev ic eco m m a n d :

< 6 3 > < slo t> < 0 x 0 ,d ev ic e> < firm w areID > < file nam eH > < filen a m eL >

d ev ic es lo o p< 0 x 0 ,d ev ice > = < 0 x 0 0 > ..< 0 x 0 F > R ea d S u b ra ck C o n tro ller S ta tu s w o rd1

3

2

4

Is S ub ra ck C o n tro llerB U S Y ?

N o

Yes

R e ad bo a rd co n fig u ra tio n s ta tu san d d ev ic e’s f irm w a re ID

- < s lo t> : s lo t n u m b e r, < 0x 1 5 > .. < 0 x 0 2>- < 0 x 0 , de v ice > : d ev ic e nu m b e r, < 0 x 0 0> .. < 0 x 0 F >- < firm w a re ID > : firm w are ID b y te- < file n a m e H > < file n am e L > : tw o by te s f ile n am e , sho u ld m a tch th e firs t fo u r d ig its o f the c o n fig u ra tio n file n am e sto re d o n th e su b rac k c o n tro lle r C o m p ac tF la sh m e m o ry ca rd .


4.1.10 Configure mixer board

Figure 4.13, configure mixer board

Step 1 is described in paragraph 2.1.1. Step 4 is described in paragraph 4.1.8.

Device # Device Type

Schematic device#, device name Mixer#1 files Mixer#2 files Mixer#3 files Mixer#4 files

0 Spartan XL U2, DFE1 YP (Outlink 5). 0200_PC.bin 0300_PC.bin 0400_PC.bin 0500_PC.bin

1 Spartan XL U1, DFE1 RB (Outlink 6). 0201_PC.bin 0301_PC.bin 0401_PC.bin 0501_PC.bin

2 Spartan XL U10, DFE1 OG (Outlink 4). 0202_PC.bin 0302_PC.bin 0402_PC.bin 0502_PC.bin

3 Spartan XL U11, DFE0 RB (Outlink 3). 0203_PC.bin 0303_PC.bin 0403_PC.bin 0503_PC.bin

4 Spartan XL U19, DFE0 OG (Outlink 1). 0204_PC.bin 0304_PC.bin 0404_PC.bin 0504_PC.bin

5 Spartan XL U18, DFE0 YP (Outlink 2). 0205_PC.bin 0305_PC.bin 0405_PC.bin 0505_PC.bin

6 Virtex U31, LINK_IN 13-15. 0206_PC.bin 0306_PC.bin 0406_PC.bin 0506_PC.bin




10 Virtex U47, LINK_IN 0. 020A_PC.bin 030A_PC.bin 040A_PC.bin 050A_PC.bin

11 Virtex U48, Backplane Left Driver. 020B_PC.bin 030B_PC.bin 040B_PC.bin 050B_PC.bin

12 Virtex U33, LINK_IN 7-9. 020C_PC.bin 030C_PC.bin 040C_PC.bin 050C_PC.bin

13 Virtex U12, Backplane DFE0 receiver. 020D_PC.bin 030D_PC.bin 040D_PC.bin 050D_PC.bin

14 Virtex U5, Backplane DFE1 receiver. 020E_PC.bin 030E_PC.bin 040E_PC.bin 050E_PC.bin

15 Virtex U6, Backplane Right Driver. 020F_PC.bin 030F_PC.bin 040F_PC.bin 050F_PC.bin

Table 4.12, Configuration Files denomination.

Page 21

Mixer# Subrack slots

1 02, 06, 10, 14, 18

2 03, 07, 11, 15, 19

3 04, 08, 12, 16, 20

4 05, 09, 13, 17, 21

Table 4.13, Mixer# and Subrack slot#.

4.1.11 Read board controller firmware revision date and board serial number

Figure 4.14, Read board controller firmware revision date and board serial number

Page 22

slo t loo p< slo t> = < 0 x 15 > ..< 0x 0 2 > 1

3

2

R e a d th e F irm w a re re v is io n d ate D AY re g is te rco m m an d : < 22 > < 0 0 > < 1 C > < slo t>

< F R D D re g _ d a ta > = > S b rck C tl M em o ry 0x 0 0 FA

R ea d th e F irm w a re re v is io n d a te M O N T H re g is te rco m m an d : < 2 2 > < 00 > < 1 D > < slo t>

< F R D M reg _ d ata> = > S b rc k C tl M e m o ry 0 x 00 FA

R e a d th e F irm w a re re v is ion d ate Y E A R re g is te rco m m an d : < 2 2 > < 0 0 > < 1E > < s lo t>

< F R D Y re g _ d a ta > = > S b rck C tl M em o ry 0x 0 0 FA

4R ea d th e b o ard se ria l n u m b er reg is te r

co m m an d : < 22 > < 00 > < 1 F > < slo t>< F R D Y re g _ d a ta > = > S b rck C tl M em o ry 0x 0 0 FA

R e se t B o ard C o n tro lle r H is to ry In fo rm a tio n1

3

2

4

R e se t O u tp u t L ink s H isto ry In fo rm a tio n

R ese t In p u t L in k s H is to ry In fo rm a tion

R e se t B ack p la ne D e v ice s H isto ry In fo rm a tion


4.1.12 Read/Write test

Figure 4.15, Read/write test

4.1.13 Reset Board History Information

The reset of the history information on a mixer board follow few steps to operate on the several devices on the board. The procedure can be generalized to the mixer system or to a subset of it using broadcasting of the commands.

Figure 4.16, Reset Board History Information

Page 23

W rite to R e a d /W rite Tes t re g is te rthe b y te < te s t_ d a ta>

co m m an d : < 1 2> < te st_ d a ta> < 1 B > < s lo t>

te st lo o p

R e ad th e R ea d /W rite Te st re g is terco m m a nd : < 2 2 > < 0 0 > < 1 B > < s lo t>

< RW T re g _d a ta > = > S b rc k C tl M e m ory 0 x0 0 FA

3

5

4

Is < RW T re g _d a ta > =< te st_ d a ta > ?

N o

Yes

G en e ra te a ra nd o m b y te < te s t_ d a ta> 2

In c re m e n t e rro r co u n te r, re c o rd erro r 6

R ese t lo o p an d e rro r c ou n te rs1

In c re m e n t lo o p c o u n ter7

defin e :< M O reg_ d a ta> < = M od e o f O p e ra tio n re g is te r co n ten t

P o in t the D ev ic e S ta tu s/C o n tro l re g is ter to a sp ec ific d ev ice

co m m an d : < 1 2> < 0 x0 ,d e v ice> < 0 1 > < slo t>

E n ab le D e vice A c ce ss reg is te rs< d ata_ a> < = < M O re g_ d a ta> O R < 0 4 >co m m an d : < 12 > < d ata _a> < 04 > < slo t>

P o in t the D ev ic e A cc es s A d dres s reg ister to a sp ec if ic reg is te r in s id e a d ev ice

com m an d: < 1 2 > < re g iste r> < 0 7 > < slo t>

R e ad the c o n ten t o f th e D e v ice A cc ess D a ta re g is terco m m an d : < 2 2 > < 0 0> < 0 8 > < slo t>

< dev re g_ d ata> = > S b rck C tl M em o ry 0 x0 0 FA

d ev ice re g is te rs lo op< reg is te r> = su bset o f < 0 0 > ..< F F >

d ev ice s lo o p< 0x 0 ,d e v ice> = < 0x 0 0> ..< 0 x 0 F >

D isab le D ev ic e A ccess re g is te rs< da ta_ c > < = < M O re g _ da ta> A N D < bx x x xx 0 x x >

co m m an d : < 12 > < d ata _c> < 08 > < slo t>

R e ad the D e v ice S ta tu s /C o n tro l reg is te rco m m an d : < 2 2 > < 0 0> < 0 1 > < slo t>

< D S C re g _d a ta> = > S b rck C tl M em o ry 0x 0 0 FA

R e ad the D e v ice F irm w a re ID reg isterco m m an d : < 2 2 > < 0 0> < 0 3 > < slo t>

< D F ID reg _ d a ta> = > S b rc k C tl M em o ry 0 x 00 FA

R e ad a ll th e b o a rd-c o n tro lle r re g is te rs< o ffse t> = < 1 F > ..< 0 0>

R e set b o ard h is to ry in fo rm atio n

1

3

2

4

5

7

6

8

9

1 0


Step 1 is described in paragraph 4.1.7. Step 2 is described in paragraph 4.2.3.Step 3 is described in paragraph 4.4.7. Step 4 is described in paragraph 4.3.1.

4.1.14 Taking a snapshot of Mixer Board statusTaking a snapshot of mixer board status consists in reading all the board controller registers and all of the device registers. This can be done using the procedures described previously in Paragraphs 4.1.1 (for step 1 in Figure 4.17) and 4.1.4 .

Figure 4.17, Mixer Board status snapshot

Page 24

The read of the output links FIFOs is not included in the procedure. One exception is the procedure to read the content of the Device Status/Control register and the Device Firmware ID register. The content of these registers reflect the status/information of the device pointed by the four less significative (device select) bits of the Device Status/Control register.It is suggested to erase all the history information after each snapshot (step 9 in Figure 4.17, the procedure is specified in paragraph 4.1.13). At the next snapshot this will provide useful insides on what happened on the board (i.e. loss of input links clock/frame-marker/frame-synchronization, etc.).

4.2 Input Links procedures

4.2.1 Read input links error status

Figure 4.18, Read input links error status

Page 25

3

5

Is th e re an y b it se t to “ 1 ” in b y te s

< IL E S H re g _ d a ta> an d

< IL E S L reg _ d a ta> ?

N o

Yes

2

R ep o rt E rro r 4

1R ea d th e In p u t L in k s E rro r S ta tu s H ig h reg is te r

co m m an d : < 2 2 > < 0 0 > < 0 6 > < slo t>< IL E S H re g _ d a ta> = > S b rck C tl M em o ry 0 x 0 0 FA

R ea d th e In p u t L in k s E rro r S ta tu s L o w reg is te rco m m an d : < 2 2 > < 0 0 > < 0 7 > < slo t>

< IL E S L reg _ d a ta> = > S b rck C tl M em o ry 0 x 0 0 FA

6

R ea d M o d e o f O p era tio n reg is te rco m m an d : < 2 2 > < 0 0 > < 0 4 > < slo t>

< M O reg _ d a ta > = > S b rck C tl M e m o ry 0 x 0 0 FA

D isa b le la tc h in g in th e In p u t L in k s S ta tu s reg is te rs< d a ta _ a> < = < M O reg _ d a ta> A N D 

co m m an d : < 1 2 > < d a ta _ a> < 0 4 > < s lo t>

7E n ab le la tch in g in th e In p u t L in k s S ta tu s reg is te rs

< d a ta_ b > < = < M O reg _ d a ta> O R co m m an d : < 1 2 > < d a ta_ b > < 0 4 > < slo t>

slo t lo o p< slo t> = < 0 x 1 5 > ..< 0 x 0 2 >

4.2.2 Read input links status

Figure 4.19, read input links status

Page 26

P o in t the D e v ic e S tatu s /C o n tro l reg is te r to a sp e c if ic dev ice

com m an d : < 1 2> < 0x 0 ,dev ice> < 01 > < slo t>

E na b le D e v ice A cce ss re g is te rs< d a ta_ a> < = < M O re g _ d a ta> O R < 0 4 >c om m an d : < 1 2 > < da ta_ a > < 0 4 > < slo t>

de v ice re g is te rs loo p< reg is te r> = < 1 6> ..< 10 > , < 26 > ..< 2 0> , < 3 6> ..< 3 0>

fron t e nd d ev ice s lo op < 0 x 0 ,d ev ic e> = < 0A > (lin k 0 ), < 0 8> (lin ks1 ..3 ) , < 0 7 > (link s4 ..6 ) , < 0 C > (lin ks7 ..9 ), < 0 9 > (lin ks1 0 ..1 2 ), < 06 > (lin k s13 ..1 5 )

1

3

2

4

5

7

6

8

9

R e a d M o d e o f O pe ra tion reg is te rcom m an d : < 2 2> < 00 > < 04 > < slo t>

< M O re g_ da ta > = > S b rc k C tl M em o ry 0x 0 0 FA

P oin t th e L in k S ta tu s A re g is te r < re g is te r> : 0x 10 , 0x2 0 , 0x 30

c om m an d : < 1 2> < re g is te r> < 0 7> < slo t>

R e a d th e L in k S ta tu s A reg is te rcom m an d : < 2 2> < 00 > < 08 > < slo t>

< L S A reg _d a ta> = > S brc k C tl M em ory 0x 00 FA

P o in t the L in k S ta tu s B reg is te r

c om m an d : < 1 2> < re g is te r> < 0 7> < slo t> < re g is te r> : 0x 11 , 0x 2 1 , 0 x 3 1

R ea d th e L ink S ta tu s B reg is te rcom m an d : < 2 2> < 00 > < 08 > < slo t>

< L S B re g _ da ta > = > S b rc k C tl M e m ory 0 x 0 0 FA

10

11

12

P o in t the F ram e S y nc S ta tu s reg is te r

c om m an d : < 1 2> < re g is te r> < 0 7> < slo t> < re g is te r> : 0x 13 , 0x2 3 , 0x 33

R ea d th e F ram e S yn c S ta tu s reg iste rcom m an d : < 2 2> < 00 > < 08 > < slo t>

< F S S reg _d a ta> = > S brc k C tl M e m o ry 0 x 0 0 FA

13

P o in t the F ram e S y nc S ta tu s H isto ry re g is te r

c om m an d : < 1 2> < re g is te r> < 0 7> < slo t> < re g is te r> : 0x 14 , 0x2 4 , 0x 34

R ea d th e F ram e S yn c S ta tu s H is to ry reg is te rcom m an d : < 2 2> < 00 > < 08 > < slo t>

< F S S H reg_ da ta> = > S b rc k C tl M em ory 0 x 00 FA

14

16

15

17

18

20

19

21

P o in t th e C o n tro l B its S ta tu s reg is te r

com m an d : < 1 2> < re g is te r> < 0 7 > < slo t> < re g is te r> : 0 x 1 6 , 0x 2 6 , 0 x 3 6

R e a d th e re g is te rc om m an d : < 2 2 > < 00 > < 0 8 > < slo t>

< C B S re g _ d a ta > = > S b rck C tl M e m o ry 0 x 0 0FA

C o n tro l B its S ta tu s

P o in t th e M o n ito rin g M od e 7 M ask reg is te r

com m an d : < 1 2> < re g is te r> < 0 7 > < slo t> < re g is te r> : 0 x 1 5 , 0x 2 5 , 0 x 3 5

R ea d th e re g is te rc om m an d : < 2 2 > < 00 > < 0 8 > < slo t>

< M M 7M reg _ da ta> = > S b rck C tl M em o ry 0x0 0FA

M on ito rin g M od e 7 M a sk

P o in t th e L in k C o n tro l re g is ter

com m an d : < 1 2> < re g is te r> < 0 7 > < slo t> < reg is te r> : 0x 12 , 0 x2 2 , 0x 32

R e a d th e reg is te rc om m an d : < 2 2 > < 00 > < 0 8 > < slo t>

< L C reg _d a ta> = > S brck C tl M em o ry 0 x00 FA

L ink C o n tro l

R e se t link h isto ry

com m an d : < 1 2> < da ta_b > < 08 > < slo t>< d a ta_ b> < = < L C reg _d a ta> O R < 0 1>

E na b le lin k h is to ry

co m m a n d : < 1 2 > < d a ta_ c > < 0 8 > < s lo t>< d a ta_ c> < = < L C reg_ da ta> A N D 

D isa b le la tch ing in C o n tro l B its S ta tu s reg is te r c om m an d : < 1 2 > < 00 > < 0 8 > < slo t>

E n a b le la tc h ing in C o n tro l B its S ta tu s reg is te rcom m an d : < 1 2> < 01 > < 08 > < slo t>

22D isa b le D e v ice A c cess re g is te rs

< d a ta_ c> < = < M O re g_ da ta> A N D com m an d : < 1 2> < da ta_c > < 0 8> < slo t>

o p tio na l s teps to re set an d en ab le lin k h istory reco rd in g

4.2.3 Reset Mixer Board input links status history

Steps 4, 5, 6 are used to reset the control bits history information stored in the Control Bits Status registers.

Figure 4.20, Reset input links status history

Page 27

P o in t th e D ev ice S ta tu s/C o n tro l reg is te r to a sp ec if ic d ev ice


E n ab le D ev ice A ccess reg is te rs< d ata_ a> < = < M O re g _ d a ta > O R < 0 4 >co m m an d : < 1 2 > < d ata_ a > < 0 4 > < slo t>

fro n t en d d ev ic es lo o p < 0 x 0 ,d ev ice > = < 0 A > (lin k 0 ), < 0 8 > (lin k s1 ..3 ) , < 0 7 > (lin k s4 ..6 ), < 0 C > (l in k s7 ..9 ), < 0 9 > (lin k s1 0 ..1 2 ), < 0 6 > ( lin k s1 3 ..1 5 )

1

3

2

4

5

6

R ead M o d e o f O p era tio n re g is te rco m m an d : < 2 2 > < 0 0 > < 0 4 > < slo t>

< M O reg _ d a ta> = > S b rc k C tl M em o ry 0 x 00 FA

7

8

10

9

11

P o in t th e C o n tro l B its S ta tu s reg iste r

co m m an d : < 1 2 > < re g is te r> < 0 7 > < slo t> < reg is te r> : 0 x 1 6 , 0 x 2 6 , 0 x 3 6

P o in t th e L in k C o n tro l reg is te r

co m m an d : < 1 2 > < re g is te r> < 0 7 > < slo t> < reg ister> : 0 x 1 2 , 0 x 2 2 , 0 x 3 2

R ead th e reg iste rco m m an d : < 2 2 > < 0 0 > < 0 8 > < slo t>

< L C reg _ d a ta> = > S b rck C tl M e m o ry 0 x 0 0 FA

L in k C o n tro l

R ese t lin k h is to ry

co m m an d : < 1 2 > < d a ta_ b > < 0 8 > < slo t>< d a ta_ b > < = < L C reg _ d a ta> O R < 0 1 >

E n ab le lin k h is to ry

co m m an d : < 1 2 > < d a ta_ c > < 0 8 > < slo t>< d a ta_ c> < = < L C reg _ d a ta> A N D D isab le la tch in g in C o n tro l B its S ta tu s reg is te r

co m m an d : < 1 2 > < 0 0 > < 0 8 > < slo t>

E n ab le la tc h in g in C o n tro l B its S ta tu s reg iste rco m m an d : < 1 2 > < 0 1 > < 0 8 > < slo t>

D isab le D ev ic e A c cess reg is te rs< d ata_ c> < = < M O re g _ d a ta > A N D 

co m m an d : < 1 2 > < d a ta_ c > < 0 8 > < slo t>

d ev ic e reg is te rs lo o p< reg is te r> = < 1 2 > ,< 1 6 > , < 2 2 > , < 2 6 > , < 3 2 > , < 3 6 >

4.2.4 Input Links Control

Figure 4.21, Input Links control procedure.

Figure 4.22, Input Links Control register

Page 28

P o in t th e D ev ice S ta tu s/C o n tro l reg is te r to a sp ec ific d ev ic e

co m m an d : < 1 2 > < 0 x 0 ,d ev ic e > < 0 1> < slo t>

E nab le D ev ice A cce ss reg is te rs< d a ta_ a> < = < M O re g _ da ta> O R < 0 4>co m m an d : < 1 2 > < d a ta_ a> < 0 4 > < slo t>

dev ice re g is te rs lo op < reg iste r> = < 1 2 > ( link s 0 , 1 , 4 , 7 , 1 0 , 1 3 ) , < 2 2 > ( link s 2 , 5 , 8 , 11 , 1 4 ), < 3 2 > ( link s 3 , 6 , 9 , 1 2 , 1 5 )

fron t e n d d e v ic es lo o p < 0 x0 ,d ev ice> = < 0 A > (lin k 0 ), < 0 8> (lin k s 1 ..3 ), < 0 7> (lin k s 4 ..6 ), < 0 C > (lin ks 7 ..9 ), < 0 9> (lin k s 10 ..1 2 ), < 0 6> (lin k s 13 ..1 5 )

1

3

2

4

5

R ead M o d e o f O p era tio n reg is te rco m m an d: < 2 2 > < 0 0 > < 0 4 > < slo t>

< M O reg _ da ta > = > S b rc k C tl M em o ry 0 x 0 0 FA

P o in t the L ink C o n tro l re g is te r < reg is te r> : 0 x1 2 , 0x 2 2 , 0x 3 2

co m m an d : < 1 2 > < reg iste r> < 07 > < slo t>

6

7

R e ad th e reg is te rcom m an d: < 2 2> < 0 0 > < 0 8> < slo t>

< L C reg _da ta> = > S b rck C tl M e m o ry 0 x 00 FA

L ink C on tro l

D isab le D e v ic e A cc ess re g is te rs< d ata_ b> < = < M O reg _ d ata > A N D 

com m an d: < 1 2> < da ta _ b> < 0 8> < slo t>

W rite n ew L ink C o n tro l re g is te r m askcom m an d: < 1 2 > < L C reg _ m ask > < 0 8 > < slo t>

| 7 6 5 4 | 3 2 1 0 |

In p u t L in k C o n tro l R e g is te r (R E A D /W R IT E )

R ese t H is to ry in fo rm a tio nK ill lin k d a taD ata sam p lin g ed g e se lec t0 E 01 E 1 (d e fau lt)

L o g ic A n a ly ze r Test P O D co n fig (L in k # 0 O N LY ) 0 : 2 1 b its c o n fig u ra tio n (d e fau lt) 1 : 2 8 b its c o n fig u ra tio n .

D elay se lec t0 0 D 0 0 1 D 11 0 D 211 D 3

(d efau lt)

XX

| 7 6 5 4 | 3 2 1 0 |

In p u t L ink C on tro l B its M a sk R e g iste r (R E A D /W R IT E )

E n ab le m ask in g

Tim e s lo t 2 m ask in g

Tim e s lo t 4 m ask in gTim e s lo t 5 m ask in gTim e s lo t 6 m ask in g




4.2.5 Input Links Control bits masking

Figure 4.23, Input Link Control Bits Mask Register

Figure 4.24, Command bits generation, timing and denomination.

Page 29

C o n tro l b it# 1 (t im e s lo t 1 ): F irs t C ro ss in gC o n tro l b it# 2 : S Y N C G a p

C on tro l b its a ssign m en t

C o n tro l b it# 3 : C F T re se tC o n tro l b it# 4 : B e am -3 9 6C o n tro l b it# 5 : L 1 A cc ep tC o n tro l b it# 6 : Te s t M o d eC o n tro l b it# 7 : S p are

( tim e s lo t 2 )( tim e s lo t 3 )( tim e s lo t 4 )( tim e s lo t 5 )( tim e s lo t 6 )( tim e s lo t 7 )

C o n tro l B its# n

fro m L in k # 1fro m L in k # 2fro m L in k # 3fro m L in k # 4fro m L in k # 5fro m L in k # 6fro m L in k # 7fro m L in k # 8fro m L in k # 9

fro m L in k # 1 0fro m L in k # 11fro m L in k # 1 2fro m L in k # 1 3fro m L in k # 1 4fro m L in k # 1 5

fro m L in k # 0 (C P S )

tim etim e s lo t # 1 2 3 4 5 6 7

C o n tro l b its tem p o ra l lo c a tio n o n LV D S lin k s fro m A F E s

C o n tro l b its tem p o ra l lo c a tio n o n LV D S lin k s to D F E s

S Y N C P U L S E

C o n tro lb it# 1

C o n tro lb it# 2

C o n tro lb it# 3

C o n tro lb it# 4

C o n tro lb it# 5

C o n tro lb it# 6

C o n tro lb it# 7

E Cb it# 1

E Cb it# 2

E Cb it# 3

E Cb it# 4

E Cb it# 5

E Cb it# 6

E Cb it# 7

E C Sb it# 1

E C Sb it# 3

E C Sb it# 4

E C Sb it# 5

E C Sb it# 6

E C Sb it# 7

E C Sb it# 2

O u tp u t L in k sIn p u t L in k s

C F T /C P SA x ia l

D ig ita lF ro n t-E n d

B o ard

C F T /C P SA x ia l

D ig ita lF ro n t-E n d

B o ard

2 sec to rs (1 sec to r p a ir)

T x -0 1T x -0 2T x -0 3T x -0 4T x -0 5T x -0 7

T x -11T x -1 2T x -1 3T x -1 4T x -1 5T x -1 7

T x -0 0

T x -0 6

T x -1 0

T x -1 6

423675

0

9

423675

0

9

M ix er B o a rd D ig ita l F ro n t E n d B o a rd s

1

1

In p u t L in k s C o n tro lB its M ask reg is te rs

1 61 6C o n tro l B its

S ta tu s reg is te rs

RESET

3

51

2

04

7

6

812

913

1014

1115

3.3 2.5

01

00

0203

0405

1514131211

to fro n t p an e l L E D s (m o n ito rin g m o d e # 7 )

C o n tro l B its S ta tu sa t L K 0 F P G A re g is te r

L in k P o in te rreg is te r

1

M o n ito rin g M o d e 7M a sk reg is te rs

E m b ed d e dC o m m an d

B it (E C b ) # n

E m b e d d edC o m m an d S ta tu s

B it (E C S b ) # n

E m b e d d ed C o m m a n d B itsS ta tu s reg is te r

E m b e d d ed C o m m an d S ta tu sB its S ta tu s re g is te r

O u tp u t L in k s C o n tro lB its M ask reg is te rs

command (0x) Notes

<12><17><84><02> Write 0x17 to the Mode of Operation Register of all mixer boards in the subrack (subrack broadcast) to enable Device Access Registers.

<12><0A><81><02> Write byte 0x0A to the Device/Status Control register in all mixer boards (subrack broadcast). Sets the device select pointer to device 0x0A.

<12><reg_addr><07><slot>

Write byte <reg_addr> to the Device Access Address register (address <07>) of the mixer board in slot <slot>. This set the Device Access Address register to point inside device 0x0A to the register having address <regaddr>.<regaddr> depends on the input link on which the control bits mask is to be modified:

<40>: Link#0 Control Bits Masking register <41>: Link#1 Control Bits Masking register <42>: Link#2 Control Bits Masking register <43>: Link#3 Control Bits Masking register <44>: Link#4 Control Bits Masking register <45>: Link#5 Control Bits Masking register <46>: Link#6 Control Bits Masking register <47>: Link#7 Control Bits Masking register <48>: Link#8 Control Bits Masking register <49>: Link#9 Control Bits Masking register <4A>: Link#10 Control Bits Masking register <4B>: Link#11 Control Bits Masking register <4C>: Link#12 Control Bits Masking register <4D>: Link#13 Control Bits Masking register <4E>: Link#14 Control Bits Masking register <4F>: Link#15 Control Bits Masking register

<07>: <offset> byte: board Device Access Address register address. The most significative three bits of the <offset> byte can be used for broadcasting control (see Figure 4.5).


<12><cb_mask><08><slot>

Write <cb_mask> to the Device Access Data register of the mixer board in slot <slot>. The byte <cb_mask> will be written to the register pointed by <reg_addr> in the device 0x0A. This will mask the control bits on input link specified by <reg_addr>.

<cb_mask> is the control bit mask and should be chosen depending on the control bits to be asked (see Figure 4.23 and Figure 4.24). <00>: masking disabled (equivalent to no masking) <FF>: masking enabled, no bit is masked <01>: all control bits are masked <DF>: only control bit at time slot 5 (L1 Accept) is masked.

<08>: <offset> byte: board Device Access Data register address. The most significative three bits of the <offset> byte can be used for broadcasting control (see Figure 4.5).


Repeat the last two commands as needed to mask the control bits on all the desired links.

<12><13><84><02> Write 0x13 to the Mode of Operation Register of all mixer boards in the subrack (subrack broadcast) to disable Device Access Registers.

<A1><00> End of list command. Stop the subrack controller execution of the commands in the command buffer.

Table 4.14, Example of command sequence to mask control bits on the input links.

Page 30

Figure 4.25, input links control bits masking

Page 31

P o in t th e D e v ice S ta tu s /C o n tro l re g is te r to d e v ic e 1 0 (0 x 0 A )

co m m a n d : < 1 2 > < 0 A > < 0 1 > < slo t>

E n ab le D e v ic e A cc es s reg is te rs< d a ta_ a> < = < M O reg _ d a ta> O R < 0 4 >co m m a n d : < 1 2 > < d a ta _ a> < 0 4 > < slo t>

d ev ice reg is te rs lo o p < re g iste r> = < 4 0 > (lin k 0 ),

< 4 1 > (lin k 1 ), < 4 2 > (lin k 2 ), < 4 3 > (lin k 3 ), < 4 4 > (lin k 4 ), < 4 5 > (lin k 5 ), < 4 6 > (lin k 6 ), < 4 7 > (lin k 7 ), < 4 8 > (lin k 8 ), < 4 9 > (lin k 9 ), < 4 A > (lin k 1 0 ), < 4 B > ( lin k 11 ), < 4 C > ( lin k 1 2 ), < 4 D > (lin k 1 3 ), < 4 E > (l in k 1 4 ) , < 4 F > (lin k 1 5 )

1

3

2

4

5

7

6

R e ad M o d e o f O p e ra tio n reg is te rco m m a n d : < 2 2 > < 0 0 > < 0 4 > < slo t>

< M O reg _d a ta > = > S b rc k C tl M e m o ry 0 x 0 0 FA

P o in t to a L in k C o n tro l B its M a sk in g re g is te r < reg is te r> : 0 x 4 F..0 x 4 0


R e ad th e L in k C o n tro l B its M a sk in g re g is terco m m a n d : < 2 2 > < 0 0 > < 0 8 > < slo t>

< C B M reg _ d a ta> = > S b rc k C tl M e m o ry 0 x 0 0 FA

W rite th e L in k n co n tro l b its m ask co m m a n d : < 1 2 > < C B M _ m ask > < 0 8 > < slo t>

D isa b le D ev ic e A c ce ss reg is te rs< d a ta_ c> < = < M O reg _ d a ta> A N D 

co m m a n d : < 1 2 > < d a ta _ c> < 0 8 > < slo t>

4.2.6 Monitoring mode 7 masking

Figure 4.26, monitoring mode 7 masking

Page 32

P o in t th e D e v ic e S ta tu s /C o n tro l reg is te r to a sp ec if ic d e v ic e

co m m an d : < 1 2 > < 0 x 0 ,d ev ic e> < 0 1 > < slo t>

E n ab le D ev ic e A cc e ss re g is te rs< d ata_ a > < = < M O reg _ d a ta > O R < 0 4 >co m m an d : < 1 2 > < d a ta_ a > < 0 4 > < slo t>

d ev ice re g is te rs lo o p < reg ister> = < 1 5 > ( lin k s 0 , 1 , 4 , 7 , 1 0 , 1 3 ), < 2 5 > ( lin k s 2 , 5 , 8 , 11 , 1 4 ), < 3 5 > ( lin k s 3 , 6 , 9 , 1 2 , 1 5 )

fro n t e n d d ev ice s lo o p < 0 x 0 ,d e v ic e> = < 0 A > ( lin k 0 ), < 0 8 > ( link s1 ..3 ), < 0 7 > ( link s4 ..6 ), < 0 C > (lin k s7 ..9 ), < 0 9 > ( link s1 0 ..1 2 ), < 0 6 > ( link s1 3 ..1 5 )

1

3

2

4

5

R e ad M o d e o f O p e ra tio n re g is te rco m m an d : < 2 2 > < 0 0 > < 0 4 > < slo t>

< M O reg _ d a ta> = > S b rc k C tl M e m o ry 0 x 0 0 FA

6

7

P o in t th e M o n ito rin g M o d e 7 M a sk re g is te r

co m m an d : < 1 2 > < reg is ter> < 0 7 > < slo t> < re g is te r> : 0 x 1 5 , 0 x 2 5 , 0 x 35

R e ad th e reg is te rco m m an d : < 2 2 > < 0 0 > < 0 8 > < slo t>

< M M 7 M reg _d a ta > = > S b rck C tl M e m o ry 0 x 0 0 FA

M o n ito rin g M od e 7 M a sk

D isab le D e v ice A c ce ss reg is te rs< d a ta_ b > < = < M O re g _ d a ta> A N D 

co m m an d : < 1 2 > < d a ta_ b > < 0 8 > < slo t>

W rite n ew M o n ito rin g M o d e 7 m askco m m an d : < 1 2 > < M M 7 _ m ask > < 0 8> < slo t>

4.2.7 Input Links Control bits status

Figure 4.27, read input links control bits status

Page 33



E n ab le D ev ice A ccess reg is te rs< d ata_ a> < = < M O re g _ d a ta > O R < 0 4 >co m m an d : < 1 2 > < d ata_ a > < 0 4 > < slo t>

d ev ic e reg is te rs lo o p< reg is te r> = < 1 6 > , < 2 6 > , < 3 6 >

fro n t en d d ev ic es lo o p < 0 x 0 ,d ev ice > = < 0 A > (lin k 0 ), < 0 8 > (lin k s1 ..3 ) , < 0 7 > (lin k s4 ..6 ), < 0 C > (l in k s7 ..9 ), < 0 9 > (lin k s1 0 ..1 2 ), < 0 6 > ( lin k s1 3 ..1 5 )

1

3

2

4

R ead M o d e o f O p era tio n re g is te rco m m an d : < 2 2 > < 0 0 > < 0 4 > < slo t>

< M O reg _ d a ta> = > S b rc k C tl M em o ry 0 x 00 FA

5

6

7

8P o in t th e C o n tro l B its S ta tu s reg iste r

co m m an d : < 1 2 > < re g is te r> < 0 7 > < slo t>

< reg is te r> : 0 x 1 6 , 0 x 2 6 , 0 x 3 6

R ead th e reg isterco m m an d : < 2 2 > < 0 0 > < 0 8 > < slo t>

< C B S reg _ d a ta > = > S b rck C tl M em o ry 0 x 0 0 FA

C o n tro l B its S ta tu s

D isab le la tch in g in C o n tro l B its S ta tu s reg is te r co m m an d : < 1 2 > < 0 0 > < 0 8 > < slo t>

E n ab le la tc h in g in C o n tro l B its S ta tu s reg is te rco m m an d : < 1 2 > < 0 1 > < 0 8 > < slo t>

D isab le D ev ic e A c cess reg is te rs< d a ta_ c> < = < M O re g _ d a ta > A N D 

co m m an d : < 1 2 > < d a ta_ c > < 0 8 > < slo t>

op tion a l s tep s to reset a n d en a b le co n tro l b its h isto ry record in g

4.2.8 Embedded Command Bits Status

This procedure will allow to verify the status of the Embedded Command Bits (see Figure4.24).

Figure 4.28, Read Embedded Command Bits status.

Page 34

P o in t th e D ev ice S ta tu s /C o n tro l reg is te r to d e v ic e 0 x A

co m m an d : < 1 2 > < 0 x 0 A > < 01 > < slo t>

E n ab le D e v ic e A ccess reg iste rs< d a ta_ a> < = < M O reg _ d ata> O R < 0 4 >co m m an d : < 1 2 > < d ata_ a> < 0 4 > < slo t>

1

3

2

4

R ead M o d e o f O p e ra tio n reg is te rco m m an d : < 2 2 > < 0 0 > < 0 4 > < slo t>

< M O reg _ d ata> = > S brck C tl M e m o ry 0 x 0 0 FA

5

P o in t th e d e s ired S ta tu s reg is te r< reg iste r> = 0 x 5 1 o r 0 x 5 2

co m m an d : < 1 2 > < reg is te r> < 0 7 > < slo t>

R e ad th e re g is te r < reg is te r>co m m an d : < 2 2 > < 0 0 > < 0 8 > < slo t>

< reg _ d a ta> = > S b rc k C tl M em o ry 0 x 0 0 FA

reg is te r lo op , < reg is te r> = 0 x 5 1 (E m b e d d ed C o m m a n d B its s ta tu s reg is te r) o r 0 x 5 2 (E m b e d d ed C o m m a n d S ta tu s B its s ta tu s reg iste r)

6

7

8

D isa b le la tch in g in reg is te r < reg is te r> co m m an d : < 1 2 > < 0 0 > < 0 8 > < slo t>

E n ab le la tch in g in reg is te r < reg is te r>co m m an d : < 1 2 > < 0 1 > < 0 8 > < slo t>

D isa b le D ev ice A cce ss reg is te rs< d a ta_ c> < = < M O reg _ d ata> A N D 

co m m an d : < 1 2 > < d ata_ c> < 0 8 > < slo t>

o p tion a l s teps to re se t an d en ab le co n tro l b its h is to ry record in g

4.3 Backplane Devices Procedures

4.3.1 Reset Backplane Devices History

Figure 4.29, reset backplane devices history.

Page 35

P o in t the D ev ice S ta tus /C o n tro l reg is te r to a sp ec ific d ev ice

co m m a n d : < 1 2 > < 0 x 0 ,d ev ice> < 0 1 > < s lo t>

E n ab le D ev ic e A ccess reg iste rs< d a ta_ a> < = < M O reg _ d ata> O R < 0 4 >co m m a n d : < 1 2 > < d a ta _ a> < 0 4 > < s lo t>

b ack p lan e d ev ice s lo o p< 0 x 0 ,d e v ic e> = < 0 F > , < 0 E > (D F E 1 _ R X F P G A ), < 0 D > (D F E 0_ R X F P G A ), < 0 B > (L E F T _ D RV F P G A )

(R IG H T _ D RV F P G A an d c lo ck co n tro lle r)

1

3

2

4

5

6

R ead M o d e o f O p e ra tio n reg is te rco m m a n d : < 2 2 > < 0 0 > < 0 4 > < slo t>

< M O reg _ d ata> = > S b rck C tl M em o ry 0 x 0 0 FA

P o in t to th e D e v ic e C o n tro l reg is te r in th e d ev ice

co m m an d : < 1 2 > < reg is te r> < 0 7 > < slo t> < reg iste r> : 0 x 0 2

W rite 0 x 0 1 to th e D ev ice C o n tro l reg is te r in th e d ev ice co m m a n d : < 1 2 > < 0 1 > < 0 8 > < slo t>

D isa b le D ev ice A cce ss reg is te rs< d a ta_ c> < = < M O reg _ d ata> A N D 

co m m a n d : < 1 2 > < d a ta _ c> < 0 8 > < s lo t>

4.3.2 Readback Mixer Board clock/SYNC status

Figure 4.30, Read Clock/SYNC Status and History.

4.3.3 Reset Mixer Board clock/SYNC status history

The procedure to reset the clock and SYNC history on the mixer board is the same specified to reset history information on backplane devices (paragraph 4.3.1) applied to the Backplane right driver device (board controller).

Page 36

R e ad M o d e o f O p e ra tio n reg is te rco m m a n d : < 2 2 > < 0 0 > < 0 4 > < slo t>

< M O reg _ d a ta > = > S b rck C tl M em o ry 0 x 0 0 FA

P o in t th e D ev ice S ta tu s /C o n tro l re g is te r to th e B a ck p lan e R ig h t D riv e r (c lo ck co n tro lle r)

co m m an d : < 1 2 > < 0 F > < 0 1 > < slo t>

E n ab le D e v ic e A cc ess reg is te rs< d a ta_ a> < = < M O reg _ d a ta > O R < 0 4 >co m m a n d : < 1 2 > < d ata_ a > < 0 4 > < s lo t>

P o in t th e D ev ice A c ce ss A d d ress re g is te r to a sp e c if ic reg is te r in s id e a d e v ic e

co m m a n d : < 1 2 > < re g is te r> < 0 7 > < slo t>

R ead th e c o n te n t o f th e D ev ice A ccess D a ta re g is te rco m m a n d : < 2 2 > < 0 0 > < 0 8 > < slo t>

< d e v reg _ d a ta> = > S b rc k C tl M em o ry 0 x 0 0 FA

D isa b le D e v ic e A cc es s reg is te rs< d a ta_ c> < = < M O reg _ d a ta > A N D 

co m m a n d : < 1 2 > < d ata_ c > < 0 8 > < s lo t>

1

3

2

4

5

re g is te rs lo o p< reg is te r> = 0 x 7 0 C lo ck D L L E rro r reg is te r 0 x 7 1 C lo ck F re q u en cy E rro r re g is te r 0 x 7 2 S Y N C E rro r reg is te r 0 x 7 3 C lo ck /S Y N C S e le c t S ta tu s re g is te r

6

7R e se t h is to ry in fo rm a tio n o n th e

B a ck p lan e R ig h t D riv er (c lo ck c o n tro lle r)co m m a n d : < 1 2 > < 0 1 > < 0 8 > < slo t>

P o in t th e D ev ice A c ce ss A d d ress re g is te r to th e D ev ice C o ntro l re g is te r

co m m a n d : < 1 2 > < 0 2 > < 0 7 > < slo t>

8

o p tion a l s tep

4.4 Output links devices procedures

4.4.1 Output link FIFO read

Figure 4.31, Read content of an output link FIFO.

Page 37

R e a d M o d e o f O p era tio n re g is te rco m m an d : < 2 2 > < 0 0 > < 0 4 > < slo t>

< M O re g _ d a ta > = > S b rc k C tl M em o ry 0 x 0 0FA

P o in t th e D ev ic e S ta tu s /C o n tro l re g is te r to a sp ec if ic B ac k -E n d d ev ice (0 x 0 to 0 x 5 )co m m an d : < 1 2 > < 0 x 0 ,d e v ic e > < 0 1 > < slo t>

E n a b le D e v ic e A c c ess re g is te rs< d a ta _ a > < = < M O re g _ d a ta > O R < 0 4 >co m m an d : < 1 2 > < d a ta _ a > < 0 4 > < slo t>

P o in t th e D ev ic e A c ce ss A d d re ss re g is te r to aL in k F IF O M e m o ry P o in te r re g is te r (0 x A D o r 0 x B D )

co m m an d : < 1 2 > < re g is te r> < 0 7 > < slo t>

D isa b le D e v ic e A cc es s reg is te rs< d a ta _ c > < = < M O re g _ d a ta > A N D 

co m m an d : < 1 2 > < d a ta _ c > < 0 8 > < slo t>

1

3

2

4

5

8

F IF O lo ca tio n lo o p< lo ca tio n > = < 0 0 > ..< 3 D >

P oin t th e M e m o ry P o in te r re g is te r to asp e c if ic lo c a tio n in s id e th e L in k F IF O (0 x 0 0 o r 0 x 3 D )

co m m an d : < 1 2 > < lo ca tio n > < 0 8 > < slo t>

P o in t th e D ev ic e A c ce ss A d d re ss re g is te r to aL in k F IF O D ata A c ce ss re g is te r (0 x A F o r 0 x B F )

co m m an d : < 1 2 > < re g is te r> < 0 7 > < slo t>6

7R e a d th e c o n te n t o f th e D e v ic e A c c ess D a ta re g is te r

co m m an d : < 2 2 > < 0 0 > < 0 8 > < slo t>< d e v reg _ d a ta > = > S b rc k C tl M e m o ry 0 x 0 0 FA

4.4.2 Output link FIFO Write

Figure 4.32, Write content of an output link FIFO.

Step 8 is specified in paragraph 4.4.1.

4.4.3 Output Link FIFO reset

Consist in the same procedure described in paragraph 4.4.2 for the output link FIFO write using <location_data> = 0x00.

Page 38

R e a d M o d e o f O p era tio n re g is terco m m a n d : < 2 2 > < 0 0 > < 0 4 > < slo t>

< M O re g _ d ata> = > S b rck C tl M e m o ry 0 x 0 0 FA

P o in t th e D e v ic e S ta tu s/C o n tro l re g is te r to a sp e c ific B a ck -E n d d e v ic e (0 x 0 to 0 x 5 )co m m a n d : < 1 2 > < 0 x 0 ,d ev ice > < 0 1 > < s lo t>

E n a b le D e v ic e A c ce ss re g is ters< d a ta _ a> < = < M O re g _ d a ta > O R < 0 4 >co m m a n d : < 1 2 > < d a ta _ a > < 0 4 > < slo t>

P o in t th e D e v ic e A c ce ss A d d res s re g is te r to aL in k F IF O M em o ry P o in te r re g is te r (0 x A D o r 0 x B D )

co m m a n d : < 1 2 > < re g iste r> < 0 7 > < slo t>

D isa b le D ev ice A cc es s reg is te rs< d a ta _ c> < = < M O re g _ d a ta > A N D 

co m m a n d : < 1 2 > < d a ta _ c > < 0 8 > < slo t>

1

3

2

4

5

9

F IF O lo c at io n lo o p< lo c a tio n > = < 0 0 > ..< 3 D >

P o in t th e M em o ry P o in te r re g is te r to asp e c ific lo ca tio n in sid e th e L in k F IF O (0 x 0 0 o r 0 x 3 D )

co m m a n d : < 1 2 > < lo ca tio n > < 0 8 > < slo t>

P o in t th e D e v ic e A c ce ss A d d res s re g is te r to aL in k F IF O D a ta A c ce ss re g is ter (0 x A F o r 0 x B F )

co m m a n d : < 1 2 > < re g iste r> < 0 7 > < slo t>6

7 W rite th e c o n te n t o f F IF O lo ca tionco m m a n d : < 1 2 > < lo ca tio n _ d a ta> < 0 8 > < slo t>

R E A D O u tp u t L in k F IF O(c o n ten t v er if ic a tio n )8

o p t i o n a l s t e p

4.4.4 Output link FIFO Configuration

Figure 4.33, Output link FIFO configuration.

Page 39

R e ad M o d e o f O p era tio n re g is te rco m m a n d : < 2 2 > < 0 0 > < 0 4 > < slo t>

< M O re g _ d a ta > = > S b rck C tl M e m o ry 0 x 0 0FA

P o in t th e D e v ic e S ta tu s /C o n tro l re g is te r to a sp e c ific B ac k -E n d d e v ic e (0 x 0 to 0 x 5 )co m m a n d : < 1 2 > < 0 x 0 ,d e v ic e> < 0 1 > < slo t>

E n ab le D ev ic e A c c ess re g is te rs< d a ta _ a> < = < M O re g _ d a ta > O R < 0 4 >co m m a n d : < 1 2 > < d a ta _ a > < 0 4> < slo t>

P o in t th e D e v ic e A c ce ss A d d res s reg is te r toL in k A F IF O C o n tro l re g is te r (0 x A E )

co m m a n d : < 1 2 > < A E > < 0 7 > < slo t>

D isa b le D ev ice A cc es s reg is te rs< d a ta _ c> < = < M O re g _ d a ta > A N D 

co m m a n d : < 1 2 > < d a ta _ c > < 0 8> < slo t>

1

3

2

4

5

8

W rite th e c o n f ig u ra tio n w ord to th eL in k A F IF O C o n tro l re g is te r

co m m a n d : < 1 2 > < c o n f ig _ w o rd _ A > < 0 8 > < slo t>

6

7

P o in t th e D e v ic e A c ce ss A d d res s reg is te r toL in k B F IF O C o n tro l reg is te r (0 x B E )

co m m a n d : < 1 2 > < A E > < 0 7 > < slo t>

W rite th e c o n f ig u ra tio n w ord to th eL in k B F IF O C o n tro l reg is te r

co m m a n d : < 1 2 > < c o n fig _ w o rd _ B > < 0 8 > < slo t>

o u tp u t lin k s d e v ic es lo o p < 0 x 0 ,d ev ic e > = < 0 0 > (D F E 1 _ Y P F P G A , link s 1 3 a n d 1 4 ) < 0 1 > < 0 2 > < 0 3 > < 0 4 > < 0 5 >

(D F E 1 _ B R F P G A , lin k s 1 5 , 1 6 a n d 1 7 ) (D F E 1 _ G O F P G A , lin k s 1 0 , 11 a n d 1 2 ) (D F E 0 _ B R F P G A , lin k s 0 5 , 0 6 a n d 0 7 ) (D F E 0 _ G O F P G A , lin k s 0 0 , 0 1 a n d 0 2 )(D F E 0 _ Y P F P G A , lin k s 0 3 an d 0 4 )

4.4.5 Triggering of Output Links FIFO

Figure 4.34, Triggering of Output Link FIFO.

4.4.6 Use of Output Links FIFOs

Figure 4.35, Use of Output Links FIFOs.

Step 1 is specified in paragraph 4.4.4. Step 2 and 3 are specified in paragraphs 4.4.2 and 4.4.3.

Step 4 is specified in paragraph 4.4.5. Step 5 is specified in paragraph 4.4.1.

Page 40

R ese t F IF O T rig g er C o n tro l reg iste rco m m a n d : < 1 2 > < 1 0 > < 11 > < slo t>1

2W rite th e tr ig g e r w o rd to th e

F IF O T rig g e r C o n tro l reg is te rco m m an d : < 1 2 > < tr ig g er_ w o rd > < 11 > < slo t>

C o n fig u re O u tp u t L in k s F IF O s1

5

If o pe ra tin g in T X M o de :W R IT E O u tpu t L in k s F IF O s2

Trig g e r O u tp u t L in k s F IF O s

If o p e ra tin g in R X M o d e:R E A D O u tp u t L ink s F IF O s

If o p e ra tin g in R X M od e :W R IT E O u tpu t L in k F IF O (re se t c o n ten t)

op tio na l s tep

3

4

4.4.7 Reset Output Links History Information

Figure 4.36, Reset output links history information

Page 41


co m m an d : < 1 2 > < 0 x0 ,d ev ice> < 0 1 > < slo t>

E n ab le D ev ice A ccess reg iste rs< d a ta_ a> < = < M O reg _ d ata> O R < 0 4 >co m m an d : < 1 2 > < d ata _ a> < 0 4 > < slo t>

o u tp u t lin k s d e v ic es lo o p < 0 x 0 ,d ev ice> = < 0 0 > (D F E 1 _Y P F P G A , lin k s 1 3 an d 1 4 ) < 0 1 > < 0 2 > < 0 3 > < 0 4 > < 0 5 >

(D F E 1 _ B R F P G A , lin k s 1 5 , 1 6 an d 1 7 ) (D F E 1 _ G O F P G A , l in k s 1 0 , 11 a n d 1 2 ) (D F E 0 _ B R F P G A , lin k s 0 5 , 0 6 an d 0 7 ) (D F E 0 _ G O F P G A , l in k s 0 0 , 0 1 a n d 0 2 )(D F E 0 _ Y P F P G A , lin k s 0 3 an d 0 4 )

1

3

2

4

5

6

R e ad M o d e o f O p e ra tio n reg iste rco m m an d : < 2 2 > < 0 0> < 0 4 > < slo t>

< M O reg _ d a ta> = > S b rck C tl M e m o ry 0 x 0 0 FA

P o in t to the D ev ice C o n tro l reg is te r in th e d e v ice

co m m a n d : < 1 2 > < reg is te r> < 0 7 > < slo t> < reg is te r> : 0 x 0 2

W rite 0 x 0 1 to th e D ev ice C on tro l reg iste r in th e d ev ice co m m an d : < 1 2 > < 0 1> < 0 8 > < slo t>

D isab le D ev ice A cc ess reg is te rs< d a ta_ c> < = < M O reg _ d ata> A N D 

co m m a n d : < 1 2 > < d ata_ c> < 0 8 > < slo t>

4.4.8 Output links Control Bits Masking

command (0x) Notes

<12><17><84><02> Write 0x17 to the Mode of Operation Register of all mixer boards in the subrack (subrack broadcast) to enable Device Access Registers.

<12><0x0,device><81><02>

Write byte <0x0, device> to the Device/Status Control register in all mixer boards (subrack broadcast). Sets the device select pointer to a particular device. There are 4 output links carrying control bits:

Output link 02 (orange) is on device 0x4 (DFE0 Green Orange FPGA)

Output link 05 (blue) is on device 0x3 (DFE0 Blue red FPGA)

Output link 12 (orange) is on device 0x2 (DFE1 Green Orange FPGA)

Output link 15 (blue) is on device 0x1 (DFE1 Blue red FPGA)

<12><reg_addr><07><slot>

Write byte <reg_addr> to the Device Access Address register (address <07>) of the mixer board in slot <slot>. This set the Device Access Address register to point inside the chosen device to the register having address <regaddr>.<regaddr> depends on the ounput link on which the control bits mask is to be modified:

<B2>: Link#02 Embedded Command Bits Mask register <A2>: Link#05 Embedded Command Bits Mask register <A2>: Link#12 Embedded Command Bits Mask register <B2>: Link#15 Embedded Command Bits Mask register

<07>: <offset> byte: board Device Access Address register address. The most significative three bits of the <offset> byte can be used for broadcasting control (see Figure 4.5).


<12><cb_mask><08><slot>

Write <cb_mask> to the Device Access Data register of the mixer board in slot <slot>. The byte <cb_mask> will be written to the register pointed by <reg_addr> in the device <device>. This will mask the control bits on output link specified by <reg_addr>.

<cb_mask> is the control bit mask and should be chosen depending on the control bits to be asked (see Figure 4.23 and Figure 4.24). <00>: masking disabled (equivalent to no masking) <FF>: masking enabled, no bit is masked <01>: all control bits are masked <DF>: only control bit at time slot 5 (L1 Accept) is masked.

<08>: <offset> byte: board Device Access Data register address. The most significative three bits of the <offset> byte can be used for broadcasting control (see Figure 4.5).


Repeat the last three commands as needed to mask the control bits on all the desired links.

<12><13><84><02> Write 0x13 to the Mode of Operation Register of all mixer boards in the subrack (subrack broadcast) to disable Device Access Registers.

<A1><00> End of list command. Stop the subrack controller execution of the commands in the command buffer.

Table 4.15, Example of command sequence to mask control bits on the output links.

Page 42

Figure 4.37, Output links control bits masking.

Page 43

P o in t th e D e v ic e S ta tu s /C o n tro l reg is te r to th e d e s ired d ev ice (0 x 4 ..0 x 1 )

co m m a n d : < 1 2 > < 0 x 0 , d ev ice > < 0 1 > < slo t>

E n a b le D e v ic e A c ce ss re g is te rs< d a ta _ a> < = < M O reg _ d a ta> O R < 0 4 >co m m an d : < 1 2 > < d a ta _ a > < 0 4 > < slo t>

1

3

2

4

5

7

6

R ea d M o d e o f O p era tio n re g is te rco m m an d : < 2 2 > < 0 0 > < 0 4 > < slo t>

< M O re g _ d a ta> = > S b rck C tl M em o ry 0 x 0 0 FA

P o in t to an E m b ed d ed C o m m an d B its M ask reg is te r < reg is te r> = 0 x A 2 o r 0 x B 2

co m m a n d : < 1 2 > < re g is te r> < 0 7 > < s lo t>

R ea d th e co m m an d : < 2 2 > < 0 0 > < 0 8 > < slo t>

< E C B M reg _ d ata> = > S b rck C tl M em o ry 0 x 0 0 FA

E m b e d d ed C o m m an d B its M ask reg is te r

W rite th e e m b e d d ed co m m a n d b its m ask co m m a n d : < 1 2 > < E C B M _ m a sk > < 0 8 > < slo t>

D isa b le D ev ice A cc es s re g is te rs< d a ta _ c> < = < M O re g _ d a ta> A N D 

co m m a n d : < 1 2 > < d a ta_ c > < 0 8 > < slo t>

O u tp u t lin k D ev ice E C B M ask reg . a d d re ss0 2 (o ran g e ) 0 x 4 (D F E 0 _ G O F P G A ) 0 x B 20 5 (b lu e ) 0 x 3 (D F E 0 _ B R F P G A ) 0 x A 21 2 (o ran g e ) 0 x 2 (D F E 1 _ G O F P G A ) 0 x B 21 5 (b lu e ) 0 x 1 (D F E 1 _ B R F P G A ) 0 x A 2

4.4.9 Output Links Control

Figure 4.38, Output links control

To be noted that the output links LVDS transmitters clock can be disabled for all the output links at once using the Board Controller’s Mode of Operation register.

Page 44

P o in t th e D ev ice S ta tu s /C o n tro l reg is te r to a sp e c ific d ev ice

co m m an d : < 1 2 > < 0 x 0 ,d e v ic e> < 0 1 > < s lo t>

E n a b le D ev ice A cc ess reg is te rs< d a ta_ a> < = < M O reg _ d a ta> O R < 0 4 >co m m an d : < 1 2 > < d ata_ a > < 0 4 > < slo t>

d ev ice reg is te rs lo o p < reg iste r> = < A 1 > (lin k s 0 0 /0 1 , 0 4 , 0 5 , 1 0 /11 , 1 4 , 1 5 ) , ( lin k s 0 2 , 0 3 , 0 6 /0 7 , 1 2 , 1 3 , 1 6 /1 7 )

1

3

2

4

5

R ea d M o d e o f O p e ra tio n reg is te rco m m an d : < 2 2 > < 0 0 > < 0 4 > < slo t>

< M O reg _ d a ta> = > S b rck C tl M em o ry 0 x 0 0 FA

P o in t th e L in k C o n tro l re g is te r < reg iste r> : 0 x A 1 , 0 x B 1

co m m an d : < 1 2 > < reg is te r> < 0 7 > < s lo t>

6

7

R e ad th e reg is te rco m m a n d : < 2 2 > < 0 0 > < 0 8 > < slo t>

< L C reg _ d a ta> = > S b rc k C tl M em o ry 0 x 0 0 FA

L in k C o n tro l

D isa b le D ev ice A cc ess reg is te rs< d a ta _ b > < = < M O re g _ d ata> A N D 

co m m an d : < 1 2 > < d ata_ b > < 0 8 > < slo t>

W rite n ew L in k C o n tro l reg is te r m askco m m an d : < 1 2 > < L C reg _ m ask > < 0 8 > < slo t>

o u tp u t lin k s d ev ices lo o p< 0 x 0 ,d e v ice> = < 0 0 > (D F E 1 _ Y P F P G A , lin k s 1 3 an d 1 4 ) < 0 1 > < 0 2 > < 0 3 > < 0 4 > < 0 5 >

(D F E 1 _ B R F P G A , lin k s 1 5 , 1 6 a n d 1 7 ) (D F E 1 _ G O F P G A , l in k s 1 0 , 11 an d 1 2 ) (D F E 0 _ B R F P G A , lin k s 0 5 , 0 6 a n d 0 7 ) (D F E 0 _ G O F P G A , l in k s 0 0 , 0 1 an d 0 2 )(D F E 0 _ Y P F P G A , lin k s 0 3 an d 0 4 )

4.5 System procedures

4.5.1 Mixer System reset

Figure 4.39, Mixer System reset

Page 45

1

2

W rite to b o ard s ta tu s /co n tro l reg is te ro f a ll M aste r b o a rd s (m ix er b o ard # 1 )

co m m an d : < 1 2 > < 4 2 > < 0 0> < 0 2 >

W rite to b o ard s ta tu s /co n tro l reg is te ro f a ll M aste r b o a rd s (m ix er b o ard # 1 )

co m m an d : < 1 2 > < 4 0 > < 0 0> < 0 2 >

3W rite to b o ard s ta tu s /co n tro l reg is te r

o f s lav e b o a rd s (m ix e r b o ard # 2 , 3 , 4 ) co m m an d : < 1 2 > < 4 2 > < 0 0> < slo t>

4W rite to b o ard s ta tu s /co n tro l reg is te r

o f s lav e b o a rd s (m ix e r b o ard # 2 , 3 , 4 ) co m m an d : < 1 2 > < 4 0 > < 0 0> < slo t>

slo t lo o p< slo t> = < 0 x 0 5 > ..< 0 x 0 3 >

re se t m a ste r b o a rd s(M ix e r b o ard # 1 ,s lo ts# 2 , 6 , 10 , 1 4 , 1 8 )

re se t s lav e b o ard s(M ix e r b o ard # 2 , s lo ts# 3 , 7 , 11 , 1 5 , 1 9

)M ix e r b o ard # 3 , s lo ts# 4 , 8 , 1 2 , 1 6 , 2 0

M ix e r b o ard # 4 , s lo ts# 5 , 9 , 1 3 , 1 7 , 2 1


4.5.2 Mixer System Extended Reset

Figure 4.40, Mixer System extended reset

Steps 1 and 2 specified in paragraph 4.1.6. Steps 2 and 4 specified in paragraph 4.1.13.Steps 5 and 6 consist in the sequance of steps from 5 to 7 of the procedure specified in 4.2.1.Step 7 is specified in Figure 5.49.

Page 46

1

3

2

4

R eset M as te r B o a rd s

R ese t M as te r B o ards H is to ry

R ese t S la v e B o a rd s

R ese t S lav e B o ards H is to ry

D isab le la tc h in g o n in p u t lin k s s ta tu s reg is te rs

E n ab le la tc h ing o n in p u t lin k s s ta tu s re g is te rs

S e t L E D m o n ito rin g m o d e to M o de # 1 4

5

7

6

4.5.3 Mixer System power-up initialization

Figure 4.41, Mixer System Power-up initialization

Step 1 is automatically performed by the subrack controller using the command sequances stored in the “autoexec.000” and “autoexec.001” files.

Step 2 is specified in paragraph 4.5.2.

4.5.4 Mixer System configuration erasing

Figure 4.42, Mixer System configuration erasing.

Page 47

C o n fig u re M ix e r B o a rd s1

2

T h is s tep is au to m a tic a lly p e rfo rm e d b y th e su b rac k c o n tro lle ru s in g th e f ile s : “a u to e x ec .0 0 0 ” an d “au to ex ec .0 0 1 ” s to red o n th e co m p ac t f la sh .

M ix e r S y stem E x ten d ed R ese t

1

2

R e ad M o d e o f O p e ra tio n reg is te r o n o n e b o a rdco m m a n d : < 2 2 > < 0 0 > < 0 4 > < 0 2 >

< M O reg _ d ata > = > S b rck C tl M em o ry 0 x 0 0 FA

W rite to M o d e o f O p e ra tio n reg is te r o f a ll b o ard s< d a ta_ a > = < M O reg _ d a ta > O R < M O re g _ m as k _ B >

co m m a n d : < 1 2 > < d a ta _ a> < 8 4 > < 02 >o n a ll m ix e r b o a rd s< M O reg _ m ask _ A > = 

E n ab le E ras in g D ev ice C o n fig u ra tio n

3 W rite to D e v ic e S ta tu s /C o n tro lreg is te rco m m a n d : < 1 2 > < 4 0 > < 8 1 > < 0 2 >

S e ttin g th e b it “P R O G ” to “1 ” o n d ev ice # 0o n a ll m ix er b o ard s fo rc e th e e ra s in g o f co n fig u ra tio n o n a ll d ev ice s

4 W rite to D e v ic e S ta tu s /C o n tro lreg is te rco m m a n d : < 1 2 > < 0 0 > < 8 1 > < 0 2 >

S e ttin g th e b it “P R O G ” to “0 ” o n d ev ice # 0en a b le d ev ice s to ac ce p t n e w co n fig u ra tio n

5 W rite to M o d e o f O p e ra tio n reg is te r o f a ll b o ard s< d a ta_ b > = < M O reg _ d ata > A N D < M O reg _ m ask _ B >

co m m a n d : < 1 2 > < d ata _ b > < 8 4 > < 0 2 >

D isab le E ra s in g D e v ice C o n fig u ra tio no n a ll m ix er b o ard s .< M O reg _ m ask _ B > = 

R ead M o d e o f o p e ra tio n reg is te r c o n ten t o n o n eb o ard (fo r e x am p le s lo t2 ) a n d u se it fo r a l l th e b o ard s in th e sy s te m in s te p # 2 .

d ev ice s lo op< 0 x 0 ,d ev ic e> = < 0 x 0 0 > ..< 0 x 0F >

R e ad S u b ra c k C o n tro ller S ta tu s w ord

1

4

2

5

Is S u b rac k C o n tro lle rB U S Y ?

N o

Yes

R e ad b oa rd co n fig u ra tio n s ta tu san d d e v ic e’s f irm w a re ID

o n a ll m ix e r b o ard s

- < s lo t> : s lo t nu m b er, < 0 x 0 2> .. < 0x 0 5 >- < filen a m e H > < filena m eL > : tw o b y tes f ile n am e, sh ou ld m a tch th e f irs t fou r d ig i ts o f th e co n figu ra tio n file n a m e s to re d o n the su b rac k co n tro l ler C o m p ac tF lash m em o ry c a rd . T h e co n v e n tio n u sed is : < filen a m eH > = < slo t> < filen a m eL . = < 0 x ,d ev ic e>

B ro a d cas t w rite to th e D ev ic e F irm w are ID reg iste rco m m a n d : < 1 2 > < firm w are ID > < 4 3 > < slo t>

3

B ro ad cas t W rite to D ev ice S ta tu s /C o n tro lreg is terto se t d e v ice se lec t to a sp e cific de v ice

co m m a n d : < 1 2 > < 0 x 0 ,de v ic e> < 81 > < 02 >

slo t loo p< slo t> = < 0 x 0 2> ..< 0 x0 5 >

D o w nlo ad file to b a ck p lan e (to co n fig u re d ev ice )com m a n d :

< 5 3> < 00 > < 4 2> < slo t> < file n am eH > < file na m eL >

6


4.5.5 Broadcast configuration of the mixer system

The procedure is illustrated in Figure 4.43 and follows the same steps used to automatically configure the mixer system at power-up. The command sequence used at power-up is stored in two “autoexec” command files on the subrack controller Compact Flash memory card. Steps 2 and 3 are not used for automatic power-up configuration but are needed when issuing commands remotely. The firmware ID byte can assume any value and at the moment no convention has been established for the mixer system. Step 6 is described in procedure XYZ and is used to verify that the successful configuration of the mixer system.

Figure 4.43, broadcast configuration of the mixer system

Page 48

RESET

3

51

2

04

7

6

812

913

1014

1115

3. 3 2. 5

01

00

02

03

0405

1514131211

3 2s ig n a l se t# 03 2s ig n a l se t# 1

3 2s ig n a l se t# 1 5

3 2 s ig n a l s tre tc h in g1 5 0 m sec m in

3 21 6

1 6

1 6 1 6

1 6

G re en L E D s

R e d L E D s

M o n ito rin g S ta tu s H ig hre g is te r

M o n ito rin g S ta tu s H ig hH is to ry reg is te r

M o n ito rin g S ta tu s L o wH is to ry reg is te r

M o n ito rin g S ta tu s L o wre g is te r

re se t b u tto nre se t b u tto n

fro n t p a n e l b i-c o lo r L E D s

se le c t L E D s M o n ito rin g M o d e(s ig n a l se t)

la tch L E D s

se lec t L E Dm o n ito r se t

M o n ito rin g M o d ere g is te r

m o n ito r in g m o d e

M o d e o f O p era tio nre g is te r

en ab le L E D s to sh o wm o n ito r in g m o d e

re se t h is to ry w h enM o n ito rin g M o d e reg iste r

is acc e ssed in w rit in g


5. Use of the LEDs Monitoring Mode

Figure 5.44, Front panel LEDs and LEDs monitoring mode

Figure 5.45, Mode of Operation register

Page 49

| 7 6 5 4 | 3 2 1 0 |

M o d e o f O p era tion R eg is te r A d d re ss : ox 0 4 (R E A D /W R IT E )

E n a b le L E D s to sh o w M o n ito rin g M o d eE n ab le D e v ice A cce ss R eg is te rsE n a b le E ra s in g D ev ice C o n fig u ra tio nE n a b le LV D S T X s c lo ck

E n ab le L a tch in g in th e In p u t L in k s S ta tu s R e g is te rs

| 7 6 5 4 | 3 2 1 0 |

M o n ito rin g M o de R e g is te r A d dress : ox 0 B (R E A D /W R IT E )

se lec t L E D M o n ito rin g M o d e0 0 0 0 M o d e 0 : in p u t lin k s c lo ck a n d D L L s ta tu s0 0 0 1 M o d e 1 : in p u t lin k s S Y N C b it s ta tu s0 0 1 0 M o d e 2 : in p u t lin k s w a lk in g 1 p a tte rn d e tec tio n0 0 11 M o d e 3 : in p u t lin k s w a lk in g 0 p a tte rn d e te c tio n0 1 0 0 M o d e 4 : in p u t lin k s S Y N C b it s ta tu s a f te r s y n c h ro n iza tio n0 1 0 1 M o d e 5 : in p u t lin k s fram e sy n ch ro n iza tio n s ta tu s0 11 0 M o d e 6 : o u tp u t lin k s tes t p a tte rn d e tec tio n ( lin k # 0 o n ly )0 111 M o d e 7 : in p u t lin k s co n tro l b its s tre am m o n ito rin g1 0 0 0 M o d e 8 : lo ca l b u s m o n ito rin g1 0 0 1 M o d e 9 : b ack p lan e c o n tro l s ig n a ls an d se ria l b u s m o n ito r in g1 0 1 0 M o d e 1 0 : b ack p lan e p a ra lle l b u s ad d ress m o n ito r in g1 0 11 M o d e 11 : b ack p lan e p a ra lle l b u s d a ta m o n ito r in g11 0 0 M o d e 1 2 : F P G A s c o n fig u ra tio n s ta tu s11 0 1 M o d e 1 3 : o u tp u t lin k s tes t m o d e en ab le s ta tu s111 0 M o d e 1 4 : in p u t lin k s s ta tu s1111 M o d e 1 5 : L E D s tes t (a l l L E D s O N )

E n a b le L E D L a tc h M o d eL E D m on ito r se t (G re en /R ed )M o d e# 1 5 L E D s O N /O F F

| 7 6 5 4 | 3 2 1 0 |

M o n ito rin g S ta tu s H ig h R eg is te r A d d ress : o x 0 D (R E A D O N LY )

G ree n L E D # 8 s ta tu sG ree n L E D # 9 s ta tu sG ree n L E D # 1 0 sta tu sG ree n L E D # 11 s ta tu sG ree n L E D # 1 2 sta tu sG ree n L E D # 1 3 sta tu sG ree n L E D # 1 4 sta tu sG ree n L E D # 1 5 sta tu s


Figure 5.46, Monitoring Mode Register

Figure 5.47, Monitoring Status Registers

Figure 5.48, Monitoring Status History Registers

Page 50

| 7 6 5 4 | 3 2 1 0 |

M on ito rin g S ta tu s L o w R e g is te r A d dress : ox 0 C (R E A D O N LY )

G reen /R e d L E D # 0 s ta tu sG reen /R e d L E D # 1 s ta tu sG reen /R e d L E D # 2 s ta tu sG reen /R e d L E D # 3 s ta tu sG reen /R e d L E D # 4 s ta tu sG reen /R e d L E D # 5 s ta tu sG reen /R e d L E D # 6 s ta tu sG reen /R e d L E D # 7 s ta tu s

| 7 6 5 4 | 3 2 1 0 |

M on ito rin g S ta tu s L o w H is to ry R e g is te r A d d re ss : o x 0 E (R E A D O N LY )

G reen /R ed L E D # 0 h is to ryG reen /R ed L E D # 1 h is to ryG reen /R ed L E D # 2 h is to ryG reen /R ed L E D # 3 h is to ryG reen /R ed L E D # 4 h is to ryG reen /R ed L E D # 5 h is to ryG reen /R ed L E D # 6 h is to ryG reen /R ed L E D # 7 h is to ry

| 7 6 5 4 | 3 2 1 0 |

M o n ito r in g S ta tu s H ig h H is to ry R eg is te r A d d ress : o x 0 F (R E A D O N LY )

G re en /R ed L E D # 8 h is to ryG re en /R ed L E D # 9 h is to ryG re en /R ed L E D # 1 0 h is to ryG re en /R ed L E D # 11 h is to ryG re en /R ed L E D # 1 2 h is to ryG re en /R ed L E D # 1 3 h is to ryG re en /R ed L E D # 1 4 h is to ryG re en /R ed L E D # 1 5 h is to ry

1 <22><00><0B><slot>

Read the content of the Monitoring Mode register.


<00>: unused byte.

<0B>: <offset> byte, Device Access Data address.


The read data byte <MMreg_data > will be available in the subrack controller General Purpose Memory at location 0x00FA.

2 <12><data_a><0B><slot>

Write to the Monitoring Mode register.


<data_a>: (<MMreg_data> AND <bxxxx0000>) OR < MMreg_mask >.Is the logic AND of the byte obtained from the previous operation (<MMreg_data>) and <bxxxx0000> to reset the four least significative bits to “0”. The result is then ORed with the desired mode:<MMreg_mask> = <b0000, mode>.

In <bxxxx0000> the “bxxxx” are four non-care bits meaning that the AND operation is not performed on them and “mode” are four bits representing the desired monitoring mode. The four bxxxx bits can be replaced by a different set of bits to enable/disable some of the monitoring features such as “Enable LED latch Mode”, select the “LED Monitoring set (green/red)”, turn the LEDs ON/OFF in monitoring mode #15, see Figure 5.46.

<0B>: <offset> byte, Monitoring Mode register address. The most significative three bit of the <offset> byte can be used for broadcasting control (see Figure 4.5).


Table 5.16, Monitoring Mode change

Figure 5.49, Monitoring Mode change

Figure 5.50, Enable/Disable LEDs to show monitoring mode

Page 51

1

2

R e ad M o n ito rin g M o d e reg is te rco m m an d : < 2 2 > < 0 0 > < 0 B > < slo t>

< M M reg _ d a ta> = > S b rck C tl M em o ry 0 x 0 0 FA

W rite to M o n ito rin g M o d e reg is te rco m m a n d : < 1 2 > < d a ta _ a> < 0 B > < slo t>

< d a ta_ a> = (< M M re g _ d a ta> A N D ) O R 

1

2

R ead M o d e o f O p e ra tio n reg is te rco m m an d : < 2 2 > < 0 0 > < 0 4 > < slo t>

< M O reg _ d a ta> = > S b rck C tl M em o ry 0 x 0 0 FA

W rite to M o d e o f O p era tio n reg is te rco m m an d : < 1 2 > < d a ta_ a> < 0 4 > < slo t>

E n ab le /D isab le L E D to sh o w m o n ito r in g m o d e< d a ta_ a> :< M O reg _ d a ta> A N D to D isab le< M O reg _ d a ta> O R to E n ab le

Figure 5.51, Read monitoring status and status history

Page 52

1

2

R e a d M o n ito r in g M o d e re g is te rco m m and : < 2 2 > < 0 0 > < 0 B > < slo t>

< M M reg _ d ata > = > S b rc k C tl M em o ry 0 x 0 0 FA

3

4

R e ad M o d e o f O p era tio n reg is te rco m m and : < 2 2 > < 0 0 > < 0 4 > < slo t>

< M O re g_ d a ta> = > S b rck C tl M em o ry 0 x 00 FA

C he c k c u rre n t m on ito rin gm o d e an d s e t ting s

C he c k if te L E D a re en ab led to sh o w th e m on ito rin g m o d e

R e ad M o n ito r in g S ta tu s H ig h reg is te rco m m an d : < 22 > < 0 0 > < 0 D > < slo t>

< M S H reg _ d a ta > = > S b rc k C tl M em o ry 0 x 0 0 FA

R e a d M o n ito r in g S ta tu s L o w re g is te rco m m an d : < 2 2 > < 0 0 > < 0 C > < slo t>

< M S L re g _d a ta> = > S b rc k C tl M e m ory 0 x 00 FA

5R e a d M o n ito r in g S ta tu s H ig h H is to ry reg is te r

co m m and : < 2 2 > < 0 0 > < 0 F > < slo t>< M S H H re g _d a ta> = > S b rck C tl M e m ory 0 x 00 FA

6R ea d M o n ito rin g S ta tu s L ow H is to ry re g is te r

co m m an d : < 22 > < 00 > < 0 E > < slo t>< M S L H re g _ da ta > = > S b rck C tl M e m o ry 0 x 0 0FA

R e a d cu rren t L E D s s ta tu s

R e a d L E D s s ta tu s h is to ry

op tio n a l s tep s


6. Problem reporting

6.1 Report a problem to mixer system support

Stefano M. Rapisarda

E-mail: [email protected]

Phone: (630) 840-6559.

Neal G. Wilcer


Phone: (630) 840-2749.

Computing and Engineering for Physics Application Department

Electronics Systems Engineering Section

Names and emails available on the ESE Section web page:

http://www-ese.fnal.gov/

6.2 Report a problem to AFE system support

George Ginther


Phone: (630) 840-6337.

Fred Borcherding


Phone: (630) 840-3164.

John T. Anderson


Phone: (630) 840-8885.

Page 53

mailto:[email protected]






7. References

[1] Jamieson T. Olsen,

a) "Digital Front End Mother Board register map", Engineering Note 2000-01-28a.

b) "DFE and Mixer Board Registers ", Engineering Note 2000-01-28a.

c) "DFE backplane address/data bus protocol", Engineering Note 2000-03-28a.

d) "DFE slow monitoring custom serial bus specification", Engineering Note 2000-01-31a.

e) Digital Front End Controller (DFEc) Board:http://d0server1.fnal.gov/users/jamieson/www/projects/dfec/index.html

f) “DFE Crate Controller (DFEC) Command Structure and 1553 Interface Specification”,Engineering Note 2001-04-16a.

Information available on the internet: http://d0server1.fnal.gov/users/jamieson/www/index.html

[2] Robert D. Angstad, technical documentation.Information available on the internet:http://d0server1.fnal.gov/users/angstadt/www/datapump/datapump.htm

[3] John T. Anderson,

a) “D-Zero Central Fiber Tracker 8-MCM Analog Front End Board, Design Specification”, January 7, 2000.

Information available on Internet:http://d0server1.fnal.gov/users/janderson/Public_Eng_Notes/default.html.

[4] Mixer System documentation

a) Neal Wilcer, John Anderson, Stefano Rapisarda “Central Tracker Trigger (CTT) Mixer System Backplane Description & Power Distribution Specification”, July 4, 2000. Document#: ESE-D0-000704.

b) Makoto Tomoto, "Note on cable mapping from AFE to Mixer", October 26, 2001.

c) Central Tracker Trigger (CTT) Mixer System Test Procedures.

d) Central Tracker Trigger (CTT) Mixer System.

The mentioned documents and several others are available on Internet: http://www-ese.fnal.gov/D0_CTT_Mixer/

Page 54

http://www-ese.fnal.gov/D0_CTT_Mixer/

http://d0server1.fnal.gov/users/janderson/Public_Eng_Notes/default.html

http://d0server1.fnal.gov/users/angstadt/www/datapump/datapump.htm

http://d0server1.fnal.gov/users/jamieson/www/index.html

http://d0server1.fnal.gov/users/jamieson/www/projects/dfec/index.html

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