LogKola.ppt - tnt.etf.rs
Transcript of LogKola.ppt - tnt.etf.rs
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Familije, osobine i realizacija logičkih kolalogičkih kola
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TTL
• Kašnjenje u ns
• Standard 10
• LS 10• LS 10
• ALS 4
• S 3
• F 2
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ECL
XNILI ILIY
\Z Z-Vref
-VEE
I1
I2I3
24
5 3
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MEC I 8nS MEC II 2nS MEC III (16XX) 1nS101xx 100 series 10K ECL, 3.5nS102xx 200 series 10K ECL, 2.5nS108xx 800 series 10K ECL, voltage compensated, 3.5nS10Hxxx 10K - High speed, voltage compensated, 1.8nS10Hxxx 10K - High speed, voltage compensated, 1.8nS10Exxx 10K - ECLinPS, voltage compensated, 800pS100xxx 100K, temperature compensated 100Hxxx 100K - High speed,temperature compensated 100Exxx 100K - ECLinPS, temp, voltage comp., 800pS
Integrisano 150ps
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• Potrošnja skoro da ne zavisi od prekidanja
• 25 x brži od najbržeg CMOS-a
• Niska integracija
• Može GaAs
• Primena – ALU superkompjutera• Primena – ALU superkompjutera
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Realizacija logičkih kola u CMOS tehnologijiCMOS tehnologiji
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Fizička realizacija CMOS invertora
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Zaštita
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Moraju na ulazima da budu obe nule da bi na izlazu bila jedinica
NEBAFERISAN NILI
X Y Z X Y X Y 2
31
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VDD
A
Y
C
B
U1
NOR3CB
AY
Prenosna funkcija
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Dvostruko baferisanje
22 2
DSD GS T DS DS DD T DS
om
B VI V V V V B V V V
r
ox
WB C
L
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1 2 3 4 5 6
3 4 5 62
34
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NILI i ILI
2
31 1 2 3 4 5 6
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NI i I
1 2 3 4 5 62
34
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Y
VDD
1
23
1
23EN
X
Y
EN
X 1 3
2Trostatička kola
Y=X
VDD
EN=1
X
Y=Hi Z
VDD
EN=0
X 0
1
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Integrisano kolo 74HC241
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SRAM
CLK2
D1
Q3
CLK2
D1
Q3
1 3 1 3
A0 S0
A9
A1
S 1023
Dekoder
CLK2
D1
Q3
CLK2
D1
Q3
CS
1
23
1
23
WE
OED7D0
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Povezivanje memorija na magistralu
A010
A19
A28
A37
A46
A55
A64
A7325
D011
D112
D213
D315
D416
D517
D618
D719
U1
A[0:15]
D[0:7]
A0A1A2A3A4A5A6A7A8
D0D1D2D3D4D5D6D7
A010
A19
A28
A37
A46
A55
A64
A73
A82524
D011
D112
D213
D315
D416
D517
D618
D719
U2
A1A0
A4A3A2
A6A5
A9A8A7
D1D0
D4D3D2
D7D6D5
\WR
\RD
142
3
U4
A15A14A13
A7A8
25
A924
A1021
A1123
A122
CS120
OE22
WE27
D7A8A9A10A11A12
142
3
U5
A8A9
24
A1021
A1123
A122
CS120
OE22
WE27
A9
A12A11A10
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Bidirekcioni bafer74HC245
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Kola sa otvorenom drejnom (kolektorom)
1 2
Y
X 1 2X Y
1 0
0 Hi Z
X Y
X Y
Kod TTL logike, na izlazu je NPN tranzistor
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Primena – wired OR logikaPrimer 1: komparator
X0Y0 1
2
3
12
3
VDD
X1
Yn
Y1
Xn
Z
12
3
12
3
12
3
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Alternativna klasična realizacija
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Primer 2 Zajednički prekid od više periferija (prekid je aktivan na log. nulu
VDD
INTR
PerNPer1
D7
13
2
13
2
13
2
13
2
1
23
1
23
CS2CS1
RD
D[0..7]
D0 D7D0D7
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Bilateralni prekidač(transmisioni gejt)
DDVTG
DDV
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Bilateralni prekidač i serijska logika:primer exor
XOR 74HC86
Ušteda u površini, potrošnji
1,
0,
B Y A
B Y A
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Analogni multiplekser-demultiplekser 2/1
Vout
V0
D0
Q
1 2 1 2A0
Vout
V1
Q
D1
A
2 2 2 2 8tran invertoriprekidacin
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1
23
1
23
1
23
1 2 1 2A
D1
D0
Q
21 2 1 2A
3 4 2 2 16tran invertoriNIn
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D0 D0
D1
A
Q
D1
D2 D0
D3Q
D1
Q
D1
D0
A
Q
Mux 4/1
A
D1
A1A0
3 4 2 4 20
* 3 12 2 4 44
tran prekidaci invertori
tran NI invertori
n
n
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BICMOSVDD
1 2
142
3
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Ostale MOS tehnologije
• NMOS / Pseudo NMOS• SCL• Dinamička logika• Domino logika• Adijabatska logika• Adijabatska logika• Clocked CMOS Logika (C 2 MOS). • NP Domino Logika (Zipper CMOS). • Cascade Voltage Switch Logika (CVSL). • Source Follower Pull-up Logika (SFPL).
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Kola niskog i srednjeg stepena integracijePakovanje
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Ne isplati se ni po jednom kritetijumu = ne radi se!