. Semiconductor Research Group National Taipei University of Technology 1...

1. Semiconductor Research Group National Taipei University of Technology

矽奈米元件電物理特性及量測

Heng-Sheng Huang主講 : 黃恆盛教授國立台北科技大學機電整合所

Nov. 28, 2001


ContentsContentsNano device revolution - silicon age? or other materials ?

Silicon nano device physical limits - ELJ effect,MSJZ effect,SDE tunneling effect.Nano silicon device measurement - the C-R method

Conclusions


Silicon Age or Other Materials?


奈米電子世紀何時來？

半導體的故事


Semiconductor Road Map

182535

5070100130

180250350

500800

1 TB(2023)

1

10

100

1000

10000

1989 1990 1993 1996 1999 2002 2005 2008 2011 2014 2017 2020 2023 2026

1.E+05

1.E+06

1.E+07

1.E+08

1.E+09

1.E+10

1.E+11

1.E+12

1.E+13

1.E+14

1.E+15

Ga

te L

en

gth

year

Tra

ns

isto

r Nu

mb

er pe

r c

hip

Increasing Technology difficulty

Neuron Number in Brain

64GB(2015)

DRAM1.4 Times/Year

(nm)1015

1014

1013

1012

1011

1010

109

108

107

106

105


Scaled-Down Device Characteristics

Source: IEEE Spectrum,

July 19990.02 0.05 0.1 0.2 0.5 1

0.1

0.2

0.5

1

2

5

10

1

2

5

10

20

50

MOSFET channel length, m

Vdd

Vt

tox

2003-2006

Ga

te o

xc

ide

th

ick

nes

s,

nm

Po

wer s

up

ply

an

d t

hre

sh

old

vo

ltag

e,

V




July 1999


Year

Gate Length

Gate Oxide Thickness

Gate Leakage Current

Threshold Voltage

Power Supply

2020

0.018m

<10Å

0.05A/m2

(50 times of off current)

<0.1V

≦0.6V

2000 – 2006

0.13m – 0.10m

~20Å

~0.05nA/m2

(1/20 of off current)

0.3V

1V



CMOS Revolution

IG ~ A – Gate dielectric materials (low tunneling leakage)

VT ~ 0.2V – Control gate materials (фms optimization),channel engineering

VDD ~ 0.6V – high k dielectric materials

BJT-like CMOS?

gate

gatetgi CCVV

4.0


TECHNOLOGY IN THE INTERNET ERAFuture Scaling Beyond Bulk CMOS

Single Electronics

Today 2020 2040

Molecular Switch

Nanotubes

RTD

RTD

RTD

BulkCMOS

SOI

Vertical Gate Structure


Number of transistors on a chip in thousands

1

1b

100,000

10,000

1,000

100

10

'70 '75 '80 '85 '90 '95 '00 '05 '15'10

processors

‘25‘20 ‘30

100b

10b

Moore’s law prediction

4004

8080

8086

8028680386

80486

PentiumPentium Pro

Pentium II

Pentium III

Pentium III Xeon

1-billion transistors

100-billion transistors

CPU with Multimedia Capability Road Map


2020 0.0180.018mm Ultimate Generation?

2020 – 2040 or 2050 Integration Continues.

2015 64GB DRAM

1-Billion-Tx CPU

2025 1TB DRAM VDD=0.6V, VT=0.1V

100-Billion-Tx CPU IG ~ A

2050 32TBTB DRAM VDD<0.6V, VT=0.1V

4-TrillionTrillion-Tx CPU IG ~ A

Integration Revolution — A Monster


RAM

RAM

RAM

CPU

ASIC

ROM

ROM

ROM

DSP PLD

A/MS

Board components

A/MS=analog/mixed signalASIC = application-specific ICCPU = central processing unitPLD = programmable logic device

CPUcore

DSPcore

DSPbook

I/O pads

I/O pads

Memory

Control

A/MS

I/O p

ads

I/O p

ads

Virtual componentsSOURCE: MENTOR GRAPHICS CORP.

Is it possible to design a 100-Million-Transistor Chip in 100 Days


Technology Convergence

Digital Revolution

Mainframe/Minicomputer

CentralizedComputing

Host-basedNetwork

PersonalComputing

Client-ServerNetwork

Internet/Intranet InformationNetwork

Network-CentricComputing

Computer

Comm.ConsumerElectronics

Telephonewith S/W(Switch)

Analog-based/BroadcastTV, VCR, ...

Comm.

Computer

Consumer Electronics

SPC

WAN/Data Comm.

Very littleMultimedia CATV

Comm.

Computer


IN

LAN

Video phone/conferencing

Digital TV

MPEG-II

Comm.

Computer


Digital Convergence heading to

We are hereWe are hereWe are hereWe are here


Personal IA ( Mobile Phone: Smart/Super)

SoC(CPU + DSP +

RF + EmbeddedMemory + …)

Netw

ork

ing

(A

ccess S

ecu

rity &

Traffic

)

Ho

me

IA

(A/V

)

RTOS

RTOS

Mobile IP W

AP

Protocols: & Middle ware

Enterprise (Thin Clients: WBT, …)

Services / SWDevelopment

ISP/ASP

Internet Services & Networking

NSP

Applications Development

IA 產業組成圖


Nano device physical limits

ELJ effect (Extension Lateral Junction Effect)


Inconstant Unit Channel Conductance Model(Inconstant Channel Oxide Thickness Model)

Ids~μeff Cox (Leff ) W /Leff(Vg-Vth) Vds

(ELJ effect)


Lmet =Li+Lj,dep

Leff =Li+Lj,dep+Lacc =Lmet+Lacc

≒Lmet( ifθ’ 1≒ )

Lacc =Ldj,acc+Lsj,acc 2(L≒ j-Lovlap)

=2Lovlap[(1/ θ’)-1]

LQVLQQQL

Q

VLQLQQQL

Q

accsaccddsaccdaccs

accjsaccdacc

effacc

dsdjsjisjdji

djisjidepfj

effj

,,,,

,,

,

,,

,,,

,

)(

)(

)(

)(

The Relationships among Various Length Definitions

ELJ Effect


Rchannel =Ri,MOS + Ri,dep + Racc

=[(Li/Qi )+( Lj,dep /Qj, eff )+( Lacc /Qacc,eff )] /µeffW

= Leff[(α/Qi )+( β/Qj, eff )+( γ /Qacc,eff )] /µeffW

= Leff /µeff Qi, eff W =Vds / Ids ~ Leff / Qi, eff W (4.1)

Here, α(Leff)+ β(Leff) + γ(Leff) = 1,and

Qj, eff = Lj,dep (Qi,sj Qi,dj ) /( Qi,dj Lsj,dep + Qi,sj Ldj,dep(Vds)) (4.2)

Qacc, eff = Lacc (Qd,accQs,acc ) /(Qd,acc Lsj,acc + Qs,acc Ldj,acc(Vds)) (4.3)

Qi, eff(Leff) = 1/ [(α/Qi )+( β/Qj, eff )+( γ /Qacc,eff )]

= (Vg-Vt) Cox,eff (Leff)= (Vg-Vt) εox /dox,eff(Leff)

As Vds is small, µeff constant for devices without ≒

halo implant

The Channel Resistance


For advanced MOS devices(γ 0 as θ’ 1 and V≒ ≒ ds is small)

Qi, eff(Leff) 1/ [(α/Q≒ i )+( β/Qj, eff )]

≒ (Vg-Vt) Cox,eff (Leff) ≒ (Vg-Vt) εox /dox,eff(Leff)

For a long channel device(α>>β)

Qi, eff(Leff) ≈ 1/[(α/Qi)+(β/Qj, eff)] Q≒ i(constant)

= (Vg-Vt)Cox(constant)=(Vg-Vt)εox /dox(constant)

Rchannel = Leff / µeff Qi,eff W ~ Leff / W

For a short channel device

α β

Qi,eff(Leff) and Cox,eff (Leff)

dox,eff(Leff)

The Channel Resistance

PS: Qi =CoxV

Cox=εox/dox

The unit channel conductance G = μCox


0.0 0.4 0.8 4 8 12

0.4

0.8

1.2

1.6

2.0

2.4

0.4

0.8

1.2

1.6

2.0

2.4

(um)

ox

ox C Ratio d Ratio

With halo implant,Tilted 00

N¢wdose = 2E15 , As

ox,c

onst

ant

ox,e

ff

ox,c

onst

ant

ox,e

ff

eff

d

/

d

C

/

C

L

The Relationship between Cox,eff (or dox,eff ) and Leff


The Relationship between Cox,eff (or dox,eff ) and Vds

0.0 0.2 0.4 0.6 0.8 1.0 4 8 120.2

0.4

0.6

0.8

1.0

1.2

1.4

1.6

1.8

2.0

2.2

2.4

2.6

2.8

3.0

0.2

0.4

0.6

0.8

1.0

1.2

1.4

1.6

1.8

2.0

2.2

2.4

2.6

2.8

3.0

V

V

V

VV

VV

V

(um)

oxds

ds ox

V =0.1 for d Ratio 0.2 0.3 0.4

V =0.1 for C Ratio 0.2 0.3 0.4



ox,c

onst

ant

ox,e

ff

ox,c

onst

ant

ox,e

ff

eff

d

/

d

C

/

C

L

Rchannel(Vds)=Leff(Vds)/WµeffQi,eff(Vds)

~Leff(Vds)/Qi,eff(Vds) ~ 1/Qi,eff(Vds )

Leff is nearly Vds independent

(or weak dependent)

Therefore, as Vds

Qi,eff(Vds) Rchannel

dox,eff Cox,eff

The Inconstant Channel Conductance Model


0.0 0.4 0.8 4 8 12

0.4

0.6

0.8

1.0

1.2

1.4

1.6

1.8

2.0

2.2

2.4

0.4

0.6

0.8

1.0

1.2

1.4

1.6

1.8

2.0

2.2

2.4

¢õ

V

V

V

V

V

VVV

(£g )

gs ox

gs ox

V =1.5 for d Ratio 1.3 1.1 0.9

V =1.5 for C Ratio 1.3 1.1 0.9



ox,c

onst

ant

ox,e

ff

ox,c

onst

ant

ox,e

ff

effd

/

d

C

/

C

L

The Relationship between Cox,eff (or dox,eff ) and Vgs

Vgs ELJ Effect

dox,eff Cox,eff

The Effective Channel Conductance Model


The Effective Current Unit Factor G=μC

Without halo region G(Leff)=μoCox,eff(Leff)

With halo region G(Leff)=μhalo (Leff) Cox,eff(Leff)

The Inconstant Channel Conductance Model

Gate

N+

N+

P substrate-PP

halo implant

halo region

halo implant


The Mobility function , μhalo(Leff) , for NMOS

PS:the degradation of mobility due to special process step becomes measurable

0.0 0.4 0.8 4 8 120.0

0.4

0.8

1.2

0.0

0.4

0.8

1.2

(cm2/ V-s)

(um)

ox,e

ffef

fef

fef

fha

lo

eff

eff

effhalo£g (L )

eff

G(L

)

/G (

L

=10

um)

£g

(L

)

¡ÜG

(L

)/C

(L

)*

L

With a halo angle 00

With a halo angle 300


0.0 0.4 0.8 4 8 12

0.4

0.6

0.8

1.0

1.2

(um)

eff

halo

eff

eff

£g

(L

)

/£g

(L

=

10um

)

effL

NMOS with 300 halo tilt angle

PMOS with 300 halo tilt angle

No halo Region existing(without spike annealing process)

Mobility degradation due to halo impurity

The channel mobility difference between N/PMOS

PS:this technology is more important for nano device applications


Nano device physical limits

MSJZ(MOS-Surface Junction transistor –Zener)Effect


The surface channel can be partitioned to three regions

-NN

-

L (V )

Qi0

0.1Qi00.9Qi0

y

x

R-G region(surface zener region)

diffusion region(SJT region)

(MOS region)drift region

concentration of Q i(y)

W

slope

dQi0

dy

concentration of Q i0(Vds=0)

I diffusion, minority (e )I

R-GI ( drift, majority (h )I )drift, majority (e )I

diffusion, minority (e )I

concentration of Q

R-GI ( )diffusion, majory (h )IR-GI ( )diffusion, majory (h )I

concentration of Q

L ( )

s dd

effLeff

,, ,,

dsat j,sat

V >ds Vdsat

Vds surf

ace

conc

entr

atio

n of

car

rier

ssu

rfac

e co

ncen

trat

ion

of c

arri

ers


The MSJZ Model For Nano Mos Devices

1.The MOS/Surface-Junction-transistor/surface-Zener-diode

(“MSJZ”) model is set up and adopted “surface current equation”.

2.A novel MSJZ model that is used to describe the entire

channel current behaviors, considering the 2-D effect.

3.Current density and continuity equations:

Ids = Ids(y) = Idrift(y) + Idiffusion(y) + IR-G(y)(A/um)

4.The surface channel be partitioned to three regions:

drift region, diffusion region and R-G region.

(or MOS region, SJT region and surface-zener region)


V ( V )

I o

r I

(m

A/u

m)

(a) The load line method 0.0 0.5 1 1.5 2.0

Vg=1.5V for L =0.2um

Vg=1.1V for L =0.2um

eff

eff

0.67

0.43

0.16

0.075

Vg=1.5V for L =1um

Vg=1.1V for L =1umeff

eff

RS

JT

ds

Load line analysis before Ids saturation

0.0 0.4 0.8 1.2 1.6

eff

eff

eff

effLLLL

V

V

V

V

Vg=1.1

Vg=1.5

Vg=1.1

Vg=1.5

(mA

/um

)

(V)

=1um=1um

=0.2um

=0.2um1.0

0.9

0.8

0.0

0.1

0.2

0.3

0.4

0.5

0.6

0.7 W=10um

I

modulation

�

saturation behaviorD-D mode I

ds

ds

( V )

ds

dsV

without considering £]

D-D

m

ode

(b) The D-D mode current behavior


(V)I

(b) short channel

0.0 0.6 0.7 0.8 0.9 1.0 1.1 1.2 1.3 1.4 1.5

Effective factor modulation

β ( )

(non-saturated)

surface zener potential modulation

dsVds

Vd sat,

( =0.7V)Vds

d satV, Vds( =1.5V)

Γ ( )>1Vds

I ds

Vds(V)

zV dsV( =1.5V)

Vz( =0.7V)Vds

Vds

Load line analysis after Ids saturation


Nano device physical limits — SDE(Source /Drain Extension) tunneling leakage


V S=0 V D=Vdd

V G=0

V SUB=0

channel leak

junction leak

gate leak

The electron leakage paths of an off state NMOS device

The whole leakage paths in an NMOS device when operated in off state. This condition likes the NMOS transistor of an inverter circuit at Vin=VLOW.

The leakage paths include SDE direct tunneling leak 、 junction leak and channel leak (Note: Ichannel

and Ijunction are too small that can

be neglected).


Vdd

V in Vout

"H""L"OFF

ON

Vdd

V in Vout

"H" "L"

OFF

ON

The concerned gate direct leakage components in an inverter circuit when operated in both “Logic-High” and “Logic-Low”. (Here channel leak Ichannel and junction leak Ijunction are neg

lected in this situation.)


VS=0V VD=0V

VG=Vdd

Case3. VSUB =0

Case 1.

IDIS ISUB

Case 2.

P-Substrate

N N

LovLov

The various leakage components Is/Id/Isub of an NMOS

device operand which can be determined as the voltage is biased at gate to source/drain/substrate.


(a) NMOS (b) PMOS

The practical measured I-V curves of IS/D and Isub tunneling

leak in (a) NMOS and (b) PMOS. The device size is W/L=50/0.5(μm) and gate oxide thickness, dox=2.3nm.

0.0 0.5 1.0 1.5 2.0 2.5 3.01E-14

1E-13

1E-12

1E-11

1E-10

1E-9

1E-8

S/D/B:Gnd

I S/D(I

SUB)

VGD

/VGB

IS¡ÜI

D

ISUB

-3.0 -2.5 -2.0 -1.5 -1.0 -0.5 0.01E-14

1E-13

1E-12

1E-11

1E-10

1E-9

1E-8

S/D/B:Gnd

I S/D (

ISU

B)

VGD

/VGB

IS¡ÜI

D

ISUB


(a) NMOS (b) PMOS

The measured SDE tunneling leakage current increases with a

longer Lov length in both n and p-MOS.

1.35 1.40 1.45 1.50 1.55 1.60 1.65

1E-11 S/D/B:Gnd

I S/D (

NM

OS

)

VGS

/VGD

W/O oxide spacer ,Lov=0.0291um oxide spacer width=200A,Lov=0.0176um oxide spacer width=300A,Lov=0.0135um

-1.65 -1.60 -1.55 -1.50 -1.45 -1.40 -1.35

1E-12

I S/D (

PM

OS

)

VGS

/VGD

W/O oxide spacer ,Lov=0.0628um oxide spacer width=200A,Lov=0.0436um oxide spacer width=300A,Lov=0.0365um

PS:Lov is determined using C-R method


(a) NMOS (b) PMOS

The gate direct tunneling leakage currents of gate to SDE overlap region and to substrate.

0.0 0.5 1.0 1.5 2.0 2.5 3.0

1E-15

1E-14

1E-13

1E-12

1E-11

1E-10

J S/D(J

SUB)

curr

ent d

ensi

ty

VGS

/VGD

/VGB

JS/D

per unit gate width (1/£gm)

JSUB

per unit channel area (1/£gm2)

-3.0 -2.5 -2.0 -1.5 -1.0 -0.5 0.0

1E-15

1E-14

1E-13

1E-12

1E-11

1E-10

J S/D(J

SUB)

curr

ent d

ensi

tyV

GS/V

GD/V

GB

JS/D

per unit gate width (1/£gm )

JSUB

per unit channel area(1/£gm2)


(a) NMOS (b) PMOS

The measured SDE tunneling leakage current increases with a higher SDE impurity concentration in both n and p-MOS.

1.35 1.40 1.45 1.50 1.55 1.60 1.65

1E-7

I S/D

VGS

/VGD

NMOS SDE concentration=2.5E15cm-3

NMOS SDE concentration=2.0E15cm-3

-1.65 -1.60 -1.55 -1.50 -1.45 -1.40 -1.35

1E-7

1E-6

1E-5

I S/D

VGS

/VGD

PMOS SDE concentration=2.5E15cm-3




A set of various gate direct leakage currents in an inverter circuit operated in both Vin=Vhigh and Vin=Vlow.

-3.0 -2.5 -2.0 -1.5 -1.0 -0.5 0.0

1E-15

1E-14

1E-13

1E-12

1E-11

1E-10

1E-9

J S/D_J

SUB c

urre

nt d

ensi

tyV

GS/V

GD/V

GB

JS/D

_PMOS(1/£gm)

JSUB

_PMOS(1/£gm2) J

D _NMOS(1/£gm)

0.0 0.5 1.0 1.5 2.0 2.5 3.0

1E-15

1E-14

1E-13

1E-12

1E-11

1E-10

J S/D

_JSU

B c

urre

nt d

ensi

ty

VGS

/VGD

/VGB

JS/D

_NMOS (1/£gm )

JSUB

_NMOS (1/£gm2) J

D _PMOS (1/£gm )

dox=23nm


(a) (b)

(a)The variation of the JS/D leakage current density of NMOS in an inverter when operated at Vin=Vhigh with different gate oxide thickness.

(b)As the same condition of PMOS when operated at Vin=Vlow.

1.0 1.1 1.2 1.3 1.4 1.5

1E-14

1E-13

1E-12

1E-11

1E-10

1E-9

J S/D

(1

/£g

m)

VGS

/VGD

2.1nm_NMOS 2.3nm_NMOS 2.6nm_NMOS

-1.5 -1.4 -1.3 -1.2 -1.1 -1.0

1E-16

1E-15

1E-14

1E-13

1E-12

1E-11

1E-10

1E-9

1E-8

1E-7

J S/D

(1/

£gm

)

VGS

/VGD

2.1nm_PMOS 2.3nm_PMOS 2.5nm_PMOS


Nano silicon device measurement

The C-R method


The Relationship of various length

Lj Lmet

Leff

1/2Lpb Lgate

N+ N+N-N-

Lovlap

LmaskLeff = Lmask - ΔLΔL = 2Lovlap + Lpb

Leff is the effective channel lengthLpb is the length of process biasLmet is the metallurgical channel length


Extraction of Leff

• I-V method

S&R(Shift and Ratio) Method

• C-V method

Decoupled C-V Method

• C-R Method

Capacitance Ratio Method


The Comparison of C-R and S&R Method

I-V method:Ids~μeffCoxW /Leff(Vg-Vth) Vds Leff △L

C-R method: without 2D effect & Rsd effect

2D effect

Lpb,Lovlap △L Leff

Rsd effect

(Here‚Lovlap Lpb Leff all are useful parameters)


S&R Method

Ids0= µeffCoxW(Vg-Vtho)Vds/Leff0

~Vds/Rchannel0

Idsi = µeffCoxW(Vg-Vthi )Vds/Leffi

~Vds/Rchanneli

S0(Vg) = dRchanne0/dVg

=Leff0 df(Vg-Vth0)/dVg

Si(Vg) = dRchannei/dVg

=Leffi df(Vg-Vthi)/dVg

f(Vg-Vth0)=1/(µeffCoxW(Vg-Vth0))

f(Vg-Vthi)=1/(µeffCoxW(Vg-Vthi))


S&R Method

r(δ,Vg)= S0(Vg)/ Si(Vg- δ)


2000


.

.

00

min

0min

LL

LL

L

Lr

VV

imask

maskieff

eff

ionon

S&R Method


2000

PS:The extracted △ L result is not constant -function of (L^ mask)


Decoupled C-V Method

Cgc = CoxWLcap

Ctot = Cgc+2Cov= CoxWLcap +2Cov(F)Cgc is the intrinsic gate-to-channel capacitanceLcap is the capacitively defined

channel length


1994


C-R Method(High Frequency Measurement Structure)

Vgs

G

S

D

B

以 NMOS為例

-3 -2 -1 0 1 2 3-20

0

20

40

60

80

100

120

Vg

Caccumulation

Cinversion

Cinversion

Cinversion

Coffset

+Cfringing

2Covlap

Lmask

=0.13um

Lmask

=0.5um

Lmask

=1um

Cgate

C(

fF/u

m )

(V) Source: JJAP 2001


The Calculation Method for Θ’ , Θ” and Θ

-3.0 -1.5 0.0 1.5 3.00.0

0.3

(Without RC delay effect)

Strong accumulation

(a) Extraction of Cox

(Vg¡ÜV

flatband=0V)

(With Shielding Effect)

Strong Inversion

Cgate,flatband

=0.295

Covlap,flatband

=0.0325

Cox

(P

f)

VG



-3.0 -1.5 0.0 1.5 3.00

1

2£c=£c //£c // = 0.96

(£c /¡Ü£c1¡Ü L

ovlap/L

j )

(b) The calculation of £c /,£c // and £c

£c /=0.93

£c //=0.97

Cox

/Cox

(Vg¡

ÜV

flat

band

)

Vg

Process condition:


N¢wdose = 2E15 , Arsenic


Θ(Vg)= Covlap,depletion (Vg=-Vcc)/ Covlap,accumulation (Vg>Vt)Θ= Covlap,depletion (Vg=-Vcc)/ Covlap,accumulation (Vg=+Vcc)Θ=(Covlap (Vg=-Vcc)*Lgate)/ (Cgate (Vg=+Vcc)*2Lovlap) = Θ’/ Θ” Here, Θ is the net compensation factor

Θ’ (Vg)= Covlap,depletion (Vg =-Vcc)/Covlap,flatband is S/D extension depletion compensation factor

Θ”(Vg)= Cgate,depletion (Vg =Vcc)/Cgate,flatband is the poly depletion compensation factor

Θ(Vg>Vt)=Θ’/ Θ” (Vg>Vt) Θ≒ ’ Θ≒For a highly doped poly gate(NMOS)

The Definition of Θ’ , Θ” and Θ


Lpb (poly gate process bias) and Lovlap (S/D overlap bias) Extraction (C-R method)

Region 1:(accumulation)Cacc=CovlapW+CfriW+Coffset

Region 2:(inversion)Cinv=CgWLg+CfriW+Coffset

-3 -2 -1 0 1 2 30

20

40

60

80

100

120C

inversion

Caccumulation

Coffset

+Cfringing

2Covlap

Cgate

C(f

F)

Vg(V)

C if

Covlap

CfriCfri

Covlap

C if


C-R method－ Lovlap extraction

effox

gateoxfri d

dC

,

1ln2

friaccacc

ovlap

accaccoffset

CWW

CCC

WW

CWCWC

21

21

12

2112

2

Lovlap (um)extraction

offsetfriovlapacc

offsetfriovlapacc

CWCWCC

CWCWCC

222

111

or2222

1111

lCACC

lCACC

friareameasure

friareameasure

)/(

)/(2umFC

umFCL

ox

ovlapovlap

(2)

(1)

(3)


C-R method － Lpb

extractionLpb(um) extraction

11

2121

11

21

1

21

1

gmaskpb

maskmaskinvinv

offsetfriinvg

invinv

offsetfriinv

maskmask

g

LLL

LLCC

CWCCL

CC

CWCC

LL

L

offsetfrigginv CWCWLCC 11

offsetfrigginv CWCWLCC 22

Assume the Lpb is the same on this two long channel devices in the same wafer

2121)2()1( ggginvinv LLWCCC

(1)

(2)

(3)


0.0 0.2 0.4 0.6 0.8 1.0 9 10 11

0.0

0.2

0.4

0.6

0.8

1.0

91011

Lpb

2Lovlap

L

Lmask

(um)

Lef

f(um

)

0.008

0.012

0.016

0.020

0.024

0.028

0.032

0.036

0.040

Δ

Δ

Lovlap ,L

pb , L(um

)

The within wafer 5 points data of Lpb, Lovlap, △L and

Leff using the suggested C-R method


Extractions of Cgd and Rsd for RF CMOS Application

Cgd (Vg < 0V) = Covlap,accumulation (Vg < 0V) + Cfringing (Vg < 0V)

= [Caccumulation (Vg= -Vcc) - (Coffset/W)] θ’(Vg < 0V) / 2θ’

≒ [Cmeasured(Vg < 0V) - (Coffset/W)] (pF/um)

Cgd0 = Cgd (Vg≒0V) +Cif

≒ [Cmeasured(Vg = 0V) - (Coffset/w)] / 2 (pF/um)

Ids = (Vds * W)/ (Rchannel + Rsd) = Vds / Rtotal (A)

γ = Leff1 / Leff2 = Rchannel1 / Rchannel2

Rsd = (Rtotal2 * Leff1 – Rtotal1 * Leff2) / (Leff1 - Leff2) (Ω-um)


The C-R method be used to verified ISE TCAD 2-D

Simulation results


Pictures (a), (b) and (c) show the Lj values and halo impurity distributions of devices with different halo tilt angles using ISE

TCAD 2-D simulation tool

(a) halo tilt angle=0∘




(b) halo tilt angle=20∘




(c) halo tilt angle=30∘


0.00 0.02 0.04 0.06 0.08 0.10

1E16

1E17

1E18

1E19

1E20

Bornor surface concentration w/o halo implant

Boron surface concentration with different halo condition

Arsenic surface concentration

(d)Tilt angle=30o(c)Tilt angle=20o

(b)Tilt angle=10o

(a) N -

surf

ace

imp

uri

ty c

on

cen

tra

tion

(A

tom

s/cm

3 )

Distance to poly gate edge in L-direction(um)

Different tilt angles of halo implant make almost the same Lj values but different surface halo impurity distributions

surf

ace

impu

rity

co

ncen

trat

ion

3


0.05 0.10 0.15 0.20 1

0.05

0.10

0.15

0.20

0.25

0.30

0.35

0.40

0.45

0.50

Poor short channel effect

Reverse short channel effect

0.50

Vt(

Vol

t)

Lmask(um)

without halo implant

halo tilted angle 0o

10o

20o

30o

The short channel Vt rolling-off curves of devices with

different halo conditions Reverse short channel effect


This figure shows the extracted ΔL values of devices with different halo conditions using the C-R or S&R method.

0.0 0.1 0.2 0.3 0.4 0.5 1.0

-0.02

0.00

0.02

0.04

0.06

0.08

£G

j pbL =simulated 2L + extracted L (tilted 30 o)

j pb

£GL

pb

pb

mask

(w/o halo)

met

met

(tilted 300)the S&R method

£G

£Gthe S&R method

(tilted 300)

(without halo implant)

(£g¢õ)

(£g¢

õ)

£G

£G

Extracted L using the C-R method

Extracted L using

Extracted L using

L =simulated 2L + extracted L (without halo implant)



L

without halo(S&R)

tilted 30o

without halo(C-R)

tilted 30o

PS:The verification of nano- device simulation results will be difficult,the C-R method can help that.


ConclusionsConclusions

Silicon Technology should be the main stream for future nano device

application

– SOC, IC Based MEMS, Silicon photo logic…etc. R/D of new materials are necessary for overcoming physical limits

– Gate Engineering(gate material, dielectric material)

– S/D Engineering (S/D extension material, doping technology)

New challenges on nano device measurement and physics studies – 2D Effect / Inconstant unit channel conductance model (C-R method)

– Bipolar effect / MSJZ model (C-R method and ?)

. Semiconductor Research Group National Taipei University of Technology 1...

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