3

3

1.1.1 4

1.1.2 4

4

1.2.1 4

1.2.1 5

5

5

3.1.1 5

3.2.2 6

9

2.2.1 9

2.2.2 10

11

3.3.1 11

3.3.2 12

3.3.3 12

3.3.4 12

3.3.5 12

3.3.6 13

EMC13

CAD14

19

3.2.1 FPGA19

3.2.2 FPGA22

3.2.3 EPLD23

3.2.4 MAX + PLUS II26

3.2.5 VHDL33

42

3.3.1 42

3.3.2 43

3.3.3 44

3.3.4 RS23244

3.3.5 RS422RS42345

3.3.6 RS48545

3.3.7 20mA47

48

3.4.1 48

3.4.2 48

3.4.3 49

3.4.4 ID49

3.4.5 50

3.4.6 51

3.4.7 51

3.4.8 Watchdog52

3.4.9 53

54

3.5.1 TTLECLPECLCMOS54

3.5.2 TTLECLMOS66

67

3.6.1 67

3.6.2 70

3.6.3 76

3.6.4 79

81

3.7.1 CPU81

3.7.2 82

3.7.3 82

3.7.4 82

88

3.8.1 88

3.8.2 91

95

3.9.1 95

3.9.2 102

DSP108

3.10.1 DSP108

3.10.2 DSP109

3.10.3 TMS320 C54X DSP110

3.10.4 TMS320C54X114

120

120

4.1.1 ISO120

4.1.2 CCITTITU-T121

4.1.3 IEEE121

4.1.4 ETSI121

4.1.5 ANSI122

4.1.6 TIA/EIA122

4.1.7 Bellcore122

122

4.2.1 ISO122

4.2.2 CCITT G123

4.2.3 I125

4.2.4 V125

4.2.5 TIA/EIA 128

4.2.5 CCITT X130

132

132

132

IC134

137

141

144

145

MRPIIBOM146

1.1.1

CPUI/OPCBPCB12PCB

1.1.2

ID.WDT

1.2.1

1

2

3

4

5

1.2.1

EPLDFPGA

IDWDT

3.1.1

PCB

4/QM-RSD009199721

3.2.2

MBC

CADEMICADCAD

PCB

PCB

CADPCB

PCBPCBCADPCBPCBCADPCBPCBPCBPCBCAD

2.2.1

HUAWEIISO9000rndI

2.2.2

1

2

3

4

5

6

PCBPCBPCB

7

8

9

I/O

10

PCB

3.3.1

3.3.2

3.3.3

XXXX

3.3.4

3.3.5

3.3.6

EMC

EMC

EMC

EMCEMC

1

2

3

4

CAD

15MHz5nsPCB

2

3

VN1I2ZGI2ZG1

4

5PCBEMCZ

CL0

Z0L/C377(d/w) (r/r) < 0.1

1

2

3 PCB

4

1

251

3

4I/O

5

6

7

8

1 >

SE(dB)R(dB)A(dB)

21MHz()1MHzDC/DC

3()

4()

5

6UNjwB.A.cosojwM.I1(A2BMI1BACOS0MI1

7 < min/2070

1300KHz50KHz10MHz< 0.05< 0.05

2

3

4L < 0.15L 1MHz

3

4(1-100nF)DC/DC(uF)

CminIt/Vmax Vmax2

EMC

EMCEMCEMC

3.2.1 FPGA

FPGA

FPGAField Programmable Gate ArrayASICFPGAXilinx

EPLDErasable Programmable Logic Devices)FPGA

1EPLDFPGA

EPLDMacrocellFPGAEPLD

2FPGA

3FPGA

FPGAFPGAPQFPTQFPBGAEPLDPLCC

4EPLDEPROM-baseFPGASRAM-base

5EPLDFPGA

FPGA

1FPGA

CLB:Configurable Logic Block

IOB:Input/Output Block

PIC:Programmable Interconnect

SRAM

2FPGA

1FPGALCALogic Cell Array

FPGACLBLCACLBLCALCA

2FPGASRAM

FPGASRAMCLBIOBPICLCASRAM

3FPGA

1FPGA

FPGA

A

LCAPROMEPROM

FPGALCALCALCA

PROMLCA

FPGAFPGAFPGAFPGA

B

FPGAFPGAFPGA

C

FPGA

2FPGA

FPGAFPGAFPGASRAM

FPGAM0M1M2LCAFPGALCASRAMLCALCALCADOUTFPGAI/O

3.2.2 FPGA

1 FPGA

PCXILINX FPGAViewlogicXACTstep6.0.1ALDECFoundation SeriesXACTstep

Design Entry

Prosim Prowave

XACTstep

Prosim Prowave

Download

Design EntryProsimProwaveXACTstepXILINX FPGALCABITFPGAProsimProwave

FPGA

XILINX FPGAXC3000XC4000

Device

Gates

CLBs

IOBs

Flip-Flops

XC3120

1000-1500

64

64

256

XC3130

1500-2000

100

80

360

XC3142

2000-3000

144

96

480

XC3164

3500-4000

224

120

688

XC3190

5000-6000

320

144

928

XC3195

6500-7500

484

176

1320

XC3000

Device

Gates

CLBs

IOBs

Flip-Flops

XC4002A

2000

64

64

256

XC4003A

3000

100

80

360

XC4003/H

3000

100

80/160

360/300

XC4004A

4000

144

96

480

XC4005A

5000

196

112

616

XC4005/H

5000

196

112/192

616/392

XC4006

6000

256

128

768

XC4008

8000

324

144

936

XC4010/D

10000

400

160

1120

XC4013/D

13000

576

192

1536

XC4020

20000

784

224

2016

XC4025

25000

1024

256

2560

3.2.3 EPLD

1

PLDPLDICTTLPLDASICPLDPLD

2ALTERAPLD

ALTERA7PLDFLEX 10KFLEX8000MAX9000MAX7000FLASHLogicMAX5000ClassicFlexible Logic Element MatrixFLEXMultiple Array MatrixMAXFLASHlogicClassic

ALTERA

FLEX 10K

SRAM

FLEX 8000

SRAM

MAX9000

EEPROM

MAX7000

EEPROM

FLASHLogic

RAM&FLASH

MAX5000

EPROM

Classic

EPROM

ALTERAPLD

1Classic

ClassicALTERA90068Classic0EPROM

2MAX5000

MAX5000ALTERAMAX300380020100ALTERAMAX5000ASICEPROMMAX5000

3MAX7000

MAX7000ALTERA 60050003225636164I/O5 ns16178.9MHZ/I/O EEPROMMAX7000

MAX7000EMAX 7000MAX7000SMAX7000EJTAG BSTISP

4MAX9000

MAX9000 MAX 7000FLEXEEPROMMAX9000600012000320560216I/OJTAG BSTISPPLDISP

5FLASHlogic

FLASH LogicRAMICRISPJTAG BSTFLASH LogicSRAMFLASH160032008016062120I/O

10ns

6FLEX 8000

FLEX 8000I/O2,50016,000282150078208I/OFLEX 8000SRAMFLEX 8000ICRPC

FLEX 10K

FLEX 10KPLDSPLD100,000 FLEX10KEAB

ALTERACMOS

EPLD

3.3V

3. 3V5.0V

I/O PIN

PLL

PCI

Compliance

ISP

ICR

JTAG

SRAM

FLEX10K

(

(

(

(

(

(

(

(

(

FLEX8000

(

(

(

(

(

(

MAX9000

(

(

(

(

(

MAX7000

MAX7000S

(

(

(

(

(

(

(

(

(

(

(

(

FLASH

logic

(

(

(

(

(

(

(

(

MAX5000

Classic

3.2.4 MAX + PLUS II

1

AlteraMAXPLUS

MAXPLUSMAXPLUS

MAXPLUSCompilerMAXPLUSAlteraClassicMAX5000MAX7000MAX 9000FLASHlogicFLEX 8000FLEX 10K

MAXPLUS486PCMicrosoft WindowsWindows NTSun SPARCHP9000700DEC Alpha AXPX windows

MAXPLUS

3.2.4MAXPLUS

HDLMAXPLUS HDLVHDLVerilog HDLAlteraAHDL

AlteraCAEMAXPLUSCAEEDIF 200209LPMVerilogVHDLAlteraCAEMAXPLUS CompilerAlteraAlteraCAEMAXPLUSSynopsysViewlogicMentor GraphicsCadenceExemplarDate I/OIntergraphMincOrCAD

MAXPLUS

2

MAXPLUSMAXPLUSCAEMAXPLUSMAXPLUSProject

2.1

3.2.4.1 MAXPLUSGraphic Editordrag-and -dropPrimitive74300

3.2.4.1

2.2

MAXPLUSText EditorVHDLVerilog HDLAHDLAlteraHDLMAXPLUSCompilerAltera

HDL

2.3

MAXPLUSWaveform Editor

CompilerCompiler

2.4

MAXPLUSFloorplan Editor3.2.4.2

3.2.4.2

2.5CAE

MAXPLUS CompilerEDIF200290CAECompiler.lmfCAEMAXPLUSAltera74100LMFCadenceMentor GraphicsMincOrCADViewlogicCadenceExemplarIntergraphMentor GraphicsRacal-RedacSynopsysViewlogicVHDLVeilog

MAXPLUSLPMLibrary of parameteride modulesLPMCAE MAXPLUS CompilerEDIFLPMMAXPLUSLPM

MAXPLUSOrCAD.schXilinx.xnf,Altera

2.6

HDLEDIFMAXPLUSMAXPLUS

3

MAXPLUSCompilerTiming AnalyzeMessage Processor

3.1

MAXPLUSMessage Processor MAXPLUS3.2.4.3

3.2.4.3

3.2

MAXPLUSCompilerLogic SynthesizerWYSIWYGwhat-yuo-see-what-you-ger

Altera

Compiler FitterFitterReport File.rpf

3.3

CompilertpDTCOTSUFMAXFitter

3.4

MAXPLUSCompilerDesign Doctor

3.5

CompilerPartitionerFitter

3.6

MAXPLUSCompiler

EDIF

EDIF200290

Verilog

VerilogXLVerilog

VHDL

VHDLVHDL

3.7

Assembler.pofSRAM.sof/JEDEC.jedMAXPLUSAlteraMAXPLUSIntel.hexTab-ular.ttfFLEX8000Bit.sbf

4

AlteraCAE

4.1

MAXPLUS

MAXPLUS

Message ProcessorWaveform Editor

1

MAXPLUSSimulatorMAXPLUS

2

MAXPLUS0.1ns

3

MAXPLUSAltera/Altera

4.2

MAXPLUSTiming AnalyzerMAXPLUSTiming Analyzer Message ProcessorTiming Analyzer

5

3.2.4.4 MAXPLUSProgrammerCompilerAlteraPCATAlteraMPUMaster Programmer UnitMPUMPU

AlteraFLEXFLEX8000BitBlasterFLEX8000MPUEPROMFLEX8000BitBlasterRS232FLEX8000BitBlasterPCFLEX8000MAXPLUS

Altera

3.2.4.4

6

MAXPLUSMAXPLUSAlteraAHDLAltera

F1shift+F1AHDL

7

MAXPLUSAltera

7.1PC

486PentiumPCAT

16RAM

DOS5.0

Microsoft Windows3.1

Micosoft Windows

1.443

CDROM

Microsoft Windows3.1

8ISA

7.2Sun

Sun SPARC

32RAM

Sun OS4.1.2Solaris 1.0

Sun Open Windows 3.0Solaris 1.0

ISO9660CDROM

7.3HP

HP Series700

32RAM

HPUX 9.03

Hp-VUE

ISO9660CDROM

7.4DEC Alpha AXP

DEC Alpha APX

32RAM

OSF/1 1.3

Motif 1.2

ISO 9660CDROM

3.2.5 VHDL

VHDL

VHDLVHSIC Hardware Description Language7080VHSICVery High Speed Integrated CircuitVHDL1981VHSIC198712VHDLIEEE1076VHDLVHDL

VHDL

VHDLVHDLVHDL

1entity

VHDLVHDLVHDL

ENTITY mux2 IS

PORT(i0:IN std_logic;

i1:IN std_logic;

cnt:IN std_logic;

y:OUT std_logic);

END mux2;

VHDLmux2i0i1mux2cntyINOUTstd_logicVHDLVHDLVHDL

2architecture

1)

mux2

ARCHITECTURE mux2_behav OF mux2 IS

BEGIN

yi1,o=>temp1);

U2:and2

PORT MAP(i0=>i0,i1=>temp0,o=>temp2);

U3:or2

PORT MAP(i0=>temp1,i1=>temp2,o=>y);

END mux2_arch;

mux2_archmux2ARCHITECTUREBEGINtemp0-temp3std_logicand2or2mux2and2or2i1i2ostd_logicBEGINENDmux2

3configuration

CONFIGURATION mux2_config OF mux2 IS

FOR mux2_behav

END FOR;

END mux2_config;

mux2mux2_behavmux2_config

4attribute

VHDLVHDLFPGApin number

5process

VHDLVHDL

VHDL

1

mux2_arch

U1:and2 PORT MAP(i0=>cnt,i1=>i1,o=>temp);

and2i0i1oU1cnti0i1i1tempo

2

mux2_archBEGINENDCPASCAL

abcdee=ab+c/dVHDLVHDLVHDL

-- This is an example of combinational logic;

-- Version 1.0 , 20/5/1997;

LIBRARY ieee;

USE ieee.std_logic_1164.ALL;

ENTITY comb_test0 IS

PORT(a:IN std_logic;

b:IN std_logic;

c:IN std_logic;

d:IN std_logic;

e:OUT std_logic);

END comb_test0;

ARCHITECTURE comb_test0_behav OF comb_test0 IS

SIGNAL temp0:std_logic;

SIGNAL temp1:std_logic;

SIGNAL temp2:std_logic;

BEGIN

temp0