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Pentium® Processor FamilyDeveloper’s Manual

Volume 3:Architecture and Programming Manual

NOTE: The Pentium® Processor Family Developer’s Manual consistsof three books: Pentium® Processor Order Number 241428; the

82496/82497/82498 Cache Controller and 82491/82492/82493 CacheSRAM, Order Number 241429; and the Architecture and

Programming Manual, Order Number 241430. Please refer to all three volumes when evaluating your design needs.

1995

PATENT NOTICE

Through its investment in computer technology, Intel Corporation (Intel) has acquired numerous proprietary rights, includingpatents issued by the U.S. Patent and Trademark Office. Intel has patents covering the use or implementation of processorsin combination with other products, e.g., certain computer systems. System and method patents or pending patents, of Inteland others, may apply to these systems. A separate license may be required for their use (see Intel Terms and Conditionsfor details). Specific Intel patents include U.S. patent 4,972,338.

Information in this document is provided solely to enable use of Intel products. Intel assumes no liability whatsoever,including infringement of any patent or copyright, for sale and use of Intel products except as provided in Intel’s Terms andConditions of Sale for such products.

Intel Corporation makes no warranty for the use of its products and assumes no responsibility for any errors which mayappear in this document nor does it make a commitment to update the information contained herein.

Intel retains the right to make changes to these specifications at any time, without notice.

Contact your local Intel sales office or your distributor to obtain the latest specifications before placing your product order.

MDS is an ordering code only and is not used as a product name or trademark of Intel Corporation.

Intel Corporation and Intel's FASTPATH are not affiliated with Kinetics, a division of Excelan, Inc. or its FASTPATH trade-mark or products.

*Other brands and names are the property of their respective owners.

† Since publication of documents referenced in this document, registration of the Pentium, OverDrive and iCOMPtrademarks has been issued to Intel Corporation.

Additional copies of this document or other Intel literature may be obtained from:

Intel CorporationLiterature SalesP.O. Box 7641Mt. Prospect, IL 60056-7641

or call 1-800-879-4683

© INTEL CORPORATION 1995

EETABLE OF CONTENTS

CHAPTER 1GETTING STARTED PAGE1.1. HOW TO USE THIS MANUAL................................................................................. 1-11.1.1. Part I—Application and Numeric Programming..................................................... 1-21.1.2. Part II—System Programming ............................................................................. 1-21.1.3. Part III—Compatibility .......................................................................................... 1-41.1.4. Part IV—Optimization .......................................................................................... 1-41.1.5. Part V—Instruction Set ........................................................................................ 1-41.1.6. Appendices.......................................................................................................... 1-51.2. RELATED LITERATURE ......................................................................................... 1-51.3. NOTATIONAL CONVENTIONS............................................................................... 1-51.3.1. Bit and Byte Order............................................................................................... 1-61.3.2. Undefined Bits and Software Compatibility........................................................... 1-61.3.3. Instruction Operands ........................................................................................... 1-71.3.4. Hexadecimal Numbers......................................................................................... 1-71.3.5. Segmented Addressing........................................................................................ 1-81.3.6. Exceptions........................................................................................................... 1-8

CHAPTER 2INTRODUCTION TO THE INTEL PENTIUM® PROCESSOR FAMILY

PART I — APPLICATION ANDNUMERIC PROGRAMMING

CHAPTER 3BASIC PROGRAMMING MODEL3.1. MEMORY ORGANIZATION .................................................................................... 3-13.1.1. Unsegmented or "Flat" Model .............................................................................. 3-23.1.2. Segmented Model ............................................................................................... 3-33.2. DATA TYPES.......................................................................................................... 3-43.3. REGISTERS ........................................................................................................... 3-83.3.1. General Registers................................................................................................ 3-83.3.2. Segment Registers .............................................................................................3-103.3.3. Stack Implementation .........................................................................................3-123.3.4. Flags Register ....................................................................................................3-133.3.4.1. STATUS FLAGS.............................................................................................3-143.3.4.2. CONTROL FLAG............................................................................................3-153.3.5. Instruction Pointer...............................................................................................3-153.4. INSTRUCTION FORMAT .......................................................................................3-15

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3.5. OPERAND SELECTION.........................................................................................3-173.5.1. Immediate Operands ..........................................................................................3-183.5.2. Register Operands .............................................................................................3-193.5.3. Memory Operands..............................................................................................3-193.5.3.1. SEGMENT SELECTION .................................................................................3-203.5.3.2. EFFECTIVE-ADDRESS COMPUTATION........................................................3-203.6. INTERRUPTS AND EXCEPTIONS .........................................................................3-23

CHAPTER 4APPLICATION PROGRAMMING4.1. DATA MOVEMENT INSTRUCTIONS....................................................................... 4-14.1.1. General-Purpose Data Movement Instructions ..................................................... 4-14.1.2. Stack Manipulation Instructions............................................................................ 4-24.1.3. Type Conversion Instructions............................................................................... 4-54.2. BINARY ARITHMETIC INSTRUCTIONS.................................................................. 4-64.2.1. Addition and Subtraction Instructions ................................................................... 4-74.2.2. Comparison and Sign Change Instruction ............................................................ 4-84.2.3. Multiplication Instructions..................................................................................... 4-84.2.4. Division Instructions............................................................................................. 4-94.3. DECIMAL ARITHMETIC INSTRUCTIONS ..............................................................4-104.3.1. Packed BCD Adjustment Instructions..................................................................4-104.3.2. Unpacked BCD Adjustment Instructions..............................................................4-104.4. LOGICAL INSTRUCTIONS.....................................................................................4-114.4.1. Boolean Operation Instructions ...........................................................................4-114.4.2. Bit Test and Modify Instructions ..........................................................................4-124.4.3. Bit Scan Instructions...........................................................................................4-124.4.4. Shift and Rotate Instructions...............................................................................4-134.4.4.1. SHIFT INSTRUCTIONS..................................................................................4-134.4.4.2. DOUBLE-SHIFT INSTRUCTIONS...................................................................4-164.4.4.3. ROTATE INSTRUCTIONS..............................................................................4-174.4.4.4. FAST "bit blt" USING DOUBLE-SHIFT INSTRUCTIONS..................................4-194.4.4.5. FAST BIT STRING INSERT AND EXTRACT...................................................4-194.4.5. Byte-Set-On-Condition Instructions.....................................................................4-234.4.6. Test Instruction...................................................................................................4-234.5. CONTROL TRANSFER INSTRUCTIONS ...............................................................4-234.5.1. Unconditional Transfer Instructions .....................................................................4-234.5.1.1. JUMP INSTRUCTION.....................................................................................4-244.5.1.2. CALL INSTRUCTIONS ...................................................................................4-244.5.1.3. RETURN AND RETURN-FROM-INTERRUPT INSTRUCTIONS ......................4-244.5.2. Conditional Transfer Instructions.........................................................................4-254.5.2.1. CONDITIONAL JUMP INSTRUCTIONS..........................................................4-254.5.2.2. LOOP INSTRUCTIONS ..................................................................................4-264.5.2.3. EXECUTING A LOOP OR REPEAT ZERO TIMES..........................................4-274.5.3. Software Interrupts .............................................................................................4-274.6. STRING OPERATIONS..........................................................................................4-284.6.1. Repeat Prefixes..................................................................................................4-294.6.2. Indexing and Direction Flag Control ....................................................................4-304.6.3. String Instructions...............................................................................................4-304.7. INSTRUCTIONS FOR BLOCK-STRUCTURED LANGUAGES.................................4-314.8. FLAG CONTROL INSTRUCTIONS.........................................................................4-384.8.1. Carry and Direction Flag Control Instructions ......................................................4-384.8.2. Flag Transfer Instructions ...................................................................................4-38

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4.9. NUMERIC INSTRUCTIONS....................................................................................4-404.10. SEGMENT REGISTER INSTRUCTIONS................................................................4-404.10.1. Segment-Register Transfer Instructions..............................................................4-414.10.2. Far Control Transfer Instructions.........................................................................4-414.10.3. Data Pointer Instructions.....................................................................................4-414.11. MISCELLANEOUS INSTRUCTIONS ......................................................................4-424.11.1. Address Calculation Instruction...........................................................................4-434.11.2. No-Operation Instruction.....................................................................................4-434.11.3. Translate Instruction ...........................................................................................4-434.11.4. Byte Swap Instruction .........................................................................................4-434.11.5. Exchange-and-Add Instruction............................................................................4-454.11.6. Compare-and-Exchange Instructions ..................................................................4-454.11.7. CPUID Instruction...............................................................................................4-46

CHAPTER 5FEATURE DETERMINATION5.1. CPU IDENTIFICATION............................................................................................ 5-15.2. FPU DETECTION.................................................................................................... 5-25.3. SAMPLE CPUID IDENTIFICATION/FPU DETECTION CODE.................................. 5-2

CHAPTER 6NUMERIC APPLICATIONS6.1. INTRODUCTION TO NUMERIC APPLICATIONS.................................................... 6-16.1.1. History................................................................................................................. 6-16.1.2. Performance........................................................................................................ 6-26.1.3. Ease of Use......................................................................................................... 6-26.1.4. Applications......................................................................................................... 6-46.1.5. Programming Interface ........................................................................................ 6-56.2. ARCHITECTURE OF THE FLOATING-POINT UNIT................................................ 6-76.2.1. Numerical Registers ............................................................................................ 6-76.2.1.1. THE FPU REGISTER STACK .......................................................................... 6-86.2.1.2. THE FPU STATUS WORD............................................................................... 6-96.2.1.3. CONTROL WORD..........................................................................................6-116.2.1.4. THE FPU TAG WORD ....................................................................................6-146.2.1.5. OPCODE FIELD OF LAST INSTRUCTION .....................................................6-156.2.1.6. THE NUMERIC INSTRUCTION AND DATA POINTERS..................................6-166.2.2. Computation Fundamentals ................................................................................6-196.2.2.1. NUMBER SYSTEM.........................................................................................6-196.2.2.2. DATA TYPES AND FORMATS .......................................................................6-216.2.2.2.1. Binary Integers............................................................................................6-216.2.2.2.2. Decimal Integers .........................................................................................6-216.2.2.2.3. Real Numbers.............................................................................................6-236.2.2.3. ROUNDING CONTROL ..................................................................................6-256.2.2.4. PRECISION CONTROL..................................................................................6-266.3. FLOATING-POINT INSTRUCTION SET.................................................................6-266.3.1. Source and Destination Operands ......................................................................6-276.3.2. Data Transfer Instructions...................................................................................6-276.3.3. Nontranscendental Instructions...........................................................................6-286.3.4. Comparison Instructions .....................................................................................6-306.3.5. Transcendental Instructions................................................................................6-316.3.6. Constant Instructions..........................................................................................6-33

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6.3.7. Control Instructions.............................................................................................6-336.4. NUMERIC APPLICATIONS ....................................................................................6-356.4.1. High-Level Languages ........................................................................................6-366.4.1.1. C PROGRAMS ...............................................................................................6-366.4.1.2. PL/M-386/486.................................................................................................6-366.4.1.3. ASM386/486...................................................................................................6-386.4.1.3.1. Defining Data ..............................................................................................6-386.4.1.3.2. Records and Structures...............................................................................6-406.4.1.3.3. Addressing Methods ...................................................................................6-416.4.1.4. COMPARATIVE PROGRAMMING EXAMPLE.................................................6-426.4.1.5. CONCURRENT PROCESSING.......................................................................6-476.4.1.6. MANAGING CONCURRENCY........................................................................6-476.4.1.7. EXCEPTION SYNCHRONIZATION.................................................................6-496.4.1.8. PROPER EXCEPTION SYNCHRONIZATION .................................................6-49

CHAPTER 7SPECIAL COMPUTATIONAL SITUATIONS7.1. SPECIAL NUMERIC VALUES ................................................................................. 7-17.1.1. Denormal Real Numbers...................................................................................... 7-77.1.2. Zeros................................................................................................................... 7-97.1.3. Infinity ................................................................................................................. 7-97.1.4. NaN (Not-a-Number) ..........................................................................................7-157.1.4.1. SIGNALING NaNs ..........................................................................................7-167.1.4.2. QUIET NaNs...................................................................................................7-167.1.5. Indefinite ............................................................................................................7-177.1.6. Encoding of Data Types......................................................................................7-187.1.6.1. UNSUPPORTED FORMATS...........................................................................7-187.1.7. Numeric Exceptions............................................................................................7-187.1.8. Handling Numeric Exceptions .............................................................................7-197.1.8.1. AUTOMATIC EXCEPTION HANDLING...........................................................7-197.1.8.2. SOFTWARE EXCEPTION HANDLING............................................................7-207.1.9. Invalid Operation ................................................................................................7-217.1.9.1. STACK EXCEPTION.......................................................................................7-227.1.9.2. INVALID ARITHMETIC OPERATION..............................................................7-227.1.10. Division by Zero..................................................................................................7-237.1.11. Denormal Operand .............................................................................................7-237.1.12. Numeric Overflow and Underflow........................................................................7-247.1.12.1. OVERFLOW...................................................................................................7-247.1.12.2. UNDERFLOW.................................................................................................7-267.1.13. Inexact (Precision)..............................................................................................7-277.1.14. Exception Priority................................................................................................7-287.1.15. Standard Underflow/Overflow Exception Handler ................................................7-28

EE CONTENTSCHAPTER 8NUMERIC PROGRAMMING EXAMPLES

PAGE8.1. CONDITIONAL BRANCHING EXAMPLE................................................................. 8-18.2. EXCEPTION HANDLING EXAMPLES ..................................................................... 8-48.3. FLOATING POINT TO ASCII CONVERSION EXAMPLES ....................................... 8-78.3.1. Function Partitioning ...........................................................................................8-228.3.2. Exception Considerations ...................................................................................8-228.3.3. Special Instructions.............................................................................................8-228.3.4. Description of Operation .....................................................................................8-238.3.5. Scaling the Value................................................................................................8-248.3.5.1. INACCURACY IN SCALING............................................................................8-248.3.5.2. AVOIDING UNDERFLOW AND OVERFLOW..................................................8-248.3.5.3. FINAL ADJUSTMENTS...................................................................................8-258.3.6. Output Format ....................................................................................................8-258.4. TRIGONOMETRIC CALCULATION EXAMPLES ....................................................8-25

PART II — SYSTEM PROGRAMMING

CHAPTER 9REAL-ADDRESS MODE SYSTEM ARCHITECTURE9.1. ADDRESS TRANSLATION...................................................................................... 9-19.2. REGISTERS AND INSTRUCTIONS......................................................................... 9-29.3. INTERRUPT AND EXCEPTION HANDLING............................................................ 9-39.4. REAL-ADDRESS MODE EXCEPTIONS .................................................................. 9-3

CHAPTER 10PROTECTED-MODE SYSTEM ARCHITECTURE OVERVIEW10.1. SYSTEM REGISTERS ...........................................................................................10-110.1.1. System Flags......................................................................................................10-210.1.2. Memory-Management Registers .........................................................................10-410.1.3. Control Registers................................................................................................10-510.1.4. Debug Registers.................................................................................................10-910.2. SYSTEM INSTRUCTIONS ...................................................................................10-11

CHAPTER 11PROTECTED-MODE MEMORY MANAGEMENT11.1. SELECTING A SEGMENTATION MODEL..............................................................11-211.1.1. Flat Model ..........................................................................................................11-311.1.2. Protected Flat Model...........................................................................................11-411.1.3. Multisegment Model............................................................................................11-511.2. SEGMENT TRANSLATION ....................................................................................11-611.2.1. Segment Registers .............................................................................................11-911.2.2. Segment Selectors ...........................................................................................11-1011.2.3. Segment Descriptors ........................................................................................11-1111.2.4. Segment Descriptor Tables...............................................................................11-1511.2.5. Descriptor Table Base Registers.......................................................................11-1611.3. PAGE TRANSLATION..........................................................................................11-1711.3.1. Paging Options.................................................................................................11-18

CONTENTS EEPAGE

11.3.3. Page Tables .....................................................................................................11-1911.3.4. Page-Table Entries ...........................................................................................11-1911.3.4.1. PAGE FRAME ADDRESS.............................................................................11-2011.3.4.2. PRESENT BIT ..............................................................................................11-2011.3.4.3. ACCESSED AND DIRTY BITS......................................................................11-2111.3.4.4. READ/WRITE AND USER/SUPERVISOR BITS ............................................11-2211.3.4.5. PAGE-LEVEL CACHE CONTROL BITS........................................................11-2211.3.5. Translation Lookaside Buffers...........................................................................11-2211.4. COMBINING SEGMENT AND PAGE TRANSLATION...........................................11-2311.4.1. Flat Model ........................................................................................................11-2311.4.2. Segments Spanning Several Pages ..................................................................11-2311.4.3. Pages Spanning Several Segments ..................................................................11-2311.4.4. Non-Aligned Page and Segment Boundaries.....................................................11-2411.4.5. Aligned Page and Segment Boundaries ............................................................11-2411.4.6. Page-Table Per Segment..................................................................................11-25

CHAPTER 12PROTECTION12.1. SEGMENT-LEVEL PROTECTION..........................................................................12-112.2. SEGMENT DESCRIPTORS AND PROTECTION....................................................12-212.2.1. Type Checking....................................................................................................12-212.2.2. Limit Checking....................................................................................................12-512.2.3. Privilege Levels ..................................................................................................12-612.3. RESTRICTING ACCESS TO DATA........................................................................12-812.3.1. Accessing Data in Code Segments ...................................................................12-1012.4. RESTRICTING CONTROL TRANSFERS..............................................................12-1012.5. GATE DESCRIPTORS .........................................................................................12-1212.5.1. Stack Switching ................................................................................................12-1512.5.2. Returning from a Procedure..............................................................................12-1812.6. INSTRUCTIONS RESERVED FOR THE OPERATING SYSTEM ..........................12-2012.6.1. Privileged Instructions.......................................................................................12-2012.6.2. Sensitive Instructions........................................................................................12-2112.7. INSTRUCTIONS FOR POINTER VALIDATION.....................................................12-2112.7.1. Descriptor Validation.........................................................................................12-2312.7.2. Pointer Integrity and RPL..................................................................................12-2312.8. PAGE-LEVEL PROTECTION ...............................................................................12-2412.8.1. Page-Table Entries Hold Protection Parameters................................................12-2412.8.1.1. RESTRICTING ADDRESSABLE DOMAIN ....................................................12-2512.8.1.2. TYPE CHECKING.........................................................................................12-2512.8.2. Combining Protection of Both Levels of Page Tables ........................................12-2612.8.3. Overrides to Page Protection ............................................................................12-2612.9. COMBINING PAGE AND SEGMENT PROTECTION............................................12-27

CHAPTER 13PROTECTED-MODE MULTITASKING13.1. TASK STATE SEGMENT .......................................................................................13-213.2. TSS DESCRIPTOR ................................................................................................13-413.3. TASK REGISTER...................................................................................................13-513.4. TASK GATE DESCRIPTOR....................................................................................13-613.5. TASK SWITCHING.................................................................................................13-813.6. TASK LINKING.....................................................................................................13-11

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13.6.1. Busy Bit Prevents Loops...................................................................................13-1313.6.2. Modifying Task Linkages...................................................................................13-1413.7. TASK ADDRESS SPACE .....................................................................................13-1413.7.1. Task Linear-to-Physical Space Mapping............................................................13-1413.7.2. Task Logical Address Space.............................................................................13-15

CHAPTER 14PROTECTED-MODE EXCEPTIONS AND INTERRUPTS14.1. EXCEPTION AND INTERRUPT VECTORS............................................................14-114.2. INSTRUCTION RESTART......................................................................................14-314.3. ENABLING AND DISABLING INTERRUPTS...........................................................14-314.3.1. NMI Masks Further NMIs....................................................................................14-314.3.2. IF Masks INTR ...................................................................................................14-414.3.3. RF Masks Debug Faults .....................................................................................14-414.3.4. MOV or POP to SS Masks Some Exceptions and Interrupts ...............................14-514.4. PRIORITY AMONG SIMULTANEOUS EXCEPTIONS AND INTERRUPTS..............14-514.5. INTERRUPT DESCRIPTOR TABLE .......................................................................14-614.6. IDT DESCRIPTORS...............................................................................................14-814.7. INTERRUPT TASKS AND INTERRUPT PROCEDURES.........................................14-914.7.1. Interrupt Procedures.........................................................................................14-1014.7.1.1. STACK OF INTERRUPT PROCEDURE........................................................14-1114.7.1.2. RETURNING FROM AN INTERRUPT PROCEDURE....................................14-1114.7.1.3. FLAG USAGE BY INTERRUPT PROCEDURE..............................................14-1214.7.1.4. PROTECTION IN INTERRUPT PROCEDURES............................................14-1214.7.2. Interrupt Tasks .................................................................................................14-1214.8. ERROR CODE.....................................................................................................14-1414.9. EXCEPTION CONDITIONS..................................................................................14-1414.9.1. Interrupt 0—Divide Error...................................................................................14-1514.9.2. Interrupt 1—Debug Exceptions .........................................................................14-1514.9.3. Interrupt 3—Breakpoint.....................................................................................14-1514.9.4. Interrupt 4—Overflow .......................................................................................14-1614.9.5. Interrupt 5—Bounds Check...............................................................................14-1614.9.6. Interrupt 6—Invalid Opcode ..............................................................................14-1614.9.7. Interrupt 7—Device Not Available .....................................................................14-1614.9.8. Interrupt 8—Double Fault..................................................................................14-1714.9.9. Interrupt 9—(Intel reserved. Do not use.) ..........................................................14-1814.9.10. Interrupt 10—Invalid TSS..................................................................................14-1814.9.11. Interrupt 11—Segment Not Present ..................................................................14-1914.9.12. Interrupt 12—Stack Exception ..........................................................................14-2014.9.13. Interrupt 13—General Protection ......................................................................14-2114.9.14. Interrupt 14—Page Fault...................................................................................14-2214.9.14.1. PAGE FAULT DURING TASK SWITCH ........................................................14-2314.9.14.2. PAGE FAULT WITH INCONSISTENT STACK POINTER ..............................14-2314.9.15. Interrupt 16—Floating-Point Error .....................................................................14-2414.9.15.1. NUMERICS EXCEPTION HANDLING...........................................................14-2514.9.15.2. SIMULTANEOUS EXCEPTION RESPONSE.................................................14-2614.9.16. Interrupt 17—Alignment Check .........................................................................14-2714.9.17. Interrupt 18—Machine Check ...........................................................................14-2814.10. EXCEPTION SUMMARY......................................................................................14-2814.11. ERROR CODE SUMMARY ..................................................................................14-30

CONTENTS EECHAPTER 15INPUT/OUTPUT PAGE15.1. I/O ADDRESSING..................................................................................................15-115.1.1. I/O Address Space .............................................................................................15-115.1.2. Memory-Mapped I/O...........................................................................................15-315.2. I/O INSTRUCTIONS...............................................................................................15-415.2.1. Register I/O Instructions .....................................................................................15-415.2.2. Block I/O Instructions..........................................................................................15-415.3. PROTECTED-MODE I/O........................................................................................15-515.3.1. I/O Privilege Level ..............................................................................................15-615.3.2. I/O Permission Bit Map .......................................................................................15-615.3.3. Paging and Caching............................................................................................15-815.4. ORDERING OF I/O ............................................................................................... .15-8

CHAPTER 16INITIALIZATION AND MODE SWITCHING16.1. PROCESSOR INITIALIZATION..............................................................................16-116.1.1. Processor State after Reset................................................................................16-216.1.2. First Instruction Executed ...................................................................................16-516.2. FPU INITIALIZATION .............................................................................................16-516.2.1. Configuring the Numerics Environment ...............................................................16-616.2.2. FPU Software Emulation.....................................................................................16-816.3. CACHE ENABLING................................................................................................16-916.4. SOFTWARE INITIALIZATION IN REAL-ADDRESS MODE.....................................16-916.4.1. System Tables..................................................................................................16-1016.4.2. NMI Interrupt ....................................................................................................16-1016.5. SOFTWARE INITIALIZATION IN PROTECTED MODE.........................................16-1016.5.1. System Tables..................................................................................................16-1016.5.2. Interrupts..........................................................................................................16-1116.5.3. Paging..............................................................................................................16-1116.5.4. Tasks ...............................................................................................................16-1216.5.5. TLB, BTB and Cache Testing............................................................................16-1216.6. MODE SWITCHING .............................................................................................16-1216.6.1. Switching to Protected Mode ............................................................................16-1316.6.2. Switching Back to Real-Address Mode..............................................................16-1316.7. INITIALIZATION AND MODE SWITCHING EXAMPLE .........................................16-1416.7.1. Goal of this Example.........................................................................................16-1416.7.2. Memory Layout Following Reset .......................................................................16-1416.7.3. The Algorithm...................................................................................................16-1516.7.4. Tool Usage.......................................................................................................16-1716.7.5. STARTUP.ASM Listing .....................................................................................16-1816.7.6. MAIN.ASM Source Code ..................................................................................16-2616.7.7. Supporting Files................................................................................................16-29

EE CONTENTSCHAPTER 17DEBUGGING PAGE17.1. DEBUGGING SUPPORT........................................................................................17-117.2. DEBUG REGISTERS .............................................................................................17-217.2.1. Debug Address Registers (DR0-DR3).................................................................17-317.2.2. Debug Control Register (DR7) ............................................................................17-317.2.3. Debug Status Register (DR6)..............................................................................17-417.2.4. Debug Registers DR4 and DR5 ..........................................................................17-517.2.5. Breakpoint Field Recognition...............................................................................17-517.3. DEBUG EXCEPTIONS...........................................................................................17-617.3.1. Interrupt 1—Debug Exceptions ...........................................................................17-617.3.1.1. INSTRUCTION-BREAKPOINT FAULT............................................................17-717.3.1.2. DATA MEMORY AND I/O BREAKPOINTS......................................................17-817.3.1.3. GENERAL-DETECT FAULT............................................................................17-817.3.1.4. SINGLE-STEP TRAP......................................................................................17-917.3.1.5. TASK-SWITCH TRAP.....................................................................................17-917.3.2. Interrupt 3—Breakpoint Instruction....................................................................17-10

CHAPTER 18CACHING, PIPELINING AND BUFFERING18.1. INTERNAL INSTRUCTION AND DATA CACHES ...................................................18-118.1.1. Data Cache ........................................................................................................18-218.1.2. Data Cache Update Policies ...............................................................................18-318.1.3. Instruction Cache................................................................................................18-318.2. OPERATION OF THE INTERNAL CACHES...........................................................18-318.2.1. Cache Control Bits..............................................................................................18-418.2.2. Cache Management Instructions.........................................................................18-418.2.3. Self-Modifying Code ...........................................................................................18-518.3. PAGE-LEVEL CACHE MANAGEMENT ..................................................................18-518.3.1. PCD Bit ..............................................................................................................18-618.3.2. PWT Bit..............................................................................................................18-618.4. ADDRESS TRANSLATION CACHES......................................................................18-618.5. CACHE REPLACEMENT ALGORITHM..................................................................18-718.6. EXECUTION PIPELINING AND PAIRING...............................................................18-718.7. WRITE BUFFERS ..................................................................................................18-718.8. SERIALIZING INSTRUCTIONS..............................................................................18-7

CHAPTER 19MULTIPROCESSING19.1. LOCKED BUS CYCLES..........................................................................................19-119.1.1. LOCK Prefix and the LOCK# Signal....................................................................19-219.1.2. Automatic Locking ..............................................................................................19-219.2. MEMORY ACCESS ORDERING ............................................................................19-319.3. Pentium® Processor (735\90, 815\100, 1000\120, 1110\133) INTEGRATED APIC ..19-419.3.1. Interrupt Control Mechanism...............................................................................19-619.3.1.1. VALID INTERRUPTS......................................................................................19-619.3.1.2. INTERRUPT SOURCES .................................................................................19-619.3.1.3. BUS ARBITRATION........................................................................................19-619.3.1.4. THE LOCAL APIC STRUCTURE.....................................................................19-719.3.1.5. INTERRUPT DESTINATION AND APIC ID .....................................................19-919.3.1.6. INTERRUPT DISTRIBUTION MODES ..........................................................19-1119.3.1.7. LOCAL VECTOR TABLE ..............................................................................19-12

CONTENTS EEPAGE

19.3.1.8. INTER-PROCESSOR AND SELF INTERRUPTS...........................................19-1419.3.1.9. INTERRUPT ACCEPTANCE.........................................................................19-1819.3.1.9.1. Interrupt Acceptance Decision Flow Chart .................................................19-1919.3.1.9.2. Task Priority Register ................................................................................19-2119.3.1.9.3. Processor Priority Register (PPR) .............................................................19-2119.3.1.9.4. Arbitration Priority Register (APR) .............................................................19-2119.3.1.9.5. Spurious Interrupt .....................................................................................19-2219.3.1.9.6. End-Of-Interrupt (EOI) ..............................................................................19-2219.3.1.10. READING REMOTE APIC REGISTERS........................................................19-2219.3.1.11. LOCAL APIC STATE ....................................................................................19-2319.3.1.11.1. Spurious Interrupt Vector Register.............................................................19-2319.3.1.11.2. Local APIC Initialization.............................................................................19-2419.3.1.11.3. Local APIC State After Power-Up Reset and Init........................................19-2419.3.1.12. LOCAL APIC VERSION REGISTER .............................................................19-2519.3.2. APIC Bus And Inter-APIC Communication Protocol...........................................19-2619.3.2.1. BUS ARBITRATION......................................................................................19-2619.3.2.2. BUS MESSAGE FORMATS..........................................................................19-2619.3.3. Error Handling In APIC .....................................................................................19-3319.3.4. Timer................................................................................................................19-3419.3.4.1. OVERVIEW ..................................................................................................19-3419.3.5. APIC Valid/Invalid Programming Combination...................................................19-3819.3.6. Software Visible Differences Between APIC and 82489DX................................19-3919.3.7. Dual Processing Bootup Handshake Protocol Sequence With Examples...........19-40

CHAPTER 20POWER MANAGEMENT20.1. PENTIUM® PROCESSOR (510\60,567\66) POWER MANAGEMENT.....................20-120.1.1. Introduction to System Management Mode Architecture......................................20-120.1.2. Terminology........................................................................................................20-120.1.3. Pentium® Processor System Management Interrupt Processing..........................20-220.1.3.1. SMRAM..........................................................................................................20-220.1.3.2. SMRAM STATE SAVE MAP ...........................................................................20-420.1.3.3. EXIT FROM SMM...........................................................................................20-620.1.4. System Management Mode Programming Model ................................................20-720.1.4.1. SMM ENTRY ..................................................................................................20-720.1.4.2. PROCESSOR ENVIRONMENT ......................................................................20-920.1.4.3. EXECUTING SYSTEM MANAGEMENT MODE HANDLER...........................20-1020.1.4.4. EXCEPTIONS AND INTERRUPTS WITHIN SMM .........................................20-1020.1.5. SMM Features..................................................................................................20-1120.1.5.1. SMM REVISION IDENTIFIER .......................................................................20-1120.1.5.2. HALT AUTO RESTART.................................................................................20-1220.1.5.3. SMM BASE RELOCATION ...........................................................................20-1220.1.6. Pentium® Processor SMM - Software Considerations........................................20-1420.1.6.1. SMM CODE CONSIDERATIONS..................................................................20-1420.1.6.2. EXCEPTION HANDLING ..............................................................................20-1520.1.6.3. HALT DURING SMM ....................................................................................20-1520.1.6.4. RELOCATING SMRAM TO AN ADDRESS ABOVE ONE MEGABYTE..........20-1520.2. PENTIUM® PROCESSOR (735\90, 815\100, 1000\120, 1110\133) POWER

MANAGEMENT....................................................................................................20-1620.2.1. System Management Mode Architecture...........................................................20-1620.2.2. Pentium® Processor (735\90, 815\100, 1000\120, 1110\133) Power Management

Differences vs. Pentium Processor (510\60, 567\66) .........................................20-16

EE CONTENTSPAGE

20.2.3. System Management Interrupt Via APIC...........................................................20-1720.2.4. I/O Instruction Restart.......................................................................................20-1720.2.4.1. ENABLING I/O INSTRUCTION RESTART ....................................................20-1720.2.4.2. SMRAM STATE SAVE MAP .........................................................................20-1720.2.4.2.1. I/O Instruction Restart Slot ........................................................................20-1920.2.4.3. BACK-TO-BACK SMI# AND I/O INSTRUCTION RESTART...........................20-2020.2.4.4. EXIT FROM SMM.........................................................................................20-2020.2.5. System Management Mode Revision Identifier..................................................20-2020.2.6. SMM — Dual Processing Considerations..........................................................20-2120.2.6.1. DP SMI DELIVERY.......................................................................................20-2220.2.6.2. DP SMRAM ..................................................................................................20-2220.2.6.3. DP SMIACT# ................................................................................................20-22

CONTENTS EEPART III — COMPATIBILITY

CHAPTER 21MIXING 16-BIT AND 32-BIT CODE21.1. USING 16-BIT AND 32-BIT ENVIRONMENTS........................................................21-121.2. MIXING 16-BIT AND 32-BIT OPERATIONS ...........................................................21-221.3. SHARING DATA AMONG MIXED-SIZE CODE SEGMENTS...................................21-321.4. TRANSFERRING CONTROL AMONG MIXED-SIZE CODE SEGMENTS ...............21-421.4.1. Size of Code-Segment Pointer............................................................................21-421.4.2. Stack Management for Control Transfer..............................................................21-421.4.2.1. CONTROLLING THE OPERAND SIZE FOR A CALL ......................................21-721.4.2.2. CHANGING SIZE OF A CALL.........................................................................21-721.4.3. Interrupt Control Transfers..................................................................................21-821.4.4. Parameter Translation ........................................................................................21-821.4.5. The Interface Procedure .....................................................................................21-8

CHAPTER 22VIRTUAL-8086 MODE22.1. EXECUTING 8086 CPU CODE...............................................................................22-122.1.1. Registers and Instructions ..................................................................................22-222.1.2. Address Translation............................................................................................22-322.2. STRUCTURE OF A VIRTUAL-8086 TASK..............................................................22-422.2.1. Paging for Virtual-8086 Tasks.............................................................................22-422.2.2. Protection within a Virtual-8086 Task ..................................................................22-522.3. ENTERING AND LEAVING VIRTUAL-8086 MODE.................................................22-522.3.1. Transitions Through Task Switches.....................................................................22-722.3.2. Transitions Through Trap Gates and Interrupt Gates ..........................................22-822.4. SENSITIVE INSTRUCTIONS..................................................................................22-922.5. VIRTUAL INTERRUPT SUPPORT..........................................................................22-922.6. EMULATING 8086 OPERATING SYSTEM CALLS ...............................................22-1022.7. VIRTUAL I/O ........................................................................................................22-1022.7.1. I/O-Mapped I/O ................................................................................................22-1122.7.2. Memory-Mapped I/O.........................................................................................22-1122.7.3. Special I/O Buffers............................................................................................22-1222.8. DIFFERENCES FROM 8086 CPU........................................................................22-1222.9. DIFFERENCES FROM INTEL 286 CPU ...............................................................22-1522.9.1. Privilege Level ..................................................................................................22-1522.9.2. Bus Lock ..........................................................................................................22-1622.10. DIFFERENCES FROM Intel386™ AND Intel486™ CPUs ....................................22-16

CHAPTER 23COMPATIBILITY23.1. RESERVED BITS...................................................................................................23-123.2. INTEGER UNIT......................................................................................................23-223.2.1. New Functions and Modes..................................................................................23-223.2.2. Serializing Instructions........................................................................................23-223.2.3. Detecting the Presence of New Features ............................................................23-223.2.4. Undefined Opcodes ............................................................................................23-323.2.5. Clock Counts ......................................................................................................23-323.2.6. Initialization and Reset........................................................................................23-323.2.6.1. INTEGER UNIT INITIALIZATION AND RESET................................................23-3

EE CONTENTSPAGE

23.2.6.2. FPU/NPX INITIALIZATION AND RESET.........................................................23-423.2.6.3. Intel486 SX MICROPROCESSOR AND Intel487™ SX MATH COPROCESSOR

INITIALIZATION .............................................................................................23-723.2.7. New Instructions.................................................................................................23-823.2.7.1. NEW PENTIUM® PROCESSOR INSTRUCTIONS...........................................23-823.2.7.2. NEW Intel486 PROCESSOR INSTRUCTIONS................................................23-923.2.7.3. NEW Intel386 PROCESSOR INSTRUCTIONS................................................23-923.2.8. Obsolete Instructions..........................................................................................23-923.2.9. Flags ..................................................................................................................23-923.2.9.1. NEW PENTIUM® PROCESSOR FLAGS .......................................................23-1023.2.9.2. NEW Intel486 PROCESSOR FLAGS ............................................................23-1023.2.10. Control Registers..............................................................................................23-1123.2.10.1. PENTIUM® PROCESSOR CONTROL REGISTERS......................................23-1123.2.10.2. Intel486 PROCESSOR CONTROL REGISTERS...........................................23-1223.2.11. Debug Registers...............................................................................................23-1423.2.11.1. DIFFERENCES IN DR6 ................................................................................23-1423.2.11.2. DIFFERENCES IN DR7 ................................................................................23-1423.2.11.3. DEBUG REGISTERS 4 AND 5......................................................................23-1423.2.12. Test Registers ..................................................................................................23-1523.2.13. Model Specific Registers...................................................................................23-1523.2.14. Exceptions........................................................................................................23-1523.2.14.1. NEW PENTIUM® PROCESSOR EXCEPTIONS ............................................23-1523.2.14.2. NEW Intel486 PROCESSOR EXCEPTIONS .................................................23-1623.2.14.3. NEW Intel386 PROCESSOR EXCEPTIONS .................................................23-1623.2.14.4. INTERRUPT PROPAGATION DELAY...........................................................23-1623.2.14.5. PRIORITY OF EXCEPTIONS........................................................................23-1623.2.14.6. DIVIDE-ERROR EXCEPTIONS.....................................................................23-1723.2.14.7. WRITES USING THE CS REGISTER PREFIX..............................................23-1723.2.14.8. NMI INTERRUPTS........................................................................................23-1723.2.14.9. INTERRUPT VECTOR TABLE LIMIT ............................................................23-1823.2.14.10. INTERRUPTS INSIDE SYSTEM MANAGEMENT MODE ..............................23-1823.2.15. Descriptor Types and Contents.........................................................................23-1823.2.16. Changes in Segment Descriptor Loads .............................................................23-1823.2.17. Task Switching and Task State Segments.........................................................23-1823.2.17.1. PENTIUM® PROCESSOR TASK STATE SEGMENTS ..................................23-1823.2.17.2. TSS SELECTOR WRITES ............................................................................23-1923.2.17.3. ORDER OF READS/WRITES TO THE TSS ..................................................23-1923.2.17.4. USING A 16-BIT TSS WITH 32-BIT CONSTRUCTS......................................23-1923.2.17.4.1. Differences in I/O Map Base Addresses ....................................................23-1923.2.17.4.2. Caching, Pipe-lining, Prefetching...............................................................23-2023.2.17.5. SELF MODIFYING CODE WITH CACHE ENABLED.....................................23-2123.2.18. Paging..............................................................................................................23-2123.2.18.1. PENTIUM® PROCESSOR PAGING..............................................................23-2223.2.18.2. Intel486 PROCESSOR PAGING...................................................................23-2223.2.18.3. ENABLING AND DISABLING PAGING .........................................................23-2223.2.19. Stack Operations..............................................................................................23-2223.2.19.1. PUSH SP......................................................................................................23-2223.2.19.2. FLAGS PUSHED ON THE STACK................................................................23-2323.2.19.3. SELECTOR PUSHES/POPS.........................................................................23-2323.2.19.4. ERROR CODE PUSHES ..............................................................................23-2323.2.19.5. FAULT HANDLING EFFECTS ON THE STACK ............................................23-24

CONTENTS EEPAGE

23.2.19.6. INTERLEVEL RET/IRET FROM A 16-BIT INTERRUPT OR CALL GATE.......23-2423.2.20. Mixing 16- and 32-Bit Segments .......................................................................23-2423.2.21. Segment and Address Wraparound ..................................................................23-2523.2.21.1. SEGMENT WRAPAROUND..........................................................................23-2523.2.22. Write Buffers and Memory Ordering..................................................................23-2623.2.23. Bus Locking......................................................................................................23-2623.2.24. Bus Hold...........................................................................................................23-2723.2.25. Two Ways to Run Intel 286 CPU Tasks.............................................................23-2723.3. FLOATING-POINT UNIT ......................................................................................23-2823.3.1. Control Register Bits.........................................................................................23-2823.3.1.1. EXTENSION TYPE (ET) BIT.........................................................................23-2823.3.1.2. NUMERIC EXCEPTION (NE) BIT .................................................................23-2823.3.1.3. MONITOR COPROCESSOR (MP) BIT .........................................................23-2923.3.1.4. FPU STATUS WORD....................................................................................23-2923.3.1.5. CONTROL WORD........................................................................................23-3023.3.1.6. TAG WORD..................................................................................................23-3023.3.2. Data Types.......................................................................................................23-3023.3.2.1. NaNs ............................................................................................................23-3123.3.2.2. PSEUDOZERO, PSEUDO-NaN, PSEUDEOINFINITY, AND UNNORMAL

FORMATS....................................................................................................23-3123.3.3. Exceptions........................................................................................................23-3123.3.3.1. DENORMAL EXCEPTIONS ..........................................................................23-3123.3.3.2. OVERFLOW EXCEPTIONS..........................................................................23-3223.3.3.3. UNDERFLOW EXCEPTIONS........................................................................23-3223.3.3.4. EXCEPTION PRECEDENCE ........................................................................23-3323.3.3.5. CS AND IP FOR FPU EXCEPTIONS ............................................................23-3323.3.3.6. FPU ERROR SIGNALS.................................................................................23-3323.3.3.7. INVALID OPERATION ON DENORMALS .....................................................23-3423.3.3.8. ALIGNMENT EXCEPTIONS..........................................................................23-3423.3.3.9. SEGMENT FAULT DURING FLDENV...........................................................23-3423.3.3.10. INTERRUPT 7 — DEVICE NOT AVAILABLE ................................................23-3423.3.3.11. INTERRUPT 9 — COPROCESSOR SEGMENT OVERRUN..........................23-3423.3.3.12. INTERRUPT 13 — GENERAL PROTECTION...............................................23-3523.3.3.13. INTERRUPT 16 — FLOATING-POINT ERROR.............................................23-3523.3.4. Instructions.......................................................................................................23-3523.3.5. Transcendental Instructions ..............................................................................23-3823.3.6. Obsolete Instructions........................................................................................23-3823.3.6.1. WAIT PREFIX DIFFERENCES......................................................................23-3823.3.6.2. OPERANDS SPLIT ACROSS SEGMENTS/PAGES ......................................23-3923.3.6.3. FPU INSTRUCTION SYNCHRONIZATION...................................................23-3923.3.7. Numeric Exceptions: Interrupt Sampling Window ..............................................23-3923.3.7.1. USAGE OF THE “NO-WAIT” FLOATING-POINT INSTRUCTION CLASS......23-41

EE CONTENTSPART IV — OPTIMIZATION

CHAPTER 24OPTIMIZATION PAGE24.1. ADDRESSING MODES AND REGISTER USAGE..................................................24-124.2. ALIGNMENT ..........................................................................................................24-224.2.1. Code Alignment ..................................................................................................24-224.2.2. Data Alignment...................................................................................................24-324.3. PREFIXED OPCODES...........................................................................................24-324.4. OPERAND AND REGISTER USAGE......................................................................24-324.5. INTEGER INSTRUCTION SELECTION..................................................................24-4

PART V — INSTRUCTION SET

CHAPTER 25INSTRUCTION SET25.1. OPERAND-SIZE AND ADDRESS-SIZE ATTRIBUTES............................................25-125.1.1. Default Segment Attribute...................................................................................25-125.1.2. Operand-Size and Address-Size Instruction Prefixes...........................................25-125.1.3. Address-Size Attribute for Stack .........................................................................25-225.2. INSTRUCTION FORMAT .......................................................................................25-225.2.1. ModR/M and SIB Bytes ......................................................................................25-425.2.2. How to Read the Instruction Set Pages...............................................................25-925.2.2.1. OPCODE COLUMN........................................................................................25-925.2.2.2. INSTRUCTION COLUMN .............................................................................25-1025.2.2.3. CLOCKS COLUMN.......................................................................................25-1225.2.2.4. DESCRIPTION COLUMN .............................................................................25-1325.2.2.5. OPERATION ................................................................................................25-1325.2.2.6. DESCRIPTION .............................................................................................25-1825.2.2.7. FLAGS AFFECTED ......................................................................................25-1825.2.2.8. PROTECTED MODE EXCEPTIONS.............................................................25-1925.2.2.9. REAL ADDRESS MODE EXCEPTIONS........................................................25-2025.2.2.10. VIRTUAL-8086 MODE EXCEPTIONS...........................................................25-20AAA—ASCII Adjust after Addition ....................................................................................25-21AAD—ASCII Adjust AX before Division ............................................................................25-23AAM—ASCII Adjust AX after Multiply ...............................................................................25-24AAS—ASCII Adjust AL after Subtraction ..........................................................................25-25ADC—Add with Carry ......................................................................................................25-27ADD—Add.......................................................................................................................25-29AND—Logical AND..........................................................................................................25-31ARPL—Adjust RPL Field of Selector ................................................................................25-33BOUND—Check Array Index Against Bounds ..................................................................25-35BSF—Bit Scan Forward ...................................................................................................25-37BSR—Bit Scan Reverse...................................................................................................25-39BSWAP—Byte Swap .......................................................................................................25-41BT—Bit Test ....................................................................................................................25-42BTC—Bit Test and Complement ......................................................................................25-44BTR—Bit Test and Reset.................................................................................................25-46BTS—Bit Test and Set.....................................................................................................25-48CALL—Call Procedure.....................................................................................................25-50CBW/CWDE—Convert Byte to Word/Convert Word to Doubleword..................................25-57

CONTENTS EEPAGE

CDQ—Convert Double to Quad .......................................................................................25-58CLC—Clear Carry Flag ....................................................................................................25-59CLD—Clear Direction Flag...............................................................................................25-60CLI—Clear Interrupt Flag .................................................................................................25-61CLTS—Clear Task-Switched Flag in CR0.........................................................................25-63CMC—Complement Carry Flag........................................................................................25-64CMP—Compare Two Operands.......................................................................................25-65CMPS/CMPSB/CMPSW/CMPSD—Compare String Operands .........................................25-67CMPXCHG—Compare and Exchange .............................................................................25-70CMPXCHG8B—Compare and Exchange 8 Bytes.............................................................25-72CPUID—CPU Identification..............................................................................................25-74CWD/CDQ—Convert Word to Double/Convert Double to Quad........................................25-76CWDE—Convert Word to Doubleword .............................................................................25-77DAA—Decimal Adjust AL after Addition............................................................................25-78DAS—Decimal Adjust AL after Subtraction.......................................................................25-79DEC—Decrement by 1.....................................................................................................25-80DIV—Unsigned Divide......................................................................................................25-81ENTER—Make Stack Frame for Procedure Parameters...................................................25-83F2XM1—Compute 2x–1...................................................................................................25-85FABS—Absolute Value ....................................................................................................25-86FADD/FADDP/FIADD—Add.............................................................................................25-87FBLD—Load Binary Coded Decimal.................................................................................25-89FBSTP—Store Binary Coded Decimal and Pop................................................................25-91FCHS—Change Sign .......................................................................................................25-92FCLEX/FNCLEX—Clear Exceptions.................................................................................25-93FCOM/FCOMP/FCOMPP—Compare Real.......................................................................25-94FCOS—Cosine................................................................................................................25-96FDECSTP—Decrement Stack-Top Pointer.......................................................................25-97FDIV/FDIVP/FIDIV—Divide..............................................................................................25-98FDIVR/FDIVRP/FIDIVR—Reverse Divide.......................................................................25-100FFREE—Free Floating-Point Register............................................................................25-102FICOM/FICOMP—Compare Integer...............................................................................25-103FILD—Load Integer .......................................................................................................25-105FINCSTP—Increment Stack-Top Pointer .......................................................................25-106FINIT/FNINIT—Initialize Floating-Point Unit....................................................................25-107FIST/FISTP—Store Integer............................................................................................25-109FLD—Load Real ............................................................................................................25-110FLD1/FLDL2T/FLDL2E/FLDPI/FLDLG2/FLDLN2/FLDZ—Load Constant ........................25-112FLDCW—Load Control Word.........................................................................................25-114FLDENV—Load FPU Environment.................................................................................25-116FMUL/FMULP/FIMUL—Multiply .....................................................................................25-118FNOP—No Operation ....................................................................................................25-120FPATAN—Partial Arctangent .........................................................................................25-121FPREM—Partial Remainder...........................................................................................25-122FPREM1—Partial Remainder.........................................................................................25-124FPTAN—Partial Tangent................................................................................................25-126FRNDINT—Round to Integer .........................................................................................25-128FRSTOR—Restore FPU State .......................................................................................25-129FSAVE/FNSAVE—Store FPU State ...............................................................................25-131FSCALE—Scale ............................................................................................................25-133FSIN—Sine....................................................................................................................25-134FSINCOS—Sine and Cosine..........................................................................................25-135

EE CONTENTSPAGE

FSQRT—Square Root ...................................................................................................25-137FST/FSTP—Store Real..................................................................................................25-138FSTCW/FNSTCW—Store Control Word.........................................................................25-140FSTENV/FNSTENV—Store FPU Environment ...............................................................25-141FSTSW/FNSTSW—Store Status Word ..........................................................................25-143FSUB/FSUBP/FISUB—Subtract.....................................................................................25-145FSUBR/FSUBRP/FISUBR—Reverse Subtract................................................................25-147FTST—TEST.................................................................................................................25-149FUCOM/FUCOMP/FUCOMPP—Unordered Compare Real............................................25-151FWAIT—Wait.................................................................................................................25-153FXAM—Examine ...........................................................................................................25-154FXCH—Exchange Register Contents .............................................................................25-156FXTRACT—Extract Exponent and Significand................................................................25-158FYL2X—Compute y × log2x...........................................................................................25-160FYL2XP1—Compute y × log2(x +1) ...............................................................................25-161HLT—Halt......................................................................................................................25-163IDIV—Signed Divide ......................................................................................................25-164IMUL—Signed Multiply...................................................................................................25-166IN—Input from Port........................................................................................................25-168INC—Increment by 1 .....................................................................................................25-170INS/INSB/INSW/INSD—Input from Port to String ...........................................................25-171INT/INTO—Call to Interrupt Procedure...........................................................................25-173INVD—Invalidate Cache ................................................................................................25-181INVLPG—Invalidate TLB Entry ......................................................................................25-183IRET/IRETD—Interrupt Return.......................................................................................25-184Jcc—Jump if Condition is Met ........................................................................................25-190JMP—Jump...................................................................................................................25-193LAHF—Load Flags into AH Register ..............................................................................25-198LAR—Load Access Rights Byte .....................................................................................25-199LDS/LES/LFS/LGS/LSS—Load Full Pointer ...................................................................25-201LEA—Load Effective Address ........................................................................................25-204LEAVE—High Level Procedure Exit ...............................................................................25-206LES—Load Full Pointer..................................................................................................25-207LFS—Load Full Pointer..................................................................................................25-208LGDT/LIDT—Load Global/Interrupt Descriptor Table Register ........................................25-209LGS—Load Full Pointer .................................................................................................25-211LLDT—Load Local Descriptor Table Register.................................................................25-212LIDT—Load Interrupt Descriptor Table Register .............................................................25-213LMSW—Load Machine Status Word ..............................................................................25-214LOCK—Assert LOCK# Signal Prefix ..............................................................................25-215LODS/LODSB/LODSW/LODSD—Load String Operand..................................................25-217LOOP/LOOPcond—Loop Control with CX Counter.........................................................25-219LSL—Load Segment Limit .............................................................................................25-221LSS—Load Full Pointer..................................................................................................25-223LTR—Load Task Register..............................................................................................25-224MOV—Move Data..........................................................................................................25-225MOV—Move to/from Control Registers ..........................................................................25-228MOV—Move to/from Debug Registers ...........................................................................25-229MOVS/MOVSB/MOVSW/MOVSD—Move Data from String to String..............................25-231MOVSX—Move with Sign-Extend ..................................................................................25-233MOVZX—Move with Zero-Extend ..................................................................................25-234MUL—Unsigned Multiplication of AL, AX, or EAX...........................................................25-235

CONTENTS EEPAGE

NEG—Two's Complement Negation...............................................................................25-237NOP—No Operation ......................................................................................................25-238NOT—One's Complement Negation...............................................................................25-239OR—Logical Inclusive OR..............................................................................................25-240OUT—Output to Port .....................................................................................................25-242OUTS/OUTSB/OUTSW/OUTSD—Output String to Port .................................................25-244POP—Pop a Word from the Stack .................................................................................25-247POPA/POPAD—Pop all General Registers ....................................................................25-250POPF/POPFD—Pop Stack into FLAGS or EFLAGS Register .........................................25-252PUSH—Push Operand onto the Stack ...........................................................................25-254PUSHA/PUSHAD—Push all General Registers ..............................................................25-256PUSHF/PUSHFD—Push Flags Register onto the Stack .................................................25-258RCL/RCR/ROL/ROR-—Rotate.......................................................................................25-260RDMSR—Read from Model Specific Register ................................................................25-263RDTSC—Read from Time Stamp Counter .....................................................................25-265REP/REPE/REPZ/REPNE/REPNZ—Repeat Following String Operation.........................25-267RET—Return from Procedure ........................................................................................25-271ROL/ROR—Rotate ........................................................................................................25-275RSM—Resume from System Management Mode ..........................................................25-276SAHF—Store AH into Flags ...........................................................................................25-277SAL/SAR/SHL/SHR—Shift Instructions ..........................................................................25-278SBB—Integer Subtraction with Borrow ...........................................................................25-281SCAS/SCASB/SCASW/SCASD—Compare String Data..................................................25-283SETcc—Byte Set on Condition.......................................................................................25-285SGDT/SIDT—Store Global/Interrupt Descriptor Table Register.......................................25-287SHL/SHR—Shift Instructions..........................................................................................25-289SHLD—Double Precision Shift Left ................................................................................25-290SHRD—Double Precision Shift Right..............................................................................25-292SIDT—Store Interrupt Descriptor Table Register ............................................................25-294SLDT—Store Local Descriptor Table Register................................................................25-295SMSW—Store Machine Status Word .............................................................................25-297STC—Set Carry Flag .....................................................................................................25-298STD—Set Direction Flag................................................................................................25-299STI—Set Interrupt Flag ..................................................................................................25-300STOS/STOSB/STOSW/STOSD—Store String Data .......................................................25-302STR—Store Task Register.............................................................................................25-304SUB—Integer Subtraction..............................................................................................25-305TEST—Logical Compare ...............................................................................................25-307VERR, VERW—Verify a Segment for Reading or Writing ...............................................25-308WAI

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