橡 CadMOD Design Technology, Inc. Confidential 2/22/99 JPM a.4 #3 Company Mission Provide premium...

CadMOS Design Technology, Inc.

Presents

Noise Analysis for IC Design

CadMOS Confidential 2/22/99 JPM a.4 #2

Company Introduction

• Privately held, founded in San Jose CA, Aug 1997

• 3 co-founders:– Dr. Charlie Huang CEO, Ex VP of R&D Synopsys/EPIC,

originator of PowerMill, manager of PathMill

– Dr. Ken Shepard CTO, Ex IBM Yorktown, G4 µP design lead,noise analysis expert

– Dr. Vinod Narayanan VP of R&D , Ex IBM Yorktown, staticnoise analysis developer, static analysis expert

• $3m investment from venture capital (USVP) andother investors


Company Mission

Provide premium solutions to noise, signalintegrity, and other electrical problems in

advanced leading edge designs

Provide premium solutions to noise, signalintegrity, and other electrical problems in

advanced leading edge designs


Company Status

• Current staff of 18 people (9 R&D)

• Production release of PacifIC, Dec 98– Static noise analyzer for digital ICs

– First orders received in Q1 1999 from TI and AMD

• Acquired technology and R&D staff of ApresTechnologies, Inc. in January 1999– Pioneers in mixed signal substrate noise analysis– New product SeismIC, alpha released May 1st 1999


Customer Feedback

“We are incorporating PacifIC into our design flow toadd an extra level of robustness and reliability to ourdesigns, by ensuring that we have caught andcorrected before tape out any potential noiseproblems.”

Don Draper

AMD Fellow and K6-2 Circuit Design Manager

“We are incorporating PacifIC into our design flow toadd an extra level of robustness and reliability to ourdesigns, by ensuring that we have caught andcorrected before tape out any potential noiseproblems.”

Don Draper

AMD Fellow and K6-2 Circuit Design Manager


Customer Feedback

“We purchased PacifIC because we believe it can helpus manage the noise immunity of our highperformance DSP designs more effectively.”

Robin C. Sarma

ASP-EDA, Texas Instruments Inc.

“We purchased PacifIC because we believe it can helpus manage the noise immunity of our highperformance DSP designs more effectively.”

Robin C. Sarma

ASP-EDA, Texas Instruments Inc.


Dramatic increase of on-chip noise and decrease in noise immunity

Technology Trends

• Higher interconnect densities

• Faster clock frequencies

• Scaling of threshold voltages


What is Noise?

• Noise is any deviation in voltage in a circuit fromnominal supply or ground– Noise can cause timing problems, functional failures and low yield

– Noise problems are very difficult to debug

Node X

Node Y

Waveform on Node X due to switching on node Y


Digital Noise Sources:

CLK

Gnd2

Supply Noise

Vdd2

Gnd1

Vdd1

Supply Noise

Coupling Noise

PropagatedNoise

Charge Sharing

Static Noise Analysis for Digital ICs

PacifIC

Introduces

CadMOS Design Technology,Inc.


PacifIC - Static Noise Analyzer

• Rigorously checks every node in the design withoutinput vectors or design rules– Checks are based on the transient characteristics of noise

• Identifies nodes that are noise sensitive

• Identifies over design– Insensitive nodes may be over constrained by over sized

feedback or pull-up devices


Benefits of Using PacifIC

• Fewer costly silicon re-spins needed to fix functionalfailures caused by noise.

• Improved yield by improving a design's noiseimmunity

• Improved performance or lower power by permittingmore aggressive yet robust circuit design styles

• Reduced chip area through identifying unnecessaryover design


Noise Sensitivity

Robust FailingOverDesigned

0 0.1 0.5 1.0

Marginal

• A node is deemed sensitive to noise if it amplifiesrather than attenuates noise


Noise Sensitivity

• A node is deemed sensitive to noise if it amplifiesrather than attenuates noise

Vout

Vin Vin

δVout/δVin

Attenuatednoise

Amplifiednoise

VoutVin

-

+-

+

1in(t)V

Vout(t)S(t) ≤=

δδ

in

out

vv

δδ


Transient Nature of Noise

IN

0UT

in

out

vv

δδ


Noise Sensitivity Vs DC Margin

• Many nets (4.5K) have considerable noise > 25% VDD

• Implies examination of 4.5K potential problems

Coupling noise distribution

0

968

203 144492

3441

4284 4 7 8 1 1 0 0

0

1000

2000

3000

4000

5% 15%

25%

35%

45%

55%

65%

80%

noise peak as percentage of VDD


Noise Sensitivity Vs DC Margin

• Only 9 nets warrant investigation

• Implies 500X less work!

Distribution of noise sensitivity

1 0 1 2 3 2 000101122

4453

1006

223 1 10

1000

2000

3000

4000

5000

0.05

0.15

0.25

0.35

0.45

0.55

0.65 0.

80.

9 1

Sensitivity

FailingNet


• Built-in transient analysis engine for localizedsimulation

• Sophisticated logic analysis to determine stimulus forworst case noise scenarios

• Built in noise sensitivity metric– Determines the transient sensitivity of receiving circuitry to noise

• Krylov based RLC interconnect modeling included asnative in the simulator

PacifIC - Core Technology


PacifIC : Static Noise Analysis

Check

Propagate

SimulateSimulate

User defined noise on input

Check

Propagate

Simulate

Check


DSPF UDN Models

PacifIC

PacifIC : Data Flow

Command File(TCL)

NoiseReports

(HTML)

SPICESnapshot(s)

Noise Abstract(ECHO)

WaveformReporting

CMOSDevice Model

SpiceNetlist(s)with RCs

SpiceNetlist(s)with RCs

Logic ConstraintsTiming ConstraintsI/O noise assertionsXcap factor

Bsim3


PacifIC in the Design Flow

RC Extraction

Place & Route

Floorplanning

Synthesis

Layout

Circuit Design

Logic Design

RTL

RC Extraction

Tape Out

DRC/LVS

PacifIC

PacifIC

PacifIC

PacifIC

Custom Design FlowCell Based Flow


PacifIC : Features

• Propagates worst-case noise from primary inputs toprimary outputs– Includes full PWL noise waveform propagation

• Analyzes the impact of supply and substrate noise– Supplied by the user as fixed variations

• Supports user defined constraints– logic : xor, and, or, not, mutex

– timing : arrival time, slew

• Supports TCL commands based on pattern matching,wildcarding and sub-circuit type


CLK

D1

DO

Example - Leakage

• 32-Bit Integer Adder– 0.25µ, 1.8V process

– 36K transistors

– 565 Xcaps, 172K Rs

19m

Run Time

104Mb

Memory

36

Failures

“1”

D1

CLK

DO

0.18V

1.0V


Example - Coupling

• Microprocessor Cache– 0.25µ, 1.8V process– 467K transistors

• 54K flat transistor, 8 UDNs

– 9K Xcaps, 345 Rs

1h 4m

Run Time

186Mb

Memory

46

Failures

A

DI

DO

CLKA “1”

A

Attacker

“1”

CLK

DI DO“0”


Example - Coupling

• Standard Cell Block– 0.25µ, 1.5V process

– 98K transistors

– 1.5M Rs, 2.8M Xcaps

44m 420Mb 9

Run Time Memory Failures

IN1

n1

Attacker #1 - 0.410V

Attacker #2 - 0.825V

n2

n3

IN1

n1,n2,n3

1.235V


Example - Charge Sharing

• Custom µP Block– 0.28µ, 1.6V process

– 325K transistors

– 153K Xcaps

2h 9m 185Mb 484

Run Time Memory Failures

OUT

“1”

CLK

DOUT

“0”

“0”

“1”

PacifICSPICE

DOUT

OUT

1.6V

0.0V

0.8V


Example - Over Design

• 64 bit adder– 0.18µ, 1.8V process

– 9K transistors, 112K Xcaps, 48K Rs

6m

Run Time

20Mb

Memory

0

Failures

CLK,D2

D1

DO 1.8V

1.8V

0.5VDO

D2

CLK

CLK

D1

Attacker

80.≈strengthdownPullstrengthlatchHalf


010

2030

4050

60

Delay ps

Sensitivity *100

Half Latch Strength/ Pulldown Strength

1 0.08

1 0.08

Over Design cont.

AttackerDO

D1

D2

CLK

CLK

0

50

100

150

200

Delay ps

Sensitivity *100

70ps

3ps

1.74

48ps

14ps

0.5

Half Latch Strength/ Pulldown Strength

Process 1

Process 2


PacifIC Benchmark Summary

Xtrs Rs Xcaps Runtime Memory Failures17K 0 0 0:06:07 16MB 0(0)47K 0 0 0:10:51 41MB 69(11)37K 545K 1.6K 0:18:04 162MB 3(1)95K 1.54M 2.8M 0:44:31 420MB 9(1)54K 345 9.5K 1:04:44 185MB 46(6)325K 0 153K 2:08:58 185MB 484(13)653K 1.2M 2M 3:00:57 560MB 1(1)

• All benchmarks run on Sun UltraSPARC 60, time in hrs• Failure numbers in parentheses are the number of unique failures


PacifIC Vs SPICE

PacifICSPICE


Summary

• Noise has become a significant problem for UDSM

• Static noise analysis is key for large digital designs

• PacifIC can isolate nodes with low noise immunity

• PacifIC can help improve design quality, increaseyield and shorten time to market

橡 CadMOD Design Technology, Inc. Confidential 2/22/99 JPM a.4 #3 Company Mission Provide premium...

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