C. H. Ziesler etal., 2003

Energy Recovering ASIC Design

Advanced Computer Architecture LaboratoryDepartment of Electrical Engineering and Computer Science

University of MichiganAnn Arbor, MI

Conrad H. Ziesler Joohee Kim

Marios C. Papaefthymiou

C. H. Ziesler etal., 2003

Design for Low Power

Scale voltage to reduce swing

Pipeline to meet throughput target

Total dissipation decreases…

0 0.5 1.0 1.5 2.00

250

500

750

1000

voltage (V)

fre

qu

en

cy (

MH

z)

C. H. Ziesler etal., 2003

Clock Power Dissipation

… but fraction of clock power increases

Typical approach to reduce clock power: clock gating

Cons: design complexity and cost

tree

flip-flop tree

flip-flopPipeliningVoltage scaling

C. H. Ziesler etal., 2003

An Alternative Approach: Energy Recovery

Main ideaRecycle energy stored in circuit capacitance

Inter-dependent research issues1. Which capacitance to recover from?2. How to store/reuse recovered energy?3. What circuits to do the recovery?

1. 2. 3.

C. H. Ziesler etal., 2003

Non-Dissipative rail-drivers for adiabatic circuits S.G. Younis, T.F. Knight, Jr. -- ARVLSI'95

Clock-Powered CMOS: A Hybrid Adiabatic Logic Style for Energy-Efficient Computing N. Tzartzanis, W. C. Athas -- ARVLSI'99

Driving a capacitive load without dissipating fCV2 L. Svensson and J. G. Koller -- SLPE'94

A low power sinusoidal clock B. Voss, M. Glesner -- ISCAS'01

And many, many others.... Few real working chips, however.

Previous Work in Energy Recovery

C. H. Ziesler etal., 2003

Our Contributions

Energy recovery technologies for reducing clock dissipation

Single-phase sinusoidal clock Efficient, LC resonant clock generator Low power sinusoidally clocked flip-flop

Key attributes

Compatible with ASIC design flow, low overhead High frequency (200-500MHz) Low voltage (1.0-1.5V) Real, working chips (in 0.25m logic process)

C. H. Ziesler etal., 2003

System Overview

C. H. Ziesler etal., 2003

Introducing PTERF

PTERF: Energy recovering flip-flop

Clock signal: Single phase, resonant

sinusoid

Dissipates only when D and Q are

switching

Low voltage operation at high speeds

Delay similar to conventional flip-flop

Fully compatible with standard-cell design flows

16 transistors84 m2

C. H. Ziesler etal., 2003

PTERF Structure

C. H. Ziesler etal., 2003

PTERF Operation

C. H. Ziesler etal., 2003

PTERF Characterization

Energy per cycle Idle: D, Q constant Active: D, Q changing Order of magnitude difference

200MHz 300MHz 500MHz1

10

100

1000Flip-Flop Energy

activeidle

frequency

ener

gy (

fJ)

200MHz 300MHz 500MHz0

250

500

750

1000

1250

1500Flip-Flop Delay

PTERF

frequency

Tdq

(ps

) Delay D-Q Varies with frequency Constant 25% of clock cycle Similar to conventional ffs

C. H. Ziesler etal., 2003

Resonant Clock Generator

Resonate entire clock capacitance with small inductor

Pump resonant system with NMOS switch at appropriate times

NMOS switch only conducts incremental losses whenever ON

NMOS Switch

Control

Pre-driver

Driver

C. H. Ziesler etal., 2003

Clock Generator Operation

C. H. Ziesler etal., 2003

Simulation Based Evaluation

Designed ASIC with • PTERF • resonant clock generator

Dual-mode system conventional energy recovery

Direct comparison of dissipation at target throughput

C. H. Ziesler etal., 2003

ASIC Statistics

Discrete wavelet transform

3897 gates, 413 ffs

15571 transistors

400m x 900m

13.6 pF , 21 nH

300 MHz , 1.5V

0.25m logic process

Dual-modeDWT

Clock generator

C. H. Ziesler etal., 2003

Simulation Results

Total system dissipation

Conventional mode includes clock tree

Energy recovery mode includes on-chip clock generator

300MHz, 1.5V Energy Recovery ConventionalIdle 6.74pJ 29.72pJ

Active 68.47pJ 78.28pJ

C. H. Ziesler etal., 2003

Summary Technologies for reducing clock dissipation through energy recovery

Novel flip-flop

Novel resonant clock generator

Drop-in replacement for clocking system in conventional ASIC design flow

Complexity of explicit clock gating eliminated

Simulation of DWT ASIC at 300 MHz

4X savings when idle

15% savings when active

C. H. Ziesler etal., 2003

Acknowledgments and Links

Funded in part by U.S. Army Research Office DAAG-55-97-1-0250 DAAD-19-99-1-0340

For more information please visitwww.eecs.umich.edu/acal/energyrecovery