Beta Multiplier based current reference
Design and Standard cell layout of NAND, PGI and FAST LATCH
Matlab model of N Bit 1.5 bit per stage RSD based pipelined ADC
ADC testing using histogram method
Srikanth Reddy Paramaiahgari 1206321047 Project Part2
Srikanth Reddy Paramaiahgari 1206321047 Project Part1
FinalProject_PartIII_ProjectReport