A PRESENTATION

ONVLSI DESIGN

(Industrial Training at MSME Tool Room Kolkata)

Presentation By:

Gokul Boro (Gau-C-10/L-321)Bidu Bhushan Barman (Gau-C-10/L-324)Mwnsuma Baro (Gau-C-10/L-329)Nayan Jyoti Boro (Gau-C-10/L-334)Tamash Khaklary (Gau-C-10/224)Anupam Rajbongshi (Gau-C-10/260)Dhireswar Barman (Gau-C-10/L-338)

Contents

1. MSME Tool Room Kolkata - A Brief Profile2. Introduction to VLSI3. Software used in VLSI Design4. VLSI Design Hierarchy5. Basic VHDL Code6. Verilog Using Altera7. Design using Microwind8. Programmeable Logic Device (PLD)9. Downloading process on PLD using XILINX10. Conclusion

It has been established under Technical Co-operation Programme between Governments of India and Denmark.

Set up with a view to foster the growth of the Small & Medium Enterprises (SME).

It provides invaluable technological support to the Industry.

1. MSME Tool Room Kolkata - A Brief Profile

2. Introduction to VLSI Stands for Very Large Scale Integration.

Process of creating integrated circuits by combining thousands of transistor-based circuits into a single chip.

Design/Manufacturing of extremely small, complex circuit modified semiconductor material.

Language used for designing VLSI circuitVHDLVerilog

Basic difference between VHDL and Verilog

VHDL Verilog

1. Not Case Sensitive

1. Case sensitive

2. Difficult to learn 2. Easy to learn

3. Based on Pascal 3. Based on C

3. Software Used in VLSI Design

DSCH

XILINX

ALTERA

MICROWIND

Use of DSCH

Three types of designs:

Gate Level Design

Chip Level Design

CMOS Level Design

3. Software Used in VLSI Design (Contd.)

USE OF XILINX AND ALTERA

Through VHDL and Verilog

Data Flow

Behavioural

Structural

3. Software Used in VLSI Design (Contd.)

USE OF MICROWIND

Microwind Software is used for layout design of various circuits.

3. Software Used in VLSI Design (Contd.)

4. VLSI Design Hierarchy

Flow diagram

Algorithm design

Design Entry

Fundamental simulation

Specification

Specify what to design.

Design an Algorithm to implement in software.

Enter the design in computer system, so that it can be compiled by the design software.

After completion of entry into computer, simulate to see the result.

5. Basic VHDL Code

Library declaration

Entity

Architecture

Configuration

Library Declaration

For example-

Library ieee; Use ieee.std_logic_1164.all; Use ieee.std_logic_arith.all; Use ieee.std_logic_unsigned.all;

Library Library_name; Use library_name.package_name.package_parts;

5. Basic VHDL Code (Contd.)

Entity & Port Declaration

For example- Entity and_gate is Port ( a, b : in std_logic; y : out std_logic); End and_gate;

Entity<entity_ name> is Port (port_name:<direction><data_type>; port_name:<direction><data_type>); End<entity_name>;

5. Basic VHDL Code (Contd.)

Architecture Declaration

Architecture< architecture_name> of <entity_name> is begin . . . . . . . . end architecture_name

5. Basic VHDL Code (Contd.)

Types of VHDL Architecture

Data flow -It uses concurrent signal assignment statement. - It describes the transfer of data from input to output

signals. Behavioral - It is a high level description. - It contains a set of assignment statement to

represent behaviour. Structural - Describe the circuit structure in terms of logic

gates - Interconnects wiring between logic gates to form a

circuit net list.

5. Basic VHDL Code (Contd.)

6.Verilog using Altera:

• Dataflow: syntax

module<module name>(port name);input<input names>;output<output names>;

{program part}

end module

6.Verilog using Altera(contd.):• Behavioral:

syntax:module<module name>(port list);input<input names>;output<output names>;Reg <output name>;always@<input name>;begin

{program part}

endend module

6.Verilog using Altera(contd.):• Structural:

syntax:module<module name>(port list);input<input names>;output<output names>;wire <port name>;<component name><level>(port mapping)end module

6.Verilog using Altera(contd.):Syntax for clock:

syntax:module<module name>(port list);input<input names>;output<output names>;Reg <output name>;always@(posedge clk)begin{program part}end module

7.Design using Microwind

Microwind is a windows tool for designing and

simulating microelectronic circuits at layout

level.

Process: diffusion, poly-sillicon, pads, deep

submicron CMOS design and n-well process.

Microwind Window

7.Design using Microwind(contd.)

Microwind Design (For CMOS inverter)

7.Design using Microwind(contd.)

8.PROGRAMMABLE LOGIC DEVICE (PLD)A PLD is used to build reconfiguration of

the digital circuits.

TYPES OF PLDSIMPLE PROGRAMMABLE LOGIC DEVICE

(SPLD)COMPLEX PROGRAMMABLE LOGIC DEVICE

(CPLD)FIELD-PROGRAMMABLE GATE ARRAY (FPGA)

9.DOWNLOADING PROCESS ON PLD USING XILINX

Write your program. Then check the property of PLD.Browse on user constraints and double click on assign package pins.Then give pin numbers as input and output.Then save it.

DOWNLOADING PROCESS ON PLD USING XILINX (Contd.)

Then browse on generate programming file.

Double click on configure device.Finish and ok.Then select file and then open and then ok.Right click on your Xilinx and click on

program and then apply and then ok.

10.ConclusionLearned the various technology, application and scope of

VLSI.Learned about the applications of VLSI design softwares

and programming languages .Downloading in PLD (Programmable Logic Device). Knew that there is tremendous scope and growth for those

who choose VLSI design as a career.

THANK YOU