Post on 10-Jan-2016
description
Virtex II Pro Virtex II Pro based SoPC based SoPC
designdesign
Part 2Part 2
AdvancedAdvanced
Before we start…Before we start…
TheThe guidance consists of two parts: guidance consists of two parts: IntroductionIntroduction
SoPC conceptSoPC concept Working platformsWorking platforms Design Flow – building basic systemDesign Flow – building basic system
Advanced topicsAdvanced topics Adding user coresAdding user cores JTAGJTAG Debug Debug SimulationSimulation DemonstrationDemonstration
TodayToday
OutlineOutline SoPC architecture – reviewSoPC architecture – review
PLB busPLB bus OPB busOPB bus
Adding user coresAdding user cores Adding cores without a busAdding cores without a bus IPIF architectureIPIF architecture Adding cores to OPB and PLB busesAdding cores to OPB and PLB buses
JTAG portJTAG port Hardware and Software debugHardware and Software debug
Hardware debugger – Chip Scope ProHardware debugger – Chip Scope Pro Software debugger – XMDSoftware debugger – XMD
DemonstrationDemonstration
SoPC architectureSoPC architecture Processor Local Bus (PLB)Processor Local Bus (PLB)
32-bit address, 64-bit data32-bit address, 64-bit data Separate read and write Separate read and write
busesbuses High performanceHigh performance Low loadLow load
On-Chip peripheral bus On-Chip peripheral bus (OPB)(OPB) 32-bit address, 32-bit data32-bit address, 32-bit data Max peripheralsMax peripherals High loadHigh load
Device Control Register bus Device Control Register bus (DCR)(DCR) 32-bit transfer to and from 32-bit transfer to and from
GPRGPR Direct accessible by PPC Direct accessible by PPC
PLB busPLB bus
64 bit data / 32 bit address configuration64 bit data / 32 bit address configuration Up to 16 masters and slavesUp to 16 masters and slaves Decoupled address, read data, and write data Decoupled address, read data, and write data
busesbuses Concurrent read and write transferConcurrent read and write transfer Address pipelining that reduces bus latency by Address pipelining that reduces bus latency by
overlapping a new write request with an ongoing overlapping a new write request with an ongoing write transfer and up to three read requests with an write transfer and up to three read requests with an ongoing read transferongoing read transfer
Four priority levels for master requestsFour priority levels for master requests Byte-enable capability, supporting unaligned Byte-enable capability, supporting unaligned
transferstransfers
PLB busPLB bus architecturearchitecture Each master has its Each master has its
own data read, write own data read, write and address bus (all and address bus (all merged to wide merged to wide buses)buses)
All slaves have All slaves have shared write data shared write data and address busand address bus
Each slave has its Each slave has its own read data bus own read data bus
All slaves’ read data All slaves’ read data buses are merged to buses are merged to one wide bus (OR one wide bus (OR instead of merge in instead of merge in IBM implementation)IBM implementation)
PLB bus master PLB bus master attachmentattachment
PLB arbiterPLB arbiterPLB MasterPLB Master
[n][n]
Arbitration signalsArbitration signals
M_BE M_BE [n*8:n*8+7][n*8:n*8+7]
M_ABus [n*32:n*32+31]M_ABus [n*32:n*32+31]
M_wrDBus [n*64:n*64+63]M_wrDBus [n*64:n*64+63]
PLB_MRdDBus [n*64:n*64+63]PLB_MRdDBus [n*64:n*64+63]
Naming conventions:Naming conventions: Each signal from arbiter to master starts from “PLB”Each signal from arbiter to master starts from “PLB” Each signal from master to arbiter starts from “M”Each signal from master to arbiter starts from “M”
PLB bus slave attachmentPLB bus slave attachment
PLB arbiterPLB arbiterPLB SlavePLB Slave
[m][m]
PLB_ABus [0:31]PLB_ABus [0:31]
PLB_wrDBUS [0:63]PLB_wrDBUS [0:63]
Sl_rdDBus [m*64:m*64+63]Sl_rdDBus [m*64:m*64+63]
Naming conventions:Naming conventions: Each signal from arbiter to slave starts from “PLB”Each signal from arbiter to slave starts from “PLB” Each signal from slave to arbiter starts from “Sl”Each signal from slave to arbiter starts from “Sl”
OPB busOPB bus Actually, AND-OR interconnect structure Actually, AND-OR interconnect structure
(distributed multiplexer)(distributed multiplexer) 8-128 bit data / 16-32 bit address configuration8-128 bit data / 16-32 bit address configuration Bus arbitration overlapped with last cycle of bus Bus arbitration overlapped with last cycle of bus
transferstransfers 16 masters and unlimited number of slaves16 masters and unlimited number of slaves 8-64-bit slaves and 32-64-bit masters8-64-bit slaves and 32-64-bit masters Dynamic bus sizing: byte, halfword, fullword, and Dynamic bus sizing: byte, halfword, fullword, and
doubleword transfersdoubleword transfers Optional Byte Enable supportOptional Byte Enable support Single cycle transfer of data between OPB bus Single cycle transfer of data between OPB bus
master and OPB slavesmaster and OPB slaves
OPB busOPB bus architecturearchitecture Each master has its Each master has its
own read data and own read data and address bus (all ORed address bus (all ORed to single buses)to single buses)
Each slave has its Each slave has its own read data bus own read data bus (all ORed with (all ORed with masters’ read data masters’ read data bases to single bus)bases to single bus)
ORed masters’ and ORed masters’ and slaves’ data buses slaves’ data buses represents shared represents shared OPB write data busOPB write data busOPB_DBus
OPB bus master OPB bus master attachmentattachment
OPB busOPB bus
logiclogicOPB MasterOPB Master
[n][n]
Mn_BE [0:7]Mn_BE [0:7]
Mn_DBus [0:63]Mn_DBus [0:63]
Mn_ABus [0:31]Mn_ABus [0:31]
OPB_DBus [0:63]OPB_DBus [0:63]
Naming conventions:Naming conventions: Each signal from bus logic to master starts from “OPB”Each signal from bus logic to master starts from “OPB” Each signal from master to bus logic starts from “Mn”Each signal from master to bus logic starts from “Mn”
OPB bus slave attachmentOPB bus slave attachment
OPB busOPB bus
logiclogicOPB SlaveOPB Slave
[m][m]
OPB_ABus [0:31]OPB_ABus [0:31]
Sln_DBUS [0:63]Sln_DBUS [0:63]
OPB_DBus [0:63]OPB_DBus [0:63]
Naming conventions:Naming conventions: Each signal from bus logic to slave starts from “OPB”Each signal from bus logic to slave starts from “OPB” Each signal from slave to bus logic starts from “Sln”Each signal from slave to bus logic starts from “Sln”
Adding user logic to Adding user logic to designdesign
Choose chip with required hard cores inside
Add required soft cores
Add user logic
Question: How Question: How user logic is user logic is
added to added to design?design?
Answer : user cores creationAnswer : user cores creation
EDK can only recognize logic organized in a form of coreEDK can only recognize logic organized in a form of core
User core directory User core directory structurestructure
Project root directoryProject root directory
pcorepcoress
<User-core-<User-core-name_version>name_version>
datadata devldevl hdlhdl netlistnetlist docdoc
OptionalOptionalvhdlvhdl verilogverilog““mpd” filempd” file
““pao” filepao” file
““bbd” filebbd” file
Usually this Usually this directory structure directory structure
is created is created automatically by automatically by
“Import peripheral “Import peripheral Wizard”! Wizard”!
User core directory User core directory structurestructure
DataData directory contains EDK interface files for directory contains EDK interface files for the core:the core: ““mpd” file – mpd” file – MMicroprocessor icroprocessor PPeripheral eripheral DDescriptionescription ““pao” file – pao” file – PPeripheral eripheral AAnalyze nalyze OOrderrder ““bbd” file – bbd” file – BBlack lack BBox ox DDefinitionefinition
HDLHDL directory contains HDL (VHDL or Verilog) directory contains HDL (VHDL or Verilog) files representing the corefiles representing the core
Netlist Netlist directory contains synthesized netlists directory contains synthesized netlists added as a part of core (not always all the core added as a part of core (not always all the core is written in HDL)is written in HDL)
DocDoc directory contains documentation of the directory contains documentation of the peripheralperipheral
DevlDevl directory contains different files created directory contains different files created by “Import Peripheral Wizard”by “Import Peripheral Wizard”
Press to see examplePress to see example
Press to see examplePress to see example
Press to see examplePress to see example
MPD fileMPD file
MPD file defines the interface of MPD file defines the interface of the peripheralthe peripheral
MPD includes:MPD includes: List of ports and default connectivity List of ports and default connectivity
for bus interfacesfor bus interfaces List of parameters and default valuesList of parameters and default values Any MPD parameter is overwritten by Any MPD parameter is overwritten by
the equivalent MHS assignmentthe equivalent MHS assignment
MPD file - exampleMPD file - exampleBEGIN opb_gpio## Peripheral OptionsOPTION IPTYPE = PERIPHERALOPTION IMP_NETLIST = TRUEOPTION SIM_MODELS = BEHAVIORAL:STRUCTURAL## Bus InterfacesBUS_INTERFACE BUS=SOPB, BUS_STD=OPB, BUS_TYPE=SLAVE## Generics for VHDL or Parameters for VerilogPARAMETER C_BASEADDR=0xFFFFFFFF, DT=std_logic_vector, MIN_SIZE=0x100, BUS=SOPBPARAMETER C_HIGHADDR=0x00000000, DT = std_logic_vector, BUS=SOPBPARAMETER C_OPB_DWIDTH=32, DT=integer, BUS=SOPBPARAMETER C_OPB_AWIDTH=32, DT=integer, BUS=SOPBPARAMETER C_GPIO_WIDTH=32, DT=integerPARAMETER C_ALL_INPUTS=0, DT=integer## PortsPORT OPB_Clk = “”, DIR=IN, SIGIS=CLK, BUS=SOPBPORT OPB_Rst = OPB_Rst, DIR=IN, BUS=SOPBPORT OPB_ABus = OPB_ABus, DIR=IN, VEC=[0:C_OPB_AWIDTH-1], BUS=SOPBPORT OPB_BE = OPB_BE, DIR=IN, VEC=[0:C_OPB_DWIDTH/8-1], BUS=SOPBPORT OPB_DBus = OPB_DBus, DIR=IN, VEC=[0:C_OPB_DWIDTH-1], BUS=SOPBPORT OPB_RNW = OPB_RNW, DIR=IN, BUS=SOPBPORT OPB_select = OPB_select, DIR=IN, BUS=SOPBPORT OPB_seqAddr = OPB_seqAddr, DIR=IN, BUS=SOPBPORT GPIO_DBus = Sl_DBus, DIR=OUT, VEC=[0:C_OPB_DWIDTH-1], BUS=SOPBPORT GPIO_errAck = Sl_errAck, DIR = OUT, BUS=SOPBPORT GPIO_retry = Sl_retry, DIR = OUT, BUS=SOPBPORT GPIO_toutSup = Sl_toutSup, DIR=OUT, BUS=SOPBPORT GPIO_xferAck = Sl_xferAck, DIR=OUT, BUS=SOPBPORT GPIO_IO = “”, DIR=INOUT, VEC=[0:C_GPIO_WIDTH-1], ENABLE=MULTEND
PAO filePAO file
A PAO file contains a list of HDL files that A PAO file contains a list of HDL files that are needed for synthesis, and defines are needed for synthesis, and defines the analyze order for compilationthe analyze order for compilation
Following format is used in PAO:Following format is used in PAO:lib library hdl_file_basename
Library specifies the unique library for the peripheral, and HDL file names are specified without a file extension
All names are in lower-case Usually, library version is also specified
PAO file - examplePAO file - example
lib common_v1_00_a common_types_pkg
lib common_v1_00_a pselectlib opb_gpio_v1_00_a gpio_corelib opb_gpio_v1_00_a opb_gpio
BBD fileBBD file
The BBD file manages the file locations of optimized hardware netlists for the black-box sections of the design
The BBD format is a look-up table chart that lists netlist files The first line is the header of the look-up
table The last column of the table must be the
FILES column Each file is listed with the file extension
of the hardware implementation netlist
BBD file - exampleBBD file - exampleC_FAMILY C_BUS_CONFIG FILESvirtex 1 virtex/ip1.edfvirtex 2 virtex/ip2.edfspartan2 1 virtex/ip1.edfspartan2 2 virtex/ip2.edfvirtexe 1 virtex/ip1.edfvirtexe 2 virtex/ip2.edfspartan2e 1 virtex/ip1.edfspartan2e 2 virtex/ip2.edfvirtex2 1 virtex2/ip1.edfvirtex2 2 virtex2/ip2.edfvirtex2p 1 virtex2/ip1.edfvirtex2p 2 virtex2/ip2.edf
Adding user logicAdding user logic
Adding user Adding user logiclogic
Standalone Standalone corecore
Master / slave Master / slave bus corebus core
OPB OPB slaveslave
PLB PLB master-master-
slaveslave
PLB PLB slaveslave
Bus core architectureBus core architecture To simplify the process of attaching a
user core to a CoreConnect bus, the user core can make use of a portable, predesigned bus interface (called the IP Interface, IPIF) that takes care of the bus interface signals, bus protocol, and other interface issues
The IPIF presents an interface to the user logic called the IP InterConnect (IPIC)
User logic is designed with an IPIC interface to make use of the IPIF bus attachment and other services
User logic that is designed with an IPIC has the advantage that it is portable and can be easily reused on different processor buses by changing the IPIF to which it is attached
3 methods of adding user 3 methods of adding user logiclogic
Other logic Other logic added to added to FPGA via FPGA via external tool external tool (for example, (for example, ISE)ISE)
IPIC ports IPIC ports are defined are defined as external as external in in embedded embedded systemsystem
User core User core fully added fully added to embedded to embedded systemsystem
This method is preferredThis method is preferred
OPB IPIF architectureOPB IPIF architecture
Optional features are marked in redOptional features are marked in red
PLB IPIF architecturePLB IPIF architecture
Main IPIC signals – slave Main IPIC signals – slave interfaceinterface
Bus2IP_AddrBus2IP_Addr – address bus from the IPIF to the user logic (the – address bus from the IPIF to the user logic (the same width as host address bus)same width as host address bus)
Bus2IP_BEBus2IP_BE – a bus of BE qualifiers from the IPIF to user logic. A – a bus of BE qualifiers from the IPIF to user logic. A bit in the. Bus2IP_BE set to ‘1’ indicates that the associated bit in the. Bus2IP_BE set to ‘1’ indicates that the associated byte lane contains valid databyte lane contains valid data
Bus2IP_ClkBus2IP_Clk – clock input to the user logic (same as OPB_clk or – clock input to the user logic (same as OPB_clk or PLB_clk)PLB_clk)
Bus2IP_CSBus2IP_CS – a bus of chip select signals from IPIF to user logic. – a bus of chip select signals from IPIF to user logic. It indicates a decode within a block of addresses (address It indicates a decode within a block of addresses (address space)space)
Bus2IP_CEBus2IP_CE - a bus of chip enable signals from IPIF to user logic. - a bus of chip enable signals from IPIF to user logic. Indicates a decode of a particular register or address within the Indicates a decode of a particular register or address within the block of addressesblock of addresses
Bus2IP_RdCEBus2IP_RdCE – the same as Bus2IP_CE during read transaction – the same as Bus2IP_CE during read transaction Bus2IP_WrCEBus2IP_WrCE – the same as Bus2IP_CE during write transaction – the same as Bus2IP_CE during write transaction Bus2IP_DataBus2IP_Data - this is the data bus from the IPIF to the user - this is the data bus from the IPIF to the user
logic; it is used for both master and slave transactions (the logic; it is used for both master and slave transactions (the same width as the host bus data bus)same width as the host bus data bus)
Bus2IP_RNWBus2IP_RNW - indicates the transaction type (read or write). - indicates the transaction type (read or write). Bus2IP_RNW = 1 indicates a read transaction and Bus2IP_RNW Bus2IP_RNW = 1 indicates a read transaction and Bus2IP_RNW = 0 indicates a write transaction.= 0 indicates a write transaction.
Bus2IP_BurstBus2IP_Burst – this signal from the IPIF to the user logic – this signal from the IPIF to the user logic indicates that the current transaction is a burst transactionindicates that the current transaction is a burst transaction
Main IPIC signals – slave interface Main IPIC signals – slave interface (2)(2)
IP2Bus_Ack (OPB), IP2Bus_RdAck, IP2Bus_WrAck (PLB) - These signals provide the read/write acknowledgement from the user logic to the IPIF. For writes, it indicates the data has been taken by the user logic. For reads, it indicates that valid data is available
IP2Bus_Data - this is the data bus from the IPIF to the user logic; it is used for both master and slave transactions (the same width as the host bus data bus)
IP2Bus_Error - this signal from the user logic to the IPIF indicates an error has occurred during the current transaction. It is valid when IP2Bus_Ack is asserted.
IP2Bus_Intr (OPB), IP2Bus_IntrEvent (PLB) - output from the user logic to the IPIF that consists of interrupt event signals to be detected and latched inside the IPIF.
IP2Bus_Retry - response from the user logic to the IPIF that indicates the currently requested transaction cannot be completed at this time and that the requesting master should retry the operation
IP2Bus_ToutSup – this signal must be asserted by the user logic whenever its acknowledgement or retry response will take longer than 8 clock cycles.
Slave read – transaction Slave read – transaction exampleexample
Main IPIC signals – master Main IPIC signals – master interfaceinterface
Bus2IP_MstError - signal from the IPIF to the user logic indicates whether the transfer has an error
Bus2IP_MstLastAck - a one-cycle acknowledgement of a master transaction from the IPIF to the user logic. A transaction may consist of multiple transfers (burst transaction); Bus2IP_MstLastAck will always accompany the last Bus2IP_MstAck for the transaction.
Bus2IP_MstAck (OPB), Bus2IP_MstRdAck, Bus2IP_MstWrAck (PLB) - a one-cycle acknowledgement of a master transfer from the IPIF to the user logic. For writes it indicates that the IPIF has accepted the current data and is ready for the next data; for reads it indicates that valid data is present on the Bus2IP_Data bus.
Bus2IP_MstRetry - a one-cycle alternative completion signal to Bus2IP_MstLastAck. It indicates that the requested transaction could not be performed but may succeed if retried;
Bus2IP_MstTimeOut - (from the IPIF to the user logic) is a one-cycle alternative completion signal to Bus2IP_MstLastAck. It indicates that the requested transaction could not be performed within the timeout interval associated with the host bus.
Main IPIC signals – master Main IPIC signals – master interface (2)interface (2)
IP2Bus_Addr - an output from the user logic to the IPIF. It is the address bus for the current master transaction. It is valid when IP2Bus_Req is active.
IP2Bus_MstBE - a bus of Byte Enables qualifiers from the user logic to the IPIF for a master transaction. A bit in the IP2Bus_MstBE set to ‘1’ indicates that the associated byte lane contains valid data
IP2Bus_MstBurst qualifier from the user logic to the IPIC indicates the master transaction is a burst operation.
IP2Bus_MstBusLock qualifier from the user logic to the IPIC indicates the master is requesting that the host bus be locked until IP2Bus_MstBusLock is deasserted
IP2Bus_MstNum (OPB Only) - indicates the burst length for burst transfers. The number of transfers for the burst is IP2Bus_MstNum+1, so that a value of 0000 indicates a burst length of one, and a value of 1111 indicates a burst length of 16
IP2Bus_MstReq (OPB Only) - this signal from the user logic to the IPIF indicates that the user logic is requesting a master transaction
IP2Bus_MstRNW(OPB Only) - an input to the IPIF from the user logic that indicates the transaction type (read or write). IP2Bus_MstRNW = 1 indicates a read transaction and IP2Bus_MstRNW = 0 indicates a write transaction
IP2Bus_MstRdReq, IP2Bus_MstWrReq(PLB Only) - inputs to the IPIF from the user logic that indicates that the user logic is requesting a master transaction (read or write)
IP2IP_Addr - an output from the user logic that indicates the local device address for the master transaction. This address will be the source for a master write transaction and the sink for a master read transaction
Master read – transaction Master read – transaction exampleexample
Adding cores using “Import Adding cores using “Import peripheral Wizard…”peripheral Wizard…”
Adding cores using “Import Adding cores using “Import peripheral Wizard…”peripheral Wizard…”
Creates templates with Creates templates with required bus interfacerequired bus interface User logic has to be User logic has to be implemented laterimplemented later
Imports fully implemented Imports fully implemented peripheral peripheral Peripheral need to have Peripheral need to have ports and parameters that ports and parameters that conform to the conventions conform to the conventions required by EDKrequired by EDK
Creating templates for new Creating templates for new corecore
Shared directory, peripheral Shared directory, peripheral stored there can be used by stored there can be used by multiple projectsmultiple projects
Peripheral can be used only Peripheral can be used only by current projectby current project
Creating templates for new Creating templates for new corecore
Version managementVersion management
Name of the Name of the peripheral must be peripheral must be the same as the the same as the name of the top-level name of the top-level entityentity
Creating templates for new Creating templates for new corecore
PLB slave and master-slave PLB slave and master-slave interfaces are supportedinterfaces are supported
OPB slave only interface is supportedOPB slave only interface is supported
Choose required core componentsChoose required core components
For each component chosen, For each component chosen, additional windows will open for additional windows will open for configurationconfiguration
Creating templates for new Creating templates for new corecore According to chosen components, some signals are already According to chosen components, some signals are already connectedconnected
Additional signals can be connected if neededAdditional signals can be connected if needed
Importing existing peripheralImporting existing peripheral
Shared directory, peripheral Shared directory, peripheral stored there can be used by stored there can be used by multiple projectsmultiple projects
Peripheral can be used only Peripheral can be used only by current projectby current project
Importing existing peripheralImporting existing peripheral
Version managementVersion management
Name of the Name of the peripheral must be peripheral must be the same as the the same as the name of the top-level name of the top-level entityentity
Importing existing peripheralImporting existing peripheral
Three types of files can be added:Three types of files can be added:
Importing existing peripheralImporting existing peripheral
MPD and PAO files are MPD and PAO files are created during importing created during importing core. Existing MPD and core. Existing MPD and PAO can be usedPAO can be used
Importing existing peripheralImporting existing peripheral
In this stage, syntax of HDL code In this stage, syntax of HDL code and library dependencies are and library dependencies are checked. Error messages can be checked. Error messages can be reportedreported
Importing existing peripheralImporting existing peripheral Bus interface has to be Bus interface has to be already implemented in already implemented in imported peripheralimported peripheral
MicroBlaze onlyMicroBlaze onlyPower PC onlyPower PC only
If the names of user core ports follow If the names of user core ports follow IPIC standard names, they are IPIC standard names, they are connected automaticallyconnected automatically
Else, they have to be indicated Else, they have to be indicated explicitlyexplicitly
Importing existing peripheralImporting existing peripheral
Interrupt ports have to Interrupt ports have to indicated to give indicated to give possibility to connect them possibility to connect them later to interrupt controllerlater to interrupt controller
Importing existing peripheralImporting existing peripheralDefining peripheral Defining peripheral parameters (attributes) parameters (attributes) and port parameters …and port parameters …
Importing existing peripheralImporting existing peripheral
Importing existing peripheralImporting existing peripheralSummary:Summary:
Logical libraryLogical library : abcd_v1_00_a: abcd_v1_00_a
VersionVersion : 1.00.a: 1.00.a
Bus interface(s)Bus interface(s) : None: None
The following sub-directories will be created in the The following sub-directories will be created in the pcores repository in your project:pcores repository in your project:
- abcd_v1_00_a\data- abcd_v1_00_a\data
- abcd_v1_00_a\hdl- abcd_v1_00_a\hdl
- abcd_v1_00_a\hdl\vhdl- abcd_v1_00_a\hdl\vhdl
- abcd_v1_00_a\netlist- abcd_v1_00_a\netlist
The following HDL source files will be copied into the The following HDL source files will be copied into the abcd_v1_00_a\hdl\vhdl directory:abcd_v1_00_a\hdl\vhdl directory:
- my_abcd.vhd- my_abcd.vhd
The following files will be created under the The following files will be created under the abcd_v1_00_a\data directory:abcd_v1_00_a\data directory:
- abcd_v2_1_0.mpd- abcd_v2_1_0.mpd
- abcd_v2_1_0.pao- abcd_v2_1_0.pao
- abcd_v2_1_0.bbd- abcd_v2_1_0.bbd
The following netlist files will be copied into the The following netlist files will be copied into the abcd_v1_00_a\netlist directory:abcd_v1_00_a\netlist directory:
- my_fifo.edn- my_fifo.edn
Thank you for using this Import Peripheral Wizard!Thank you for using this Import Peripheral Wizard!
Adding new core to the Adding new core to the projectproject
Intro to JTAGIntro to JTAG
What is JTAG ?What is JTAG ?
JJointoint TTestest AActionction GGrouproup
JTAG is IEEE 1149 standardJTAG is IEEE 1149 standard This standard defines 5-pin serial protocol for This standard defines 5-pin serial protocol for
accessing and controlling signal-levels on the accessing and controlling signal-levels on the pins of a digital circuit, and has some pins of a digital circuit, and has some extensions for testing the internal circuitry on extensions for testing the internal circuitry on the chip itselfthe chip itself
Appendix B
JTAG architectureJTAG architecture
C0 C1 C2 C3 C4
Boundary scan register (BSR)
BSR read and write BSR read and write operations take place operations take place at the same time, in at the same time, in serial fashion, with serial fashion, with the new value shifted the new value shifted in from TDI, while the in from TDI, while the previous value is previous value is shifted out from TDOshifted out from TDO
C0 and C3 are input C0 and C3 are input cellscells
C1 and C4 are C1 and C4 are output cellsoutput cells
C2 is enable cellC2 is enable cell
O
I
BI
Appendix B
JTAG interface signalsJTAG interface signals TRSTTRST is the Test-ReSeT input which initializes and is the Test-ReSeT input which initializes and
disables the test interfacedisables the test interface TCKTCK is the Test-ClocK input which controls the is the Test-ClocK input which controls the
timing of the test independently from any system timing of the test independently from any system clocks. TCK is pulsed by the equipment controlling clocks. TCK is pulsed by the equipment controlling the test and not by the tested device. It can be the test and not by the tested device. It can be pulsed at any frequency up to one half of the pulsed at any frequency up to one half of the PowerPC core clockPowerPC core clock
TMSTMS is the Test Mode Select input which controls is the Test Mode Select input which controls the transitions of the test interface state machinethe transitions of the test interface state machine
TDITDI is the Test Data Input line, which supplies the is the Test Data Input line, which supplies the data to the JTAG registers (BSR, Instruction data to the JTAG registers (BSR, Instruction Register etc.)Register etc.)
TDOTDO is the Test Data Output line, which is used to is the Test Data Output line, which is used to serially output the data from the JTAG registers to serially output the data from the JTAG registers to the equipment controlling the testthe equipment controlling the test
Appendix B
JTAG registersJTAG registers Instruction Register (IRInstruction Register (IR) – contains instruction ) – contains instruction
which specifies the type of test to be performed, which specifies the type of test to be performed, and the Data Register to be used during the testand the Data Register to be used during the test
Data Registers:Data Registers: The Device ID register (IDR)The Device ID register (IDR) – reads out an – reads out an
identification number which is hardwired into the chipidentification number which is hardwired into the chip The Bypass register (BR)The Bypass register (BR) – is a 1-cell pass-through – is a 1-cell pass-through
register which connects the TDI to the TDO with 1-register which connects the TDI to the TDO with 1-clock delay to give test equipment easy access to clock delay to give test equipment easy access to another device in the test chain on the same boardanother device in the test chain on the same board
The Boundary Scan register (BSR)The Boundary Scan register (BSR) – has already been – has already been described, intercepts all the signals between the core described, intercepts all the signals between the core logic and the pinslogic and the pins
In modern chips not only pins but also internal In modern chips not only pins but also internal registers and memory cells can be included in registers and memory cells can be included in the BSR (for example, FPGA configuration the BSR (for example, FPGA configuration memory)memory)
Appendix B
How does it work?How does it work?
Test logic reset
Run test idle
Select IR chain
Capture IR
Shift IR
Update IR
Select DR chain
Capture DR
Shift DR
Update DR
N times
N times
IR or DR chain is IR or DR chain is selected by TMS selected by TMS inputinput
Data Register is Data Register is selected by selected by contents of IR contents of IR registerregister
Appendix B
Multi device debugMulti device debug
Number of devices on the same board Number of devices on the same board can be connected to single test chain can be connected to single test chain
1st device 2nd device
TDI
TRSTTCKTMSTDO
TDI=TDI1 TDO1=TDI2 TDO2=TDO
JTAG port
Appendix B
Debug tools for Debug tools for Virtex II ProVirtex II Pro
Debug supportDebug support The GNU Debugger (GDB)The GNU Debugger (GDB) runs runs
on the host machine and on the host machine and interfaces to the Xilinx interfaces to the Xilinx Microprocessor Debugger (XMD) Microprocessor Debugger (XMD) via TCPvia TCP
XMDXMD runs on the host machine runs on the host machine and interfaces to the PowerPC and interfaces to the PowerPC target via JTAG interfacetarget via JTAG interface
ChipScope ProChipScope Pro software runs on software runs on the host machine and interfaces the host machine and interfaces to the FPGA (not necessarily to to the FPGA (not necessarily to PowerPC) via JTAG interface)PowerPC) via JTAG interface)
Vision ProbeVision Probe hardware debugger hardware debugger interfaces to the PowerPC target interfaces to the PowerPC target via on-board debug port (JTAG via on-board debug port (JTAG compatible) and to the host compatible) and to the host machine software debugger machine software debugger SingleStepSingleStep via parallel port via parallel port
GDB
XMDVision Probe
PowerPC
Virtex II Pro
Target board
Chip Scope
Pro
JTAG
TCP
Single Step
Parallel
HW design for debug HW design for debug sessionsession
Both Virtex II Pro and PowerPC have its own JTAG connectionBoth Virtex II Pro and PowerPC have its own JTAG connection The system must contain a JTAG_CNTL peripheral for debugging The system must contain a JTAG_CNTL peripheral for debugging
PowerPC through FPGA JTAG pinsPowerPC through FPGA JTAG pins PPC JTAG port may alternatively be routed to FPGA user I/OPPC JTAG port may alternatively be routed to FPGA user I/O
MicroBlaze will always be debugged via FPGA JTAG port MicroBlaze will always be debugged via FPGA JTAG port
FPGA JTAG or
FPGA I/O
This peripheral connects PowerPC JTAG pins to FPGA JTAG port and also connects correctly DEBUGHALT PowerPC port which is needed to stop processor from fetching and executing instructions
Using debuggersUsing debuggers
The The Vision ProbeVision Probe hardware + hardware + SingleStepSingleStep software debuggers are typically used for software debuggers are typically used for debugging of large amounts of software, such debugging of large amounts of software, such as RTOS, so we will find a little use in themas RTOS, so we will find a little use in them
The The GDBGDB debugger still has many bugs, it is debugger still has many bugs, it is more preferably not to use itmore preferably not to use it
We will mostly use We will mostly use XMDXMD and and ChipScope ProChipScope Pro XMD is the command line, Unix-like debugger, XMD is the command line, Unix-like debugger,
preferable for software debugpreferable for software debug ChipScope Pro is scope-like tool, which gives a ChipScope Pro is scope-like tool, which gives a
possibility to analyze external or internal signals of possibility to analyze external or internal signals of the design in run-timethe design in run-time
XMD debuggerXMD debugger
XMD debuggerXMD debugger All PowerPC related commands start with “x”All PowerPC related commands start with “x” Useful XMD commands:Useful XMD commands:
ppcconnect – establish connection between debugger and ppcconnect – establish connection between debugger and PowerPC targetPowerPC target
xdownload – download elf file to the target (we will use this xdownload – download elf file to the target (we will use this command to download code to external memory)command to download code to external memory)
xreset – perform reset to the targetxreset – perform reset to the target xcontinue – run target from certain addressxcontinue – run target from certain address xrreg / xwreg – read / write PowerPC registersxrreg / xwreg – read / write PowerPC registers xrmem / xwmem – read / write memoryxrmem / xwmem – read / write memory and many other …and many other …
There are similar MicroBlaze commands without “x”There are similar MicroBlaze commands without “x” For connect to MicroBlaze target we will use “mbconnect”For connect to MicroBlaze target we will use “mbconnect”
ChipScope Pro ChipScope Pro
ChipScope Pro ChipScope Pro ChipScope Pro consists of 3 different programs:ChipScope Pro consists of 3 different programs:
ChipScope Core generatorChipScope Core generator Creates configurable cores of Integrated Bus Analyzer (IBA)Creates configurable cores of Integrated Bus Analyzer (IBA)
ChipScope Core inserterChipScope Core inserter Inserts created core to the designInserts created core to the design
ChipScope AnalizerChipScope Analizer Establishes connection to IBA core inside the design and presents Establishes connection to IBA core inside the design and presents
signals activitysignals activity IBA is a core that can be connected to any signal existing in the IBA is a core that can be connected to any signal existing in the
designdesign IBA samples connected signals when trigger condition occursIBA samples connected signals when trigger condition occurs
Number of samples, trigger signals and conditions are simply configuredNumber of samples, trigger signals and conditions are simply configured Sampled data is saved to BRAMs and later presented to the userSampled data is saved to BRAMs and later presented to the user
ChipScope Pro can be used in any design, regardless of existing ChipScope Pro can be used in any design, regardless of existing PowerPC core in the designPowerPC core in the design
ChipScope Pro system block ChipScope Pro system block diagramdiagram
IIntegratedntegrated
CONCONtrollertroller
IIntegrated ntegrated LLogic ogic AAnalyzer (up to nalyzer (up to 15)15)
Chip Scope Pro design flowChip Scope Pro design flow
Simpler Simpler and and preferrepreferredd
Chip Scope Pro design flowChip Scope Pro design flowSynthesize Synthesize
design using EDK design using EDK or external toolor external tool
Create ILA and Create ILA and insert it to insert it to
designdesign
using Chip Scope using Chip Scope Pro InserterPro Inserter
project.edf or project.edf or project.ngcproject.ngc
ILA ILA definitionsdefinitions
project.nproject.ngogo
P&R new design P&R new design with Project with Project NavigatorNavigator
project.biproject.bitt
Return to EDK to Return to EDK to update bitstream update bitstream
with softwarewith software
Update Update bitstream with bitstream with software from software from
iMPACT iMPACT (download tool)(download tool)
Download Download bitsream to bitsream to the boardthe board
Run Chip Run Chip Scope Pro Scope Pro
Analyzer to Analyzer to analyze designanalyze design
Start with HDL Start with HDL source files and source files and
system description system description (MHS, MPD)(MHS, MPD)
Chip Scope Pro design flowChip Scope Pro design flow
Your netlistYour netlist
Generated netlistGenerated netlist
Target deviceTarget device
SRL-Set Reset LatchSRL-Set Reset Latch
RPM – Relationally placed macroRPM – Relationally placed macro
Chip Scope Pro design flowChip Scope Pro design flow
Use it only if you don’t have enough global buffers Use it only if you don’t have enough global buffers for your logic (introduces skew)for your logic (introduces skew)
Chip Scope Pro design flowChip Scope Pro design flow Up to 16 trigger ports Trigger width up to 256 A match unit is a comparator that is connected to a trigger port and is used to detect events on that trigger port. The results of one or more match units are combined together to form the overall trigger condition event that is used to control the capturing of data Up to 16 match units for each trigger and overall Trigger Sequencer allows building state machine based on all match units so that trigger condition will satisfied after machine passes all its states
Chip Scope Pro design flowChip Scope Pro design flow
Check that total number of BRAMs used Check that total number of BRAMs used by Chip Scope and by you doesn’t by Chip Scope and by you doesn’t exceed number of BRAMs in FPGAexceed number of BRAMs in FPGA
Check it , if you want to Check it , if you want to sample triggers onlysample triggers only
Chip Scope Pro design flowChip Scope Pro design flow
Double click on one of Double click on one of them to connect them to connect signalssignals
Chip Scope Pro design flowChip Scope Pro design flow
DesigDesign netsn nets
Press here to Press here to connect signalsconnect signals
Chip Scope Pro design flowChip Scope Pro design flow When all When all signals are signals are connected, core connected, core insertion is insertion is performedperformed New netlist is New netlist is createdcreated Bitstream Bitstream generation can be generation can be performed in performed in Project Navigator Project Navigator
Finishing Chip Scope Pro design Finishing Chip Scope Pro design flowflow
Open Project Navigator, create new project:Open Project Navigator, create new project:
Finishing Chip Scope Pro design Finishing Chip Scope Pro design flowflow
Important: Important: Don’t select Don’t select them!them!
File created by File created by Chip Scope Pro Chip Scope Pro inserterinserter
……
Add files…Add files…
Finishing Chip Scope Pro design Finishing Chip Scope Pro design flowflow
BMM file is required for generating memoryBMM file is required for generating memory
Double click to generate Double click to generate bitstreambitstream
Finishing Chip Scope Pro design Finishing Chip Scope Pro design flowflow When starting, IMPACT will display wizard which will guide When starting, IMPACT will display wizard which will guide
you through the programming processyou through the programming process
Attention: download cable should be connected and board power on before Attention: download cable should be connected and board power on before running IMPACT !running IMPACT !If there are no problems with JTAG, 3 devices are recognized on the board:If there are no problems with JTAG, 3 devices are recognized on the board:
First two devices are on-board First two devices are on-board PROMS, we are not interested in PROMS, we are not interested in them (press Cancel twice)them (press Cancel twice)Virtex II PRO is the third in the JTAG Virtex II PRO is the third in the JTAG chain of the boardchain of the board
Finishing Chip Scope Pro design Finishing Chip Scope Pro design flowflow Right click on Virtex II PRO and select “Assign new configuration file”Right click on Virtex II PRO and select “Assign new configuration file”
Select required “.bit” file Select required “.bit” file and press “Open”and press “Open”Right click on Virtex II PRO Right click on Virtex II PRO and select “Program”and select “Program”Press “OK” – device will Press “OK” – device will start programming:start programming:
Add here updated “.bmm” Add here updated “.bmm” and “.elf” filesand “.elf” files
Using Chip Scope Pro Using Chip Scope Pro AnalyzerAnalyzerInvocation:Invocation:
Using Chip Scope Pro Using Chip Scope Pro AnalyzerAnalyzerInvocation:Invocation:
Open analyzer after Open analyzer after downloading bitstream downloading bitstream to the boardto the board Close iMPACT before Close iMPACT before accessing JTAG from accessing JTAG from analyzer !analyzer !
Press here to Press here to connect to connect to JTAG chainJTAG chain
Using Chip Scope Pro Using Chip Scope Pro AnalyzerAnalyzer Analyzer main Analyzer main window after window after connecting to connecting to JTAGJTAG
Signals list Signals list (here names of (here names of signals can be signals can be changed)changed)
Waveform window (two Waveform window (two markers)markers)
Messages & WarningsMessages & Warnings
Debug Debug configurationconfiguration
Trigger settingsTrigger settings
Using Chip Scope Pro Using Chip Scope Pro AnalyzerAnalyzer
Define here function (==, <>, < , >) of match unit and its valueDefine here function (==, <>, < , >) of match unit and its value
Define here trigger Define here trigger conditionconditionVery limited possibilities:Very limited possibilities:
All match units can be All match units can be either ANDed or ORed, either ANDed or ORed, with additional with additional possibility of NOT on possibility of NOT on whole expression whole expression
Using Chip Scope Pro Using Chip Scope Pro AnalyzerAnalyzer
Using level sequencer:Using level sequencer:
Using Chip Scope Pro Using Chip Scope Pro AnalyzerAnalyzer
Capture setting tab:Capture setting tab:
There are two modes of capturing:There are two modes of capturing: WindowWindow N SamplesN Samples
In window mode, once trigger condition satisfied, data is In window mode, once trigger condition satisfied, data is sampled for defined number of cycles (512, 1024 etc.)sampled for defined number of cycles (512, 1024 etc.) In N samples mode, each time trigger condition is satisfied, In N samples mode, each time trigger condition is satisfied, data is sampled for N cyclesdata is sampled for N cycles
Total number of samples, however, cannot exceed Total number of samples, however, cannot exceed defined previously depthdefined previously depth
Using Chip Scope Pro Using Chip Scope Pro AnalyzerAnalyzer
Signals can be bundled to bus to Signals can be bundled to bus to simplify waveform view:simplify waveform view:
Start capturing:Start capturing:
Capture Capture from from now now accordinaccording to g to trigger trigger conditioconditionn
Stop Stop capturincapturingg
UnconditionUnconditional captureal capture