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www.vlsi.itu.edu.tr 19.04.23
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Very Large Scale Integration II - VLSI II
SystemC
Gürer Özbek
ITU VLSI Laboratories
Istanbul Technical University
www.vlsi.itu.edu.tr
Outline
Design of Big Digital Systems
SystemC
SystemC Fundamentals
Coding Examples
Conclusion
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Design of Big Digital Systems
Old Way– Hardware-like C/C++
Model– Simulated and– Given to Hardware
Designers
– Hardware Designers write VHDL/Verilog Model
– Simulated and compared with C model
– Synthesized
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Design of Big Digital Systems
Drawbacks of Old Way– Different Flow– Different Library
– System Designers don’t know VHDL/Verilog
– Hardware Designers don’t understand system design
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Design of Big Digital Systems
Desired Way– Single Model
– Suitable for System-Level Modeling
– Synthesizable
– No manual conversion
– and Synopsys Creates SystemC
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SystemC
What – Subset of C++: Class library
Importance– Enables hardware and software co-design
Advantages– More hardware-like wrt C/C++
– More system-level wrt VHDL/Verilog
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SystemC
Advantages (Cont’d)– Open Source
– Runs on both C compilers & (most) HDL tools
– Many abstraction levels from system level to cycle-accurate RTL
– Rich set of data types and specifications
– Brings new concepts to system-level modeling: Powersim
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SystemC
Fundamentals– Design Entity: SC_MODULE– Ports– Signals– Module Instantiation– Processes– Clocks– Data Types– Operators
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SystemC Fundamentals
Design Entity: SC_MODULE– Class in C++
– Building blocks of the design
– Divide and Conquer
– Like Module in Verilog
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SystemC Fundamentals
Design Entity: SC_MODULE
SC_MODULE(module_name){
// Ports declaration // Signals declaration// Module constructor : SC_CTOR// Process constructors and sensitivity list// SC_METHOD// Sub-Modules creation and port mappings// Signals initialization// Process definition
};
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SystemC Fundamentals
Ports– Defines interface of the module
SC_MODULE(module_name){
sc_in<data_type> in1, in2;sc_out<data_type> out1, out2;sc_inout<data_type> inout1, inout2;
//…};
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SystemC Fundamentals
Signals– Carries information within a module
SC_MODULE(module_name){
//ports declarationsc_signal<data_type> s1,s2,s3;
SC_CTOR(module_name){
//module instances that connect to signals}
};
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SystemC Fundamentals
Module Instantiation – Submodules that called in a module
SC_MODULE(module_name){
//ports declaration//signal decletationSC_CTOR(module_name){
Module_Type submodule1 (“label1”);Module_Type submodule2 (“label2”);
submodule1.x(in1);submodule1.y(s1); //equivalent to submodule1 << in1 << s1;submodule2.x(s1);submodule2.y(out1); //equivalent to submodule2 << s1 << out1;
}};
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SystemC Fundamentals
Processes– Functions of the Classes
– Defines Functionality
– Three types: SC_METHOD (Combinational)
SC_THREAD (Testing)
SC_CTHREAD (Sequential)
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SystemC Fundamentals
METHOD Processes– Models Combinational Logic
– Triggered with what it is sensitive for
– Cannot store data between invocations
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SC_MODULE(module_name){
//ports declaration//signal declarationSC_CTOR(module_name){
SC_METHOD (process_name);sensitive << in1 << in2 << in3;
}//…Void process_name(){
out.write = in1.read() + in2.read() - in3.read();}
};
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SystemC Fundamentals
THREAD Processes– Models functionality of
testbench– Triggered with what it is
sensitive for– Stores data between
invocations– Suspendable with wait() – Reactivated with input
change
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SC_MODULE(module_name){
//ports declaration//signal declarationSC_CTOR(module_name){
SC_THREAD (process_name);sensitive << in; // or
nothing}//…Void process_name(){
a_t = 12;b_t = 15;c_t = 11;wait();//...
}};
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SystemC Fundamentals
CTHREAD Processes– Models functionality of
sequential circuit– Triggered with a clock edge– Stores data between
invocations– Suspendable with wait() – Reactivated with a clock
edge
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SC_MODULE(module_name){
//ports declaration//signal declarationSC_CTOR(module_name){
SC_CTHREAD (process_name, clock_name.pos());}//…Void process_name(){
out.write = in.read();out_n.write = ~in.read();
} };
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SystemC Fundamentals
Clocks– Triggers SC_CTHREAD processes
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sc_clock clock_name(“clock_label”, period, duty_ratio, delay, initial_value);
2 12 22 32 42
sc_clock clk_1(“clk_1”, 20, 0.5, 2, true)
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SystemC Fundamentals
Data Types– sc_bit, sc_logic: 0/1 0/1/X/Z– sc_int<n>, sc_uint<n>: 1-64 bits– sc_bigint<n>, sc_biguint<n>: arbitrary size (>64)– sc_fixed, sc_ufixed: fixed point– sc_bv, sc_lv: vector form
– And All C/C++ Data Types
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Bitwise & (and) | (or) ^ (xor) ~ (not)
Assignment = &= |= ^=
Equality == !=
SystemC Fundamentals
Operators for bits & logic
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Bitwise ~ & | ^ >> <<Arithmetics + - * / %Assignement = += -= *= /= %= &= |= ^=Equality == !=Relational < <= > > =Auto-Inc/Dec ++ --Bit selection [x] ex: mybit = myint[7]
Part select range() ex: myrange = myint.range(7,4)
Concatenation (,) ex: intc = (inta, intb);
SystemC Fundamentals
Operators for fixed point types
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SystemC Fundamentals
Operators for vectors– Just assign “=”
To a value To/from integer To/from sc_bv and sc_lv
– Functions Reduction: and_reduction() or_reduction() xor_reduction() Conversion: to_string()
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Coding Examples
sc_bit x;sc_bv<8> y;sc_bv<16> z;sc_bv<64> databus;sc_logic result;
x = y[6];
y = z.range(0,7);
result = databus.or_reduce();
cout << “bus = ” << databus.to_string();
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Coding Examples
1-bit adder
#include "systemc.h"
SC_MODULE (BIT_ADDER)
{
sc_in<sc_logic> a, b, cin;
sc_out<sc_logic> sum, cout;
SC_CTOR(BIT_ADDER)
{
SC_METHOD (process);
sensitive << a << b << cin;
}
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void process()
{
sc_logic aANDb,aXORb,cinANDaXORb;
aANDb = a.read() & b.read();
aXORb = a.read() ^ b.read();
cinANDaXORb = cin.read() & aXORb;
sum = aXORb ^ cin.read();
cout = aANDb | cinANDaXORb;
}
};
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Coding Examples
Testbench
#include "systemc.h"
SC_MODULE (testbench)
{ sc_out<sc_logic> A_p,B_p,CIN_p;
sc_in<sc_logic> SUM_p,COUT_p;
SC_CTOR (testbench)
{
SC_THREAD (process);
}
void print()
{
cout << "At time " << sc_time_stamp() << "::";
cout << "(a,b,carry_in): ";
cout << A_p.read() << B_p.read() << CIN_p.read();
cout << " (sum,carry_out): " << SUM_p.read();
cout << COUT_p.read() << endl;
}
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void process()
{
//Case 1
A_p = SC_LOGIC_0;
B_p = SC_LOGIC_0;
CIN_p = SC_LOGIC_0;
wait (5, SC_NS); //wait to set
assert ( SUM_p == SC_LOGIC_0 );
assert ( COUT_p == SC_LOGIC_0 );
wait (10, SC_NS);
print();
//Case 2
//…
print();
sc_stop();
}
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Coding Examples
Main function
#include "add1.cpp"
#include "add1_tst.cpp"
int sc_main(int argc, char* argv[])
{
sc_signal<sc_logic> A_s,B_s,CIN_s,SUM_s,COUT_s;
BIT_ADDER adder1("BitAdder1");
adder1 << A_s << B_s << CIN_s << SUM_s << COUT_s;
testbench test1("TestBench1");
test1 << A_s << B_s << CIN_s << SUM_s << COUT_s;
sc_start(200,SC_NS);
return(0);
}
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Coding Examples
Simulation OutputAt time 15 ns::(a,b,carry_in): 000 (sum,carry_out): 00
At time 30 ns::(a,b,carry_in): 001 (sum,carry_out): 10
At time 45 ns::(a,b,carry_in): 101 (sum,carry_out): 01
…
OR,
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Summary
Is a C++ Class Library Brings C/C++ and VHDL/Verilog together Eases Designing Process
Less people use it Still more work to do Better tools are necessary
We will wait and see…
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References
Stephen A. Edwards, (2001), SystemC, retrieved from: www.cs.columbia.edu/~sedwards/classes/2001/w4995-02/presentations/systemc.ppt
Silvio Veloso, SystemC Tutorial, retrieved from: www.weblearn.hs-bremen.de/risse/RST/WS03/SystemC/Tutorial.ppt
John Moondanos, SystemC Tutorial, retrived from: http://embedded.eecs.berkeley.edu/research/hsc/class/ee249/lectures/l10-SystemC.pdf
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References
Giammarini, M.; Conti, M.; Orcioni, S.; , "System-level energy estimation with Powersim," Electronics, Circuits and Systems (ICECS), 2011 18th IEEE International Conference on , vol., no., pp.723-726, 11-14 Dec. 2011doi: 10.1109/ICECS.2011.6122376
Vahid, F., SystemC Simulation Tutorial. retrieved from http://www.cs.ucr.edu/~vahid/sproj/SystemCLab/lab1a.htm
VHDL to SystemC Converter. retrieved from http://www.ht-lab.com/freeutils/vh2sc/vh2sc.html
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