Post on 23-Feb-2016
description
ECEN 475 3.1
ECEN475 Introduction to VLSI System Design
Verilog HDL
ECEN 475 2.2
HDLs Hardware Description Languages
Widely used in logic design Verilog and VHDL
Describe hardware using code Document logic functions Simulate logic before building Synthesize code into gates and layout
Requires a library of standard cells
ECEN 475 2.3
Module portsModule name
Verilog keywords
Taste of Verilog
module Add_half ( sum, c_out, a, b ); input a, b;
output sum, c_out;wire c_out_bar;
xor (sum, a, b);nand (c_out_bar, a, b);not (c_out, c_out_bar);
endmodule
Declaration of port modes
Declaration of internal signal
Instantiation of primitive gates
c_out
ab sum
c_out_bar
ECEN 475 2.4
Taste of Verilog
module Add_full ( sum, c_out, a, b, c_in ); input a, b, c_in;
output sum, c_out;
Adder_half (s1, c1, a, b);Adder_half (sum, c2, s1, c_in);
OR (c_out, c1, c2);endmodule
ECEN 475 2.5
Behavioral Descriptionmodule Add_half ( sum, c_out, a, b ); input a, b;
output sum, c_out;reg sum, c_out;always @ ( a or b ) begin
sum = a ^ b; // Exclusive orc_out = a & b; // And
endendmodule
a
bAdd_half
sumc_out
ECEN 475 2.6
Continuous Assignmentmodule Add_half ( sum, c_out, a, b ); input a, b;
output sum, c_out;assign sum = a ^ b; // Exclusive orassign c_out = a & b; // And
endmodule
ECEN 475 2.7
Example of Flip-flop
module Flip_flop ( q, data_in, clk, rst );input data_in, clk, rst;output q;reg q;
always @ ( posedge clk ) begin
if ( rst == 1) q = 0;else q = data_in;
endendmodule
data_in
q
rst
clk
Declaration of synchronous behavior
Procedural statement
ECEN 475 2.8
Gate Delay and (yout, x1, x2); // default, zero gate delay and #3 (yout, x1, x2); // 3 units delay for all
transitions and #(2,3) G1(yout, x1, x2); // rising, falling delay and #(2,3) G1(yout, x1, x2), G2(yout2, x3, x4);
// Multiple instances
ECEN 475 2.9
Time Scales Time scale directive: ‘ timescale <time_unit>/<time_precision> time_unit -> physical unit of measure, time scale of delay time_precision -> time resolution/minimum step size during
simulation time_unit time_precision
Unit/precision Delay specification
Simulator time step
Delay value in simulation
1ns / 100ps #4 0.1ns 4.0ns100ns / ns #4 1ns 400ns10ns / 100ps #4.629 0.1ns 46.3ns
ECEN 475 2.10
Net Delay… …wire #2 y_tran;and #3 (y_tran, x1, x2);buf #1 (buf_out, y_tran);and #3 (y_inertial, x1, x2);… …
x1x2
y_tran
y_inertial
buf_out
2 4 6 8 10
2 4 6 8 10
2 4 6 8 10
2 4 6 8 10
2 4 6 8 10
x1
x2
y_inertial
y_tran
buf_out
ECEN 475 2.11
Structural vs. Behavioral Descriptions
module my_module(…); … assign …; // continuous assignment and (…); // instantiation of primitive adder_16 M(…); // instantiation of module
always @(…) begin … end initial begin … endendmodule
Structural, no order
Behavior, in order in each procedure
ECEN 475 2.12
Behavioral Statements
initial | alwayssingle_statement; |
begin block_of_statements;end
initial Activated from tsim = 0 Executed once Initialize a simulation
always Activated from tsim = 0 Executed cyclically Continue till simulation
terminates
ECEN 475 2.13
Example of Behavioral Statement
module clock1 ( clk );parameter half_cycle = 50;parameter max_time = 1000;output clk;reg clk;initial clk = 0;always begin#half_cycle clk = ~clk; endinitial #max_time $finish;
endmodule
clk
tsim50 100
150
200
ECEN 475 2.14
Assignment Continuous assignment
Values are assigned to net variables due to some input variable changes
“assign …=… “
Procedural assignment Values are assigned to register variables when
certain statement is executed in a behavioral description
Procedural assignment, “=“
ECEN 475 2.15
Example module mux4_PCA(a, b, c, d, select, y_out); input a, b, c, d; input [1:0] select; output y_out; reg y_out;
always @(select or a or b or c or d) begin if (select == 0) y_out=a; else if (select == 1) y_out=b; else if (select == 2) y_out=c; else if (select == 3) y_out=d; else y_out=1’bx; end
endmodule
Value of ‘a’ is assigned to y_out at this time
ECEN 475 2.16
Blocking and Non-blocking Assignment
initial begin
a = 1;b = 0;a = b; // a = 0;b = a; // b = 0;
end initial begin
a = 1;b = 0;a <= b; // a = 0;b <= a; // b = 1;
end
Blocking assignment “=“ Statement order matters A statement has to be executed
before next statement
Non-blocking assignment “<=“ Concurrent assignment If there are multiple non-
blocking assignments to same variable in same behavior, latter overwrites previous
ECEN 475 2.17
Delay Control Operator (#)initial
begin#0 in1 = 0; in2 = 1;#10 in3 = 1;#40 in4 = 0; in5 = 1;#60 in3 = 0;end
ECEN 475 2.18
Event Control Operator (@)
…@ ( eventA or eventB ) begin … end
Event -> identifier or expression
When “@” is reached Activity flow is suspended The event is monitored Other processes keep going
posedge: 0->1, 0->x, x->1 negedge: 1->0, 1->x, x->0
ECEN 475 2.19
Intra-assignment Delay: Blocking Assignment
// B = 0 at time 0// B = 1 at time 4…#5 A = B; // A = 1C = D;…A = #5 B; // A = 0C = D;…A = @(enable) B;C = D;…A = @(named_event) B;C= D;…
If timing control operator(#,@) on LHS Blocking delay RHS evaluated at (#,@) Assignment at (#,@)
If timing control operator(#,@) on RHS Intra-assignment delay RHS evaluated immediately Assignment at (#,@)
ECEN 475 2.20
Activity Flow Control ( if … else )if ( A == B ) P = d;if ( B < C );if ( a >= b ) begin … end
if ( A < B ) P = d;else P = k;
if ( A > B ) P = d;else if ( A < B ) P = k;else P = Q;
Syntax: if ( expression ) statement [ else statement ]
Value of expression 0, x or z => false Non-zero number => true
ECEN 475 2.21
Conditional Operator ( ? … : )
always @ ( posedge clock ) yout = ( sel ) ? a + b : a – b;
Conditional operator can be applied in
• either continuous assignments • or behavioral descriptions
ECEN 475 2.22
The case Statementmodule mux4 ( a, b, c, d, select, yout ); input a, b, c, d; input [1:0] select; output yout; reg yout; always @( a or b or c or d or select ) begin case ( select ) 0: yout = a;
1: yout = b; 2: yout = c;
3: yout = d; default yout = 1`bx; endcase
endmodule
Case items are examined in order
Exact match between case expression and case item
casez – treats “z” as don’t cares
casex – treats both “x” and “z” as don’t cares
ECEN 475 2.23
Switch Level NAND Gatemodule nand_2 ( Y, A, B );
output Y;input A, B;supply0 GND;supply1 PWR;wire w;
pmos ( Y, PWR, A );pmos ( Y, PWR, B );nmos ( Y, w, A );nmos ( w, GND, B );
endmodule
Y
Vdd
A
A
B
B