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USART

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Learn how to communicate

• Programmed I/O (Software Polling)

• Interrupt Driven I/O

• Direct Memory Access (DMA)

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Programmed I/O (Polling)

• Processor must read and check I/O ready bits for proper value before a transfer. Requires looping, reading status port, and constantly waiting for correct value.

• Processor then inputs or outputs data value to/from I/O device.

• This approach is limited to systems with just a few I/O devices – Processor overhead to loop and check in software

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I/O operation • Structure of an I/O operation

– Phase 1: prepare the device for the operation • In case of output, data is transferred to the data buffer

registers

• The operation parameters are set with the control registers

• The operation is triggered

– Phase 2: wait for the operation to be performed • Devices are much slower than the processor

• It may take a while to get/put the data on the device

– Phase 3: complete the operation • Error checking

• Clean up the control registers

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Example of input operation

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Example of output operation

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Programmed I/O Pseudo Code

// loop until output ready=1

do { // read status and mask off ready bit

status = read_port(status_port_address);

output_ready = status & 0x01;

}

while (output_ready == 0);

// output new data value

write_port(data_port_address, data_value);

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Polling

• If the device is very fast, then polling may be the best approach

– In fact, an interrupt based mechanism involves at least a pair of process switches

– It the duration of the operation is less than two process switches, then polling is the most optimized solution

• Almost all devices are much slower than the processor – usually, a data transfer takes much more than two process

switches

– For these devices, an interrupt-based mechanism is the best approach

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How much slower for I/O device?

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Interrupts

• Processor can service something else until interrupt came

• I/O ready signals generate a hardware Interrupt signal. Eliminates Processor I/O ready wait loops.

• An interrupt signal stops the Processor at the next instruction and the Processor calls the Interrupt service routine (ISR)

• Interrupt service routine transfers the data

• Interrupt routines must save all registers on the stack for the interrupt return to work (ISRs like subroutines - but “called” by a hardware signal)

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Interrupts

• Interrupt control hardware is needed to support

and enable/disable multiple interrupt signals

• Lower number interrupts typically have a higher

priority (can even interrupt a higher number

interrupt’s ISR) Gives fast I/O devices priority.

• Most modern processors have a vectored

interrupt system. Each interrupt jumps to a

different ISR address (X86 uses a table lookup

of addresses in low memory to jump to ISR)

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Interrupt vector

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Servicing an Interrupt

1. Currently Running

Process is Interrupted

3. IST

Launched

(Optional)

2. ISR

Code

executes

4. ISR

Returns

…….

Mov…

Add…

……

…..

…….

……

…….

……

………

…..

…….

…..

…..

….

…….

……

Mov..

Out..

…….

Reti

……….

…………

…..

……..

……..

…….

……..

.

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Input with interrupts

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Interrupt handler

Main CPU function()

while(true){

Map_computation();

}

Interrupt handler()

If left sensor

turn right

If right sensor

turn left

Line follower robot inside the maze

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Temporal diagram

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Polling vs. Interrupt

Phase 1: prepare the device for the operation

Phase 2: wait for the operation to be performed

Phase 3: complete the operation

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Question?

An Embedded System has three periodic devices

Service time: how long it takes to run interrupt handler for each device

Interrupt latency (allowable latency): maxim elapse time between an interrupt request and the start of interrupt handler routine

If program P takes 100 seconds with interrupt disabled,how long will it takes with interrupt enabled, assuming no interrupt overlapped?

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Solution

• Device 1 shall take (150+50)/800 = 0.25

• Device 2 shall take (50+50)/1000 = 0.10

• Device 3 shall take (100+100)/800 = 0.25

In one unit real time, it will take 0.6 unit time to service interrupt

For a program with 100 seconds, it will take 250 seconds to finish the entire program with interrupt enabled

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Direct Memory Access

• A DMA controller transfers blocks of data

directly to/from memory and the I/O device.

• DMA controller is a state machine with an

address pointer and a counter. Counts down

number of memory locations for transfer and

drives bus address and control lines (is a Bus

Master)

• Processor not involved in transfer once it starts

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Direct Memory Access

• DMA controller and Processor must both share the bus. Need bus arbitration hardware to control bus access (DMAs or Processor).

• DMA controller interrupts Processor when it’s block transfer is complete.

• Processor programs DMA controller’s address register and counter to start a new transfer.

• Need hardware for each DMA controller and an interrupt system

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DMA Bus Cycle

• Processor does not drive the bus during a

DMA bus cycle

• Bus Arbitration hardware is needed to

support multiple bus masters

Processor

With

Cache

Memory

I/O

Hardware

using DMA

System Bus

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DMA Support

• Phase 1: setup all required control

registers for DMA access (OS support)

• Phase 2: do something else

• Phase 3: do something else, OS

acknowledge DMA completion

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Comparison

• Polling – Faster

• Interrupt – More efficient

– Complex in the case of service many interrupts

– Limited number of interrupt

– Lower power

• DMA – Less processor overhead

– Less power (processor can go to sleep)

– Require hardware support

– Require interrupt support

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Tradeoffs

Transfer Technique Hardware CPU Overhead

Programmed I/O

Interrupt

DMA

USART

• USART stands for Universal Synchronous

Asynchronous Receiver Transmitter

• Full-duplex NRZ asynchronous serial data

transmission

• Offer wide ranges of baud rate

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Serial communication

• Can support high speed communication

• Support Synchronous, Asynchronous, and

Iso-synchronous

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RS232C

• RS232C communication is between Data

Terminal Equipment (DTE) e.g. computer

and Data Communication Equipment

(DCE) e.g. modem

• RS232C (Recommend Standard for

Number 232C) specify communication

standard such as voltage level, terminating

resistances, cable length etc.

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RS232C port connection

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RS-232 Serial Interface

• Transmit and Receive data lines

• No clock signal exchanged – Sender and

receiver need to have same baud rate

• Baud rate is the clock rate of the bits

• Normal Bits: Start, 8 Data, Stop

• Voltage levels: a 0 is >3V and a 1 is <-3V

• Special RS232 voltage level converter

chips are typically used in interface

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RS-232 standard

• Data rate from 20 kbps to over 1 Mbps

• Range up to 50 feet maximum

• It is robust interface up to 115,200 baud rate (pulse per second)

• Voltage as high/low as 15 Volt

• Single-ended means communication is over a single wire reference to ground

• There are 9 pins (DB-9) and 25 pins format (DB-25)

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RS-232 signal

1

0

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RS-232 single ended uni-direction

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RS-232 (DB9) male connector

Pin 1: Carrier Detect (CD)

Pin 2: Receive Data (RD)

Pin 3: Transmit Data (TD)

Pin 4: Data Terminal Ready (DTR)

Pin 5: Ground (GND)

Pin 6: Data Set Ready (DSR)

Pin 7: Request to Send (RTS)

Pin 8: Clear to Send (CTS)

Pin 9: Ring Indicator (RI)

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Connect computer-modem

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From DTE-DCE

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Connect two PC directly

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RS232 Handshaking

Assume modem wants to send data to PC

• RI indicate data available

• When modem connects, modem will send DCD signal at time t0

• Modem will send DSR signal at time t1 when it receive data to send

• PC will response with DTR at time t2

• Modem will send RTS at time t3

• PC response with CTS at time t4

RTS and CTS can also be sent again during the transaction

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UART

• UART is the name for the hardware used

for a RS-232 Serial Interface

• UART – Universal Asynchronous Receiver

Transmitter

• Early PCs had a UART chip, but this

functionality is now found inside a larger

chip that also contains other I/O features

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UART transmission

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UART initial communication

• Need to know how fast the data bits are coming

• Need to know where the starts bit begins

• Then, we know when to sample

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UART communication

• Non-return to zero. In the idle state, the logic state is 1.

• Start bit: transition to 0

• Data bit consists of start bit, 8 bit data, P-bit and stop bit

• Data bits can be changed to 5,6,7, and 8 bits

• The stop bit can be for a minimum of 1.5T, 2T instead of T, when T is normal interval

• P bit can be priority or for other purpose

• Stop bit: transition to 1

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RS-232C Serial interface

transmission of an 8-bit data value

0 0 0 0 1 0 1 0

Start

Bit

0 1 2 3 4 5 6 7 Stop

BitData Bit number

Mark (1)

Space (0)

0x50 = ASCII “P”

LSB MSB

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UART output 8 bits in 10T

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UART output 7 bits in 9T

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UART output 6 bits in 8T

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UART output 8 bit in 11T

ARM USART block diagram

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Control register in ARM

• Word length can be set by programming M

bit in USART_CR1 register

• Stop bit can be set by programming

USART_CR2, bit 12-13

– 1 stop bit (default)

– 2 stop bits used in modem

– 0.5 stop bits used in smart card

– 1.5 stop bits used in smart card

• Parity bit is set by USART_CR1, PCE bit 49

Word length setting

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Stop bit programming

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Receiver

• Initial Start bit detection: the sequence is

1 1 1 0 X 0 X 0 X 0 0 0 0

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Start bit detection

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Data Transmission

1. Enable the USART by writing the UE bit in

USART_CR1 to 1

2. Program the M bit in USART_CR1 to define the word

length

3. Program the number of stop bit in USART_CR2

4. Select the baud rate using USART_BRR

5. Set the TE bit in USART_DR register to send an idle

frame as first transmission

6. Write the data to send in USART_DR register

7. After write the last data, wait for TC bit = 1. This

indicates that the transmission is complete

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Data receive

1. Enable the USART by writing the UE bit in

USART_CR1 to 1

2. Program the M bit in USART_CR1 to define the word

length

3. Program the number of stop bit in USART_CR2

4. Select the baud rate using USART_BRR

5. Set the RE bit in USART_CR1 register. This enable the

receiver to search for a start bit

When a character is received

• RXNE bit is set

• An interrupt is generated, if RXNEIE bit is set 55

USART programming

int main(void){

RCC_Configuration(); // System Clocks Configuration

NVIC_Configuration(); // NVIC Configuration

USART1GPIOInit(); // Configure the GPIO for USART1

USART1Init(); // Init USART1

USART_Communication();

}

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void USART1GPIOInit(void){

GPIO_InitTypeDef GPIO_InitStructure;

/* Enable GPIOA and USART1 clock */

RCC_APB2PeriphClockCmd(RCC_APB2Periph_GPIOA |

RCC_APB2Periph_USART1, ENABLE);

/* Configure USART1 Tx (PA.09) as alternate function push-pull */

GPIO_InitStructure.GPIO_Pin = GPIO_Pin_9;

GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz;

GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF_PP;

GPIO_Init(GPIOA, &GPIO_InitStructure);

/* Configure USART1 Rx (PA.10) as input floating */

GPIO_InitStructure.GPIO_Pin = GPIO_Pin_10;

GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IN_FLOATING;

GPIO_Init(GPIOA, &GPIO_InitStructure);

}

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void USART1Init(void){

USART_InitTypeDef USART_InitStructure;

/* USART1 is configured as follow:

- BaudRate = 115200 baud

- Word Length = 8 Bits

- One Stop Bit

- No parity

- Hardware flow control disabled (RTS and CTS signals)

- Receive and transmit enabled*/

USART_InitStructure.USART_BaudRate = 115200;

USART_InitStructure.USART_WordLength = USART_WordLength_8b;

USART_InitStructure.USART_StopBits = USART_StopBits_1;

USART_InitStructure.USART_Parity = USART_Parity_No;

USART_InitStructure.USART_HardwareFlowControl =

USART_HardwareFlowControl_None;

USART_InitStructure.USART_Mode = USART_Mode_Rx | USART_Mode_Tx;

USART_Init(USART1, &USART_InitStructure); /* Configure USART1 */

USART_Cmd(USART1, ENABLE); /* Enable the USART1 */

}

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void USART_Communication(void){

char ch;

while(1)

{

SendCharUSART1(0x0D);

SendCharUSART1(0x0A);

SendCharUSART1('U');

SendCharUSART1('S');

SendCharUSART1('A');

SendCharUSART1('R');

SendCharUSART1('T');

SendCharUSART1('1');

SendCharUSART1('>');

// Get and echo USART1

ch = GetCharUSART1();

while (ch != 0x0D)

{

SendCharUSART1(ch);

ch = GetCharUSART1();

}

}

} 59

void SendCharUSART1(char ch){

// Wait until TXE is set

while(USART_GetFlagStatus(USART1, USART_FLAG_TXE) == RESET)

{

}

USART_SendData(USART1, ch);

// Wait until the end of transmit

while(USART_GetFlagStatus(USART1, USART_FLAG_TC) == RESET)

{

}

}

char GetCharUSART1(void){

char ch;

// Wait until the USART1 Receive Data Register is not empty

while(USART_GetFlagStatus(USART1, USART_FLAG_RXNE) == RESET)

{

}

ch = (USART_ReceiveData(USART1) & 0xFF);

return ch;

} 60

Simulink UART setup

• To setup UART communication protocol

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Setup configuration

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UART RX

• To receive data from UART

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Binary blocking mode

• Blocking mode:

The cpu processor will

wait for data until full

Packet received.

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ASCII blocking mode

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ASCII block mode to string

buffer

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Non-blocking mode

• The block will come with an addition

output port “ready”

– A value of 1 means the new output is ready

– A value of 0 means data is not available

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Limitation

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UART Tx

• For sending data to UART

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Transmit Binary Packet

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Transmit ASCII packet

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Transmit ASCII packet to

Stream buffer

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Example

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Enable Subsystem

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Enable Subsystem1

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Enable Subsystem2

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Testing

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Testing (setting up the config.)

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Hardware Setup

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Output

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Simulink hi-speed

communication: target

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Configurations

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Configurations

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Simulink hi-speed

communication: host

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Simulation

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Software setup

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Setup

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Setup

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Hardware Setup

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Output

• The speed samping data is at 1KHz

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Blocking example board1

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Simulink: two boards

communication blocking mode

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Blocking Example board2

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Blocking mode

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Hardware

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What should be happening?

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Output

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Non-blocking example

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Hardware

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Output

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Simulink: two boards non-

blocking mode

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Question?

Write a program to read from USART1 and

write to USART2 BaudRate = 115200

baud, Word Length = 8 Bits, one Stop Bit,

No parity

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Questions?

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