To designing counters using verilog code

Experiment No:9 Aim: To Implement counters. NAME: Shyamveer Singh SECTION: E1207

REG N0: 11205816 ROLL NO: B-54

Truth Table: Up down counter:

Up counter:

Theory: An up counter simply counts from 0 to 9. We can use this circuit to make , This circuit can also be used to make a digital clock. Both Synchronous and Asynchronous counters are capable of counting “Up” or counting “Down”, but their is another more “Universal” type of counter that can count in both directions either Up or Down depending on the state of their input control pin and these are known as Bidirectional Counters.

Bidirectional counters, also known as a up down counter.

PROGRAMME CODES

4bit up counter: module fbuc(clk,reset,q); input clk,reset; output [3:0]q;

reg [3:0]q;

always@(clk)

begin if(reset) q=0; else if(reset==0&&q<15) q=q+1; end endmodule

reset = 1;clk = 0;

// Wait 100 ns for global reset to finish #10; reset = 0;clk = 1; #10; reset = 0;clk = 0; #10; reset = 0;clk = 1; #10; reset = 0;clk = 0; #10; reset = 0;clk = 1; #10; reset = 0;clk = 0; #10; reset = 0;clk = 1; #10; reset = 0;clk = 0; #10; reset = 0;clk = 1; #10; reset = 0;clk = 0; #10; reset = 0;clk = 1;

#10; reset = 0;clk = 0; #10; reset = 0;clk = 1; #10; reset = 0;clk = 0; #10; reset = 0;clk = 1; #10;

// Add stimulus here

endmodule // Initialize Inputs

reset = 1;clk = 0;

// Wait 100 ns for global reset to finish #10; reset = 0;clk = 1; #10; reset = 0;clk = 0; #10; reset = 0;clk = 1; #10;

reset = 0;clk = 0; #10; reset = 0;clk = 1; #10; reset = 0;clk = 0; #10; reset = 0;clk = 1; #10; reset = 0;clk = 0; #10; reset = 0;clk = 1; #10; reset = 0;clk = 0; #10; reset = 0;clk = 1; #10; reset = 0;clk = 0; #10; reset = 0;clk = 1; #10; reset = 0;clk = 0; #10; reset = 0;clk = 1; #10;

endmodule

4bit down counter module fbdc(clk,reset,q); input clk,reset; output [3:0]q;

reg [3:0]q;

always@(clk)

begin if(reset)

else if(reset==0&&q>0) q=q-1; end

endmodule

reset = 1;clk = 0;

// Wait 100 ns for global reset to finish #10; reset = 0;clk = 1; #10; reset = 0;clk = 0; #10; reset = 0;clk = 1; #10; reset = 0;clk = 0; #10; reset = 0;clk = 1; #10; reset = 0;clk = 0; #10; reset = 0;clk = 1; #10; reset = 0;clk = 0; #10; reset = 0;clk = 1; #10; reset = 0;clk = 0;

#10; reset = 0;clk = 1; #10; reset = 0;clk = 0; #10; reset = 0;clk = 1; #10; reset = 0;clk = 0; #10; reset = 0;clk = 1; #10; reset = 0;clk = 0; #10;

reset = 0;clk = 1; #10;

endmodule

4b Up down counter

module fbudc(clk,reset,up,dn,q); input clk,up,dn,reset; output [3:0]q; reg [3:0]q; always@(clk) begin if (reset) q=0; else if(up)

q=q+1;

else if(dn)

q=q-1; end

endmodule

clk = 0; reset = 1; up = 1; dn = 0;

// Wait 100 ns for global reset to finish #10; clk = 1; reset = 0; up = 1; dn = 0; #10; clk = 0; reset = 0; up = 1; dn = 0; #10; clk = 1; reset = 0; up = 1; dn = 0; #10; clk = 0;

reset = 0; up = 1; dn = 0; #10; clk = 1; reset = 0; up = 1; dn = 0; #10; clk = 0; reset = 0; up = 1; dn = 0; #10; clk = 1; reset = 0; up = 1; dn = 0; #10; clk = 0; reset = 0; up = 1; dn = 0; #10; clk = 1; reset = 0; up = 1; dn = 0; #10; clk = 0; reset = 0; up = 1; dn = 0; #10; clk = 1; reset = 0; up = 1; dn = 0; #10; clk = 0; reset = 0; up = 1; dn = 0; #10; clk = 1; reset = 0; up = 1; dn = 0; #10;

clk = 0; reset = 0; up = 1; dn = 0; #10; clk = 1; reset = 0; up = 1; dn = 0; #10; clk = 1; reset = 0; up = 0; dn = 1; #10; clk = 0; reset = 0; up = 0; dn = 1; #10; clk = 1; reset = 0; up = 0; dn = 1; #10; clk = 0; reset = 0; up = 0; dn = 1; #10; clk = 1; reset = 0; up = 0; dn = 1; #10; clk = 0; reset = 0; up = 0; dn = 1; #10; clk = 1; reset = 0; up = 0; dn = 1; #10; clk = 0; reset = 0; up = 0; dn = 1;

#10; clk = 1; reset = 0; up = 0; dn = 1; #10; clk = 0; reset = 0; up = 0; dn = 1; #10; clk = 1; reset = 0; up = 0; dn = 1; #10; clk = 0; reset = 0; up = 0; dn = 1; #10; clk = 1; reset = 0; up = 0; dn = 1; #10; clk = 0; reset = 0; up = 0; dn = 1; #10; clk = 1; reset = 0; up = 0; dn = 1; #10; clk = 0; reset = 0; up = 0; dn = 1; #10;

endmodule

To designing counters using verilog code

Engineering

Transcript of To designing counters using verilog code

Verilog HDL - 2. Introduce to Verilog HDL

Designing Combinational Logic Circuits in Verilog - 2 Discussion 7.3.

Vlsi Verilog _ Fir Filter Design Using Verilog

Synchronous Counters, ripple counter & other counters ...

Display Counters : MET Counters

1/27/06EECS150 Lab Lecture #21 Designing with Verilog EECS150 Spring 2006 – Lab Lecture #2 Brian Gawalt Greg Gibeling.

Chapter 9: Sequential Logic Modules - wiley.com · Flip-flops Memory elements Shift registers Counters ... Digital System Designs and Practices Using Verilog HDL and FPGAs @ 2008~2010,

Experiment 4 Verilog & Adders and Subtractors...Introduction to Verilog As digital designs are becoming complex, the conventional way of designing digital circuits starting from schematic

Verilog Tutorial - UCSBstrukov/ece154a/labs/verilog.pdf · Verilog Tutorial Adapted from Krste Asanovic. Verilog Fundamentals •History •Data types •Structural Verilog •Functional

05-Verilog Language Concepts - Amazon S3 · PDF file2 CSE 467 Verilog Digital System Design 3 Verilog Language Concepts Module Basics (cont.) Arrays Verilog operators Verilog data

Addressing Challenges in Designing Powertrain System …tntdpc.com/automotiveelectronics/vijay.pdf · Verilog C, C++ N RESEARCH REQUIREMENTS ... Turbo Ignition Timing ... Production

HDL Chip Design- A Practical Guide for Designing, Synthesizing and Simulating ASICs and FPGAs Using VHDL or Verilog

Verilog – Sequential Logic - Worcester Polytechnic Instituteusers.wpi.edu/~rjduck/Verilog for synthesis - sequential logic rev... · Verilog – Sequential Logic Verilog for Synthesis

Designing of fifo and serial peripheral interface protocol using Verilog HDL

Verilog through designing real circuits. 3 - Verilog... · 1 This and the next lectures are about Verilog HDL, which, together with another language VHDL, are the most popular hardware

Behavioral Modeling using Verilog-A Notes/VerilogA Modeling.pdf · Verilog-AMS Verilog-AMS is an extension of Verilog-A to include digital Verilog co-simulation functionality Works

A Verilog Primer - University of California, Berkeleyinst.eecs.berkeley.edu/.../verilog/Verilog_Primer_Slides.pdfA Verilog Primer An Overview of Verilog for Digital Design and Simulation

Verilog Introduction for System Verilog - Leading Edge · Verilog Introduction for System Verilog This 1 day course provides an introduction to the Verilog syntax with emphasis on

Verilog Tutorial - Verilog HDL Tutorial with Examples

Introduction to Verilog - Carleton Universityjknight/97.478/PetervrlJ.pdf · Introduction to Verilog Monday, ... Flip-flops, Counters, Multiplexers, Adders/Subtracters, Tri-State