The Instruction SetArchitecture Level(ISA)Architecture Level(ISA)

Chapter 5

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ISA Level

Th ISA l l i th i t f b t th il d th h dThe ISA level is the interface between the compilers and the hardware.(ISA –level code is what a compiler outputs) 2

Memory Models

An 8-byte word in a little-endian memory. (a) Aligned. (b) Notaligned. Some machines require that words in memory be aligned.

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Overview of the Pentium 4ISA Level

The Pentium 4’s primary registersregisters.

P4 fetches 8bytes at a time ffrom the memory.

80386 is 32-bit , all called ,IA-32.

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Registers1. Special purpose register2. General purpose register

SPR : program counter, stack pointer.GPR : hold local variable, intermediate results of calculations.

• P4 has three operating modes:real mode: ------------------behaves like 8088 any wrongreal mode: behaves like 8088, any wrong

in the program ----- crash.Virtual 8086 mode: operating system control the whole machinemachine.Protected mode: behaves like P4.

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Registersa) Use 8-bit name, 16-bit name, or 32-bit nameb) Applies to EAX, EBX, ECX, and EDX

AH AL

88

8 bits + 8 bits

16 bitsAX

EAX 32 bits32 bits

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General-Purpose Registers) EAX A l f d d l d di & la) EAX — Accumulator for operands and results data, div&mul

b) EBX — Pointer to data in the DS segment (Memory address)c) ECX — Counter for string and loop operationsc) ECX Counter for string and loop operationsd) EDX — I/O pointere) ESI — (Source index) Pointer to data in the segment pointed

t b th DS i t i t f t i tito by the DS register; source pointer for string operationsf) EDI — (Destination index) Pointer to data (or destination) in

the segment pointed to by the ES register; destination pointer g p y g pfor string operations

g) ESP — (Stack pointer) Stack pointer (in the SS segment)h) EBP (Base pointer )Pointer to data on the stack (in the SSh) EBP — (Base pointer )Pointer to data on the stack (in the SS

segment) point to the base of the current stack.

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Registera) Segment

– CS – code segment– DS – data segment– DS – data segment– SS – stack segment– ES, FS, GS - additional segments

b) EIP – instruction pointerc) EFLAGS

control flags (control CPU’s operation e g break– control flags (control CPU s operation, e.g. break, interrupt, enter 8086/protected mode)

– Status flag– each flag is a single binary bit (set or clear)

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Status Flags

• Carry (CF)unsigned arithmetic out of range– unsigned arithmetic out of range

• Overflow (OF)– signed arithmetic out of range

• Sign (SF)– result is negative

• Zero (ZF)( )– result is zero

• Auxiliary Carry (AC)carry from bit 3 to bit 4 in 8 bit operand– carry from bit 3 to bit 4 in 8-bit operand

• Parity (PF)– sum of 1 bits in least-significant byte is an even

numbernumber

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Segment Registers

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Overview of theOverview of the 8051 ISA Level

(a) On chip memory organization for the 8051(a) On-chip memory organization for the 8051. (b) Major 8051 registers. 11

8051

Summary of features of the standard 8051– 4K bytes internal ROM (program)– 128 bytes internal RAM (data)y ( )– Four 8-bit I/O ports– Two 16-bit timers

Serial interface– Serial interface– 64K external code memory space– 64K external data memory space

210 bi dd bl l i– 210 bit-addressable locations

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8051• 8051 implements a separate memory space for programs(code) and data.• Both code and data may be internal however both expand• Both code and data may be internal, however, both expandusing external components to a maximum of 64K code memoryand 64K data memory.

I l i f hi ROM d hi d• Internal memory consists of on-chip ROM and on-chip dataRAM.• On-chip RAM contains a rich arrangement of general purpose p g g p pstorage, bit addressable storage, register banks, and special function registers.• In the 8051 the registers and input/output ports are memory• In the 8051, the registers and input/output ports are memory mapped and accessible like any other memory location.• In the 8051, the stack resides within the internal RAM,

th th i t l RAMrather than in external RAM.13

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Data Types on the Pentium 4

The Pentium 4 numeric data types. Supported types are marked with ×.

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Data Types on the 8051

The 8051 numeric data types. ySupported types are marked with ×.

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Instruction Formats (1)

Four common instruction formats: (a) Zero-address instruction. (b) One-address instruction (c) Two-address instruction. (d) Three-address instruction.

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Instruction Formats (2)

Some possible relationships between instruction and word length.

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Expanding Opcodes (1)

A i t ti ith 4 bit d d th 4 bit dd fi ldAn instruction with a 4-bit opcode and three 4-bit address fields.22

Expanding Opcodes (2)

An expanding opcode allowing 15 three-address instructions, 14two-address instructions, 31 one-address instructions, and 16

dd i t ti Th fi ld k dzero-address instructions. The fields marked xxxx, yyyy, and zzzz are 4-bit address fields. 23

The Pentium 4 Instruction Formats

Th P ti 4 i t ti f tThe Pentium 4 instruction formats.24

The 8051 Instruction Formats

Th 8051 i t ti f tThe 8051 instruction formats.25

Addressing Modes

a) Immediateb) Directc) Indirectd) R i td) Registere) Register Indirectf) Displacement (Indexed)f) Displacement (Indexed) g) Stack

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Immediate Addressing

a) Operand is part of instructiona) Operand is part of instructionb) Operand = address fieldc) e.g. ADD 5c) e.g. ADD 5

– Add 5 to contents of accumulator– 5 is operand

d) N f f h dd) No memory reference to fetch datae) Fastf) Limited rangef) Limited range

OperandOpcode OperandOpcode

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Direct Addressing

a) Address field contains address of operand)b) Effective address (EA) = address field (A)c) e.g. ADD A

– Add contents of cell A to accumulator– Look in memory at address A for operand

d) Single memory reference to access datad) Single memory reference to access datae) No additional calculations to work out effective addressf) Limited address space

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Direct Addressing Diagram

I t ti

Address AOpcode

Instruction

Memorye o y

OperandOperand

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Indirect Addressing (1)

a) Memory cell pointed to by address field contains the address of (pointer to) the operandof (pointer to) the operand

b) EA = (A)– Look in A, find address (A) and look there for operand

c) e.g. ADD (A)– Add contents of cell pointed to by contents of A to accumulator

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Indirect Addressing (2)

a) Large address space b) 2n where n = word lengthb) 2 where n word lengthc) Multiple memory accesses to find operandd) Hence slower

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Indirect Addressing Diagram

Instruction

Address AOpcodeMemory

Pointer to operand

Operand

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Register Addressing (1)

a) Operand is held in register named in address filedb) EA = Rc) Limited number of registersd) Very small address field neededd) Very small address field needed

– Shorter instructions– Faster instruction fetch

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Register Addressing (2)

a) No memory accessb) Very fast executionc) Very limited address spaced) Multiple registers helps performanced) Multiple registers helps performancee) Direct addressing

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Register Addressing Diagram

I t ti

Register Address ROpcode

Instruction

Registerseg ste s

OperandOperand

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Register Indirect Addressing

a) indirect addressingb) EA (R)b) EA = (R)c) Operand is in memory cell pointed to by contents of

register Rgd) Large address space (2n)e) One fewer memory access than indirect addressing

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Register Indirect Addressing Diagram

R i t Add RO d

Instruction

Register Address ROpcodeMemory

Registers

OperandPointer to Operand

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Displacement Addressing

a) EA = A + (R)b) Address field hold two values

– A = base value– R = register that holds displacement– R = register that holds displacement– or vice versa

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Displacement Addressing Diagram

Instruction

Register ROpcodeMemory

Address A

Registers

OperandPointer to Operand +

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Relative Addressing

a) A version of displacement addressingb) R = Program counter, PCc) EA = A + (PC)d) i.e. get operand from A cells from current location

pointed to by PCe) locality of reference & cache usagee) locality of reference & cache usage

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Base-Register Addressing

a) A holds displacementb) R holds pointer to base addressc) R may be explicit or implicit) 80 86d) e.g. segment registers in 80x86

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Indexed Addressing

a) A = baseb) R = displacementc) EA = A + Rd) Good for accessing arrays

– EA = A + R– R++R

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Indexed Addressing (1)

A generic assembly program for computing the OR of Ai AND Bi f t 1024 l tAi AND Bi for two 1024-element arrays.

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Indexed Addressing (2)

A possible representation of MOV R4,A(R2).

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Combinations

a) Post indexa) Post indexb) EA = (A) + (R)

c) Pre indexd) EA = (A+(R))

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Pentium Addressing Modes

a) Virtual or effective address is offset into segmenta) Virtual or effective address is offset into segment– Starting address plus offset gives linear address– This goes through page translation if paging enabled

b) 12 dd i d il blb) 12 addressing modes available– Immediate– Register operandg p– Displacement– Base

Base with displacement– Base with displacement– Scaled index with displacement– Base with index and displacement– Base scaled index with displacement– Relative 46

The Pentium 4 Addressing Modes (1)

The Pentium 4 32 bit addressing modes M[x]The Pentium 4 32-bit addressing modes. M[x] is the memory word at x. 47

The Pentium 4 Addressing Modes (2)

A t [i]Access to a[i].48

Loop Control

(a) Test-at-the-end loop. (b) Test-at-the-beginning loop.

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Input/Output (1)

Three different I/O schemes are in current use in personal computerscomputers

Programmed I/O with busy waiting .

Interrupt-driven I/O.

DMA I/O.

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Input/Output (1)

•Device registers for a simple terminal (Status & Data) 4 each is 1•Device registers for a simple terminal (Status & Data). 4, each is 1Byte, two for (In) and two for (out).•Memory mapped I/O, part of the memory, Ordinary instructions. Otherwise use IN OUTOtherwise use IN, OUT. •Bit 7 sits by the hardware whenever a character arrives.•If the software has previously set bit 6, an interrupt is generatedI d I/O CPU it ti ht l t dl di th•In programmed I/O, CPU sits a tight loop repeatedly reading the

keyboard status register then the software read the buffer.•To write a character to the screen, the software first reads the di l t t i t t if th READY bit i 1display status register to see if the READY bit is 1.

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Input/Output (2)

A l f d I/OAn example of programmed I/O.52

Input/Output (2)

• Disadvantage of programmed I/O CPU spends most of• Disadvantage of programmed I/O. CPU spends most of the time waiting the device to be ready (called busy waiting)

• The way to get rid of busy waiting is to have the CPU start the I/O device and tell it to generate an interrupt g pwhen it is done.

• Disadvantage is that interrupt is required for every• Disadvantage is that, interrupt is required for every character transmitted.

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Input/Output (3)•DMA (Direct Memory Access) chip has at least four registers.

•The first one contains the memory address to be read.

• The second one contains the count how many bytes (or word ) are to beThe second one contains the count , how many bytes (or word ) are to be transferred .

•The third one specifies the device number or I/O space address to use. Thus if i hi h I/O d i i d i dspecifying which I/O device is desired.

•The fourth one tells whether data are to be read from or writing to the I/O device.device.

•To write a block of 32 bytes from memory address 100 to terminal 4, the CPU writes 32, 100, 4, and 1 for write.

• DMA controller makes a bus request to read from memory, the another request to write to the terminal. When the count reach 0, DMA controller asserts the interrupt line on the CPU chip. p p

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I t/O t t (3)Input/Output (3)

A system with a DMA controller.55

The Pentium 4 Instructions (1)

A selection of the Pentium 4 integer instructions.56

The Pentium 4 Instructions (2)

A selection of the Pentium 4 integer instructions.57

The Pentium 4 Instructions (3)

A selection of the Pentium 4 integer instructions.58

The Pentium 4 Instructions (4)

A selection of the Pentium 4 integer instructionsA selection of the Pentium 4 integer instructions.

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8051 Instructions (1)

The 8051 Instruction set.60

8051 Instructions (2)

The 8051 Instruction set.61

8051 Instructions (3)

The 8051 Instruction set.62

8051 Instructions (4)

The 8051 Instruction set.63

8051 Instructions (5)8051 Instructions (5)

The 8051 Instruction set.64