Post on 11-Dec-2015
Feb 20, 2008 E0-286@SERC 1
VLSI Testing Sequential ATPG - I
VLSI Testing Sequential ATPG - I
Virendra SinghIndian Institute of Science (IISc)
Bangalorevirendra@computer.org
E0-286: Testing and Verification of SoC Design
Lecture – 14
Feb 20, 2008 E0-286@SERC 2
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Static and Dynamic Compaction of Sequences
Static and Dynamic Compaction of Sequences
Static compactionATPG should leave unassigned inputs as XTwo patterns compatible – if no conflicting values for any PICombine two tests ta and tb into one testtab = ta tb using D-intersection Detects union of faults detected by ta & tb
Dynamic compactionProcess every partially-done ATPG vector immediatelyAssign 0 or 1 to PIs to test additional faults
Feb 20, 2008 E0-286@SERC 3
Compaction ExampleCompaction Example
t1 = 0 1 X t2 = 0 X 1t3 = 0 X 0 t4 = X 0 1
Combine t1 and t3 , then t2 and t4
Obtain:
t13 = 0 1 0 t24 = 0 0 1
Test Length shortened from 4 to 2
Feb 20, 2008 E0-286@SERC 4
ATPG based Formal Verification
ATPG based Formal Verification
A
B
C
C
A
B
Z
s-a-0
P
Q
R
S
T
Formal Equivalence Checking
Feb 20, 2008 E0-286@SERC 5
Formal Equivalence Checking
Formal Equivalence Checking
Feb 20, 2008 E0-286@SERC 6
Sequential CircuitsSequential CircuitsA sequential circuit has memory in addition to combinational logicTest for a fault in a sequential circuit is a sequence of vectors, which
Initializes the circuit to a known stateActivates the fault, andPropagates the fault effect to a PO
Methods of sequential circuit ATPGTime-frame expansion methodsSimulation-based methods
Feb 20, 2008 E0-286@SERC 7
Example: A Serial AdderExample: A Serial Adder
FF
An Bn
Cn Cn+1
Sn
s-a-0
11
1
1
1X
X
X
D
D
Combinational logic
Feb 20, 2008 E0-286@SERC 8
Time-Frame ExpansionTime-Frame Expansion
An Bn
FF
Cn Cn+11
X
X
Sn
s-a-011
1
1
D
D
Combinational logicSn-1
s-a-011
1
1 X
D
D
Combinational logic
Cn-1
1
1
D
D
X
An-1 Bn-1 Time-frame -1 Time-frame 0
Feb 20, 2008 E0-286@SERC 9
Concept of Time-FramesConcept of Time-FramesIf the test sequence for a single stuck-at fault contains n vectors,
Replicate combinational logic block n timesPlace fault in each blockGenerate a test for the multiple stuck-at fault
using combinational ATPG
Comb.block
Fault
Time-frame
0
Time-frame
-1
Time-frame-n+1
Unknownor given
Init. state
Vector 0Vector -1Vector -n+1
PO 0PO -1PO -n+1
Statevariables
Nextstate
Feb 20, 2008 E0-286@SERC 10
Thank YouThank You