MEHRAN UNIVERSITY OF ENGINEERING AND TECHNOLOGY, JAMSHORODEPARTMENT OF TELECOMMUNICATION ENGINEERING

FRM-001/00/QSP-004 Dec. 01, 2001

Tentative Teaching Plan

Name of Teacher: Engr. Naeem Aijaz YousfaniSubject: Digital Electronics Batch: 16 TL Year: First (1st Term)Term Starting Date: 04-01-2016 Term Suspension Date: 24-04-2016

S. #.

Topics

No. of Lecture

Hrs Require

Sec - I

1 Introduction 01 5-1

2 Number Systems 01 6-13 Number System Conversion 01 6-14 Grey Code 015 Logic Event, Binary Variables and Fundamental Boolean Operation 016 Boolean Operations (XOR, NOR, NAND ….), Truth Table 017 Digital Logic Gates, Symbols 018 Parity in Codes 019 Boolean Algebra and Boolean Rules 0110 DeMorgan’s Theorems 0111 Boolean Expression 0112 Reducing expression using Boolean Rules 0113 Karnaugh Map 0114 Reducing expression using K-Map 0115 Universal Gates, Design Logic Ckts using Universal gates 0116 Driving SOP and POS Expressions + Class Test # 1 0117 Combinational Logic Examples 0118 Half Adder, Full Adder 0119 Parallel Adder, Parallel Adder Subtractor 0120 Active High Decoder, Active Low Decoder 0121 Code Converter, Grey Code Converter 0122 Binary to BCD Converter 0123 Multiplexer and DeMultiplexer 0124 Seven Segment Drivers, CC and CA Seven Segmented Displays 0125 Combinational Logic Using ICs 0126 Logic Families Resister Transistor Logic (RTL) 0127 Logic Families Diode Transistor Logic (DTL) 0128 Logic Families Transistor – Transistor Logic (TTL) and Classes of

TTL. Class Test # 201

29 Logic Families Emitted Coupled (EC), Injection Integrated (II) and Direct Coupled Transistor Logic.

01

30 CMOS Logic CMOS NOT Gate and CMOS NAND Gate 0131 Switch Parameters 0132 Propagation Delay Times in TTL and CMOS 0133 Buffers, Calculating fan-in and fan-out of logic gates 0134 Interfacing TTL to CMOS, Pull-up-resistor 0135 Multivibrators, Transistors Ckts of Bi-stable Multivibrators 0136 Transistor Ckts of Mono stable Multivibrators 0137 Transistor Ckts of A-stable Multivibrators 0138 Timing diagram of Multivibrators 01

39 Ckt operation and TT of SR Latch, Ckt operation and TT of SR Flip Flop

01

40 Ckt operation and TT of JK Flip Flop, Ckt operation and TT of Master-Slave JK Flip Flop

01

41 Ckt operation and TT of D Flip Flop, Ckt operation and TT of T Flip Flop

01

42 555 Timer Internal Structure, Astable and Monostable Mode. Class Test # 3

01

Total Number of required Lectures 42

Signature of Teacher: Dated:

Remarks of DMRC:

Signature of Chairman: Dated: