Post on 28-Jan-2017
SPACE-DC/DC II
DC-DC Converter for Aerospace Industry
Gonçalo Emanuel Santos de Aguiar
Dissertação para obtenção do Grau de Mestre em
Engenharia Electrotécnica e de Computadores
Júri
Presidente: Prof. Marcelino Bicho dos Santos
Orientador: Prof. Nuno Cavaco Gomes Horta
Co-orientador: Prof. Jorge Manuel Correia Guilherme
Vogais: Prof.ª Maria Beatriz Vieira Borges
Dezembro 2011
Acknowledgements
Firstly thanks to my mother Silvina for the motivation and for teaching me ethic values and principles. To my
father Aurélio for granting me the level of instruction that I currently benefit. To Professor Jorge Guilherme for
always being available to clarify several doubts and for giving out suggestions that greatly helped in the
development of this dissertation. To Professor Nuno Horta for the support given in dealing with bureaucratic
and technical aspects.
To all a great and sincere thank you.
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Resumo
Neste documento é abordado o projecto de um conversor DC/DC de baixa potência (3 a 10 W) a ser
empregue na indústria aeroespacial.
O trabalho desenvolvido nesta dissertação vem no seguimento dos trabalhos anteriores ( [1] [2] [3] ) que
projectaram conversores DC/DC controlados pelos métodos de controlo PWM em modo de corrente ou PFM.
Foram deixados alguns problemas de estabilidade e de isolamento galvânico como sugestões futuras de
melhoramento, sendo requisito imposto pela ESA.
Em primeiro lugar é analisado o comportamento da electrónica no espaço e são descritas as restrições que
este ambiente impõe num projecto de microelectrónica. Com base nisso será escolhida a arquitectura do
conversor DC/DC que mais se apropria para a aplicação em concreto. De seguida são estudadas várias soluções
de concretização do isolamento galvânico, tendo em consideração especial o alto rendimento, bem como baixa
distorção do sinal realimentado.
Para resolver os problemas de estabilidade detectados nos trabalhos anteriores, o modelo do interruptor de
PWM será aplicado a um conversor forward de múltipla saída. Os esquemas de controlo PWM e PFM serão
simulados em ambiente LTSpice, de modo a observar as suas respostas a transitórios de carga e validar a sua
estabilidade, bem como determinar os seus rendimentos. Finalmente o circuito de controlo será implementado
num circuito integrado usando software CADENCE.
Palavras chave: Conversor DC/DC, indústria aeroespacial, isolamento galvânico, estabilidade
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Abstract
This document addresses the design of a low power (3 to 10 W) DC/DC converter to be employed in the
aerospace industry.
The work developed in this dissertation is a follow up of previous dissertations ( [1] [2] [3] ) that designed
radiation hardened DC/DC converters controlled with PWM current mode control or PFM methods. Some
stability issues and the galvanic isolation feature were left as suggestions for future improvements, being a
requirement imposed by ESA.
Firstly, the behavior of electronics in space is analyzed and the constraints that this environment poses to
microelectronics are described. Knowing this, the appropriate architecture for the DC/DC converter that suits
the application is chosen between many benchmark topologies. Subsequently various solutions to implement
the galvanic insulation are studied, giving special emphasis to high performance and efficiency, as well as low
feedback signal distortion.
In order to solve the stability issues of previous works, the PWM switch model will be applied to a multi-
output forward converter. The PWM and PFM control schemes will be simulated in LTSpice environment in
order to observe their response to transient loads and validate their stability and determine efficiency. Finally
the controller circuit scheme will be implemented in an integrated circuit using CADENCE software.
Keywords: DC/DC converter, aerospace industry, galvanic insulation, stability
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Contents
1. Introduction .................................................................................................................................................... 3
1.1. Overview ..................................................................................................................................................... 3
1.2. System specifications ................................................................................................................................. 4
1.3. Objectives ................................................................................................................................................... 4
1.4. Terminology ................................................................................................................................................ 5
1.5. Design tools ................................................................................................................................................ 5
1.6. Structure ..................................................................................................................................................... 6
2. Electronics in space environment.................................................................................................................. 7
2.1. Temperature ............................................................................................................................................... 7
2.1.1. Solution .................................................................................................................................................. 7
2.2. Vacuum ....................................................................................................................................................... 8
2.2.1. Solution .................................................................................................................................................. 8
2.3. Shock and vibration.................................................................................................................................... 8
2.3.1. Solution .................................................................................................................................................. 8
2.4. Electromagnetic inference ........................................................................................................................ 9
2.4.1. Solution .................................................................................................................................................. 9
2.5. Radiation ..................................................................................................................................................... 9
2.5.1. Sources of radiation .............................................................................................................................. 9
2.5.2. Effects of radiation in electronics ......................................................................................................... 10
2.5.3. Solution .................................................................................................................................................. 15
3. State of the Art................................................................................................................................................ 18
3.1. Power stage circuit ..................................................................................................................................... 18
3.1.1. Flyback converter .................................................................................................................................. 19
3.1.2. Forward converter ................................................................................................................................. 19
3.1.3. Other topologies .................................................................................................................................... 20
3.1.4. Comparison of benchmark topologies ................................................................................................. 21
3.1.5. Chosen power stage topology .............................................................................................................. 21
3.2. Control circuit ............................................................................................................................................. 21
3.2.1. Pulse width modulation ........................................................................................................................ 22
3.2.2. Pulse frequency modulation ................................................................................................................. 23
3.2.3. Comparison between control techniques ........................................................................................... 24
3.3. Feedback isolation ..................................................................................................................................... 26
3.3.1. Magnetic isolation ................................................................................................................................. 27
3.3.2. Acoustic isolation................................................................................................................................... 28
3.3.3. Capacitive isolation................................................................................................................................ 29
3.3.4. Comparison between isolation techniques ......................................................................................... 31
3.4. List of market converters ........................................................................................................................... 32
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4. Control and stability ....................................................................................................................................... 34
4.1. PWM control .............................................................................................................................................. 34
4.1.1. Current-mode control model................................................................................................................ 35
4.1.2. Compensating the forward converter.................................................................................................. 46
4.1.3. System simulations ................................................................................................................................ 52
4.2. PFM control ................................................................................................................................................ 56
4.2.1. Determining efficiency .......................................................................................................................... 56
4.2.2. Control mode toggling........................................................................................................................... 58
4.2.3. System simulations ................................................................................................................................ 60
5. Feedback insulation ........................................................................................................................................ 62
5.1. PWM control with magnetic insulation .................................................................................................... 62
5.1.1. System simulations ................................................................................................................................ 63
5.2. PFM control with magnetic insulation...................................................................................................... 64
6. Implemented integrated circuit..................................................................................................................... 65
6.1. Soft-start ..................................................................................................................................................... 66
6.2. D Flip-Flop with triple modular redundancy ............................................................................................ 66
6.3. Digital to analog converter – ramp generator ......................................................................................... 67
6.4. 4-bit counter ............................................................................................................................................... 68
6.5. Ramp and current signal summing circuit ................................................................................................ 69
6.6. Sample and Hold circuit ............................................................................................................................. 69
6.7. PWM comparator....................................................................................................................................... 70
6.8. Error amplifier ............................................................................................................................................ 71
6.9. Implemented blocks summary .................................................................................................................. 72
7. Top simulations ............................................................................................................................................... 73
8. Conclusions ..................................................................................................................................................... 77
References .................................................................................................................................................................... 79
A. Appendices ...................................................................................................................................................... 82
A.1. Space design constrains, effects and solutions ........................................................................................ 82
A.2. Compliance table........................................................................................................................................ 83
A.3. Output specifications table ....................................................................................................................... 84
A.4. Power stage parameter design ................................................................................................................. 84
A.4.1. Transformer ....................................................................................................................................... 85
A.4.2. Inductor.............................................................................................................................................. 87
A.4.3. Capacitor ............................................................................................................................................ 88
A.5. Power stage passive component values................................................................................................... 89
A.6. List of market available DC/DC converters............................................................................................... 91
A.7. Sensitivity analysis of type-2 error amplifier............................................................................................ 92
A.8. LTSpice simulation circuit schematics ...................................................................................................... 93
A.8.1. Multiple output forward converter AC simulation schematic using the PWM-switch model .... 93
A.8.2. Equivalent single output forward converter AC simulation schematic using the PWM-switch model 93
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A.8.3. Forward converter transient PWM simulation using the PWM-switch averaged model ............ 94
A.8.4. Forward converter transient PWM simulation using switched model ......................................... 94
A.8.5. PWM switched model controller schematic ................................................................................... 95
A.8.6. PFM controller schematic ................................................................................................................. 95
A.9. Controller circuit complete block diagram ............................................................................................... 96
A.10. Two-stage operational amplifier design ................................................................................................... 96
A.11. Controller circuit parameters calculation................................................................................................. 98
A.12. Implemented blocks circuit schematics ................................................................................................... 100
A.12.1. Digital-to-analog converter .............................................................................................................. 100
A.12.2. Soft-start ............................................................................................................................................ 100
A.12.3. Sample & Hold amplifier ................................................................................................................... 101
A.12.4. PWM comparator.............................................................................................................................. 101
A.12.5. Sample clock generator .................................................................................................................... 102
A.12.6. Sample & Hold circuit ....................................................................................................................... 102
A.13. PWM controller top circuit schematic ...................................................................................................... 103
A.14. Forward converter test-bench .................................................................................................................. 104
A.15. Circuit schematic of the three output forward converter with magnetic insulation ............................ 105
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List of Figures
Figure 2.1: Temperature range and radiation in the Earth’s atmosphere. [4] ..................................................... 7
Figure 2.2: Support scheme for the converter PCB: (a) single board converter; (b) double board converter.
[6] ..................................................................................................................................................................................... 8
Figure 2.3: Vibration during a spacecraft launch with (yellow) and without (blue) vibration isolators. [7] ...... 9
Figure 2.4: Van Allen radiation belts (represented in dark gray). [10] ................................................................ 10
Figure 2.5: Sources of high-energetic particles that can cause damage to electronics. [13] ............................ 10
Figure 2.6: (a) Trapped positive charges in the gate oxide; (b) effects of trapped charges in the CV curve.
[14] ................................................................................................................................................................................. 11
Figure 2.7: Threshold voltage shifts in NMOS and PMOS technologies in respect to the TID. [15].................. 11
Figure 2.8: Trapped positive charges in the field oxide of MOS transistor technology: (a) leakage current
between two adjacent MOS transistors [18]; (b) Edge current between the source and drain [19]. .................... 12
Figure 2.9: Optocoupler CTR degradation with increasing absorbed radiation dose. [14] ............................... 12
Figure 2.10: Bipolar junction transistor working with excessive recombination due to displacement damage.
[18] ................................................................................................................................................................................. 13
Figure 2.11: List of Single Event effects. ................................................................................................................ 13
Figure 2.12: Single Transient effect in a semiconductor and a typical waveform associated. [13] .................. 14
Figure 2.13: Semiconductor before and after a Single Event Burnout. .............................................................. 14
Figure 2.14: Parasitic Thyristor created by two adjacent complementary MOS transistors. (a) Layout
schematic; (b) Parasitic thyristor junction schematic. ............................................................................................... 15
Figure 2.15: Total ionizing dose of a space station with aluminum shielding. [14] ........................................... 16
Figure 2.16: (a) Traditional integrated MOS transistor; (b) Enclosed Layout Transistor with guard ring; (c)
layout of ELT CMOS inverter (b)................................................................................................................................... 16
Figure 2.17: (a) Simple triple modular redundancy; (b) fully triplicated Triple Modular Redundancy. [5] ...... 17
Figure 3.1: Single output flyback converter. a) Circuit topology; b) Output capacitor current and input
current waveforms........................................................................................................................................................ 19
Figure 3.2: Single output forward converter. a) Circuit topology; b) Reset winding and output capacitor
current waveforms........................................................................................................................................................ 20
Figure 3.3: Voltage-mode control scheme. (a) Block diagram; (b) Example plot of control voltage (blue),
sawtooth voltage (black) and power switch driving signal (red). .............................................................................. 22
Figure 3.4: Current-mode control scheme. (a) Block diagram; (b) some characteristic waveforms (forward
converter). ..................................................................................................................................................................... 23
Figure 3.5: Pulse Frequency Modulation control diagram block ......................................................................... 24
Figure 3.6: Sketch of output voltage waveforms for PWM and PFM.................................................................. 24
Figure 3.7: The optimum transition point between PWM and PFM modes in a buck converter as a function
of input voltage and load current. [27] ....................................................................................................................... 25
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Figure 3.8: Comparison between VM and CM dynamic responses. (a) Step load transient; (b) Input voltage
transient. [25] ................................................................................................................................................................ 25
Figure 3.9: Indirect sampling magnetic feedback. (a) Flyback magnetic feedback topology; (b) Forward
magnetic feedback topology. ....................................................................................................................................... 27
Figure 3.10: a) Direct sampling magnetic feedback in a forward converter; b) Secondary circuit schematic. 27
Figure 3.11: Inductor voltage waveforms in CCM and DCM. The sample time interval is highlighted in order
to avoid ringing.............................................................................................................................................................. 28
Figure 3.12: Piezoelectric equivalent electric circuit. (a) Schematic; (b) symbol. .............................................. 29
Figure 3.13: Piezoelectric feedback isolation block diagram. .............................................................................. 29
Figure 3.14: Capacitive isolation block diagram as described in reference [32]. ............................................... 29
Figure 3.15: Capacitive isolation block diagram as described in reference [33]. (a) Main block diagram; (b) C-
element digital block in CMOS technology.................................................................................................................. 30
Figure 3.16: DC/DC step down isolated converter operated in voltage-mode control with digital capacitive
isolation. [33] ................................................................................................................................................................. 30
Figure 3.17: DC/DC step down isolated converter operated in current-mode control with capacitive
isolation. ........................................................................................................................................................................ 31
Figure 4.1: Generic block diagram of the output voltage control in closed loop with (b) and without (a)
compensator.................................................................................................................................................................. 35
Figure 4.2: Inductor current waveform for duty cycles less than 50% (a) and greater than 50% (b). [25] ...... 36
Figure 4.3: Inductor current waveforms (blue) influenced by the ramp compensation. .................................. 36
Figure 4.4: Coefficient α as a function of the duty cycle and the quotient between the compensation and off
slopes (kS)....................................................................................................................................................................... 37
Figure 4.5: Current-mode control block diagram with ramp compensation. ..................................................... 37
Figure 4.6: PWM Switch model concept. (a) Symbol; (b) Single output forward converter with the PWM
Switch model and a DC transformer simulating the real transformer. ..................................................................... 38
Figure 4.7: PWM Switch model in current-mode control in continuous conduction mode.............................. 39
Figure 4.8: Two output forward converter schematic using the PWM-switch model and cross regulation. .. 40
Figure 4.9: Multiple output forward converter model used by Prof. Basso to calculate the equivalent
inductance. .................................................................................................................................................................... 41
Figure 4.10: Secondary portion of the single output equivalent circuit to the N output forward converter
power stage. .................................................................................................................................................................. 42
Figure 4.11: Forward converter single output equivalent circuit (a) and some waveforms used in the slope
calculation...................................................................................................................................................................... 43
Figure 4.12: kS as a function of the number of cycles needed to dump the inductor current perturbation to
5% of the initial value and for different duty cycles. .................................................................................................. 44
Figure 4.13: Voltage waveform at the output of the current sensed signal amplifier....................................... 45
Figure 4.14: Comparison between bode plots of the simulated models and the theoretical analytical model.
........................................................................................................................................................................................ 45
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Figure 4.15: Transient response for different [25] ............................................................................................... 46
Figure 4.16: Type 2 amplifier circuit schematic – integrator and zero-pole pair. .............................................. 47
Figure 4.17: (a) Type 2 k-factor compensation; (b) Phase boost calculation. .................................................... 48
Figure 4.18: Compensated power stage bode plot. (a) Magnitude [dB]; (b) argument [o]. .............................. 48
Figure 4.19: Bode plot of the open loop transfer function for different values of duty cycle, without (a) and
with (b) ramp compensation (Equation (4.30)). ......................................................................................................... 49
Figure 4.20: Bode plot of the open loop transfer function for different values of output capacitance (a) and
inductance (b). The colored dots and crosses represent the frequency values of the zero and pole, respectively,
which the inductor and capacitor influence. .............................................................................................................. 50
Figure 4.21: Feedback scheme of the error amplifier with the operational amplifier single pole model........ 51
Figure 4.22: Open loop compensated transfer function for finite values of: (a) error amplifier GBW; (b) low-
frequency gain. .............................................................................................................................................................. 51
Figure 4.23: Open loop compensated transfer function after shifting error amplifier passive component
values: a) Cp; b) Cz; c) Rz. The colored dots and crosses represent the fp and fz values of equations (4.42), for the
different passive component values............................................................................................................................ 52
Figure 4.24: Output voltage during a step load transient using the PWM-switch average model (blue) and
the switched model (superimposed in green). ........................................................................................................... 53
Figure 4.25: Startup and steady state operation of a three output forward converter. (a) Output voltages
and inductor currents; (b) Output voltages and inductor current zoomed in 20 switching cycles. ....................... 53
Figure 4.26: Step load transient of 40% of maximum output current and respective output voltage response.
Above: the output current plot; below: the output voltage plot. ............................................................................. 54
Figure 4.27: Mainly and cross regulated output voltages transient response to a step load in the main
output, for different input voltage levels. ................................................................................................................... 55
Figure 4.28: Output voltage response for a step load transient in the 4.5 V output. ........................................ 55
Figure 4.29: Output voltages, main output inductor [I(Ls1)] and load currents [I(S1)] during load steps in
DCM conditions. ............................................................................................................................................................ 56
Figure 4.30: Input voltage source (red) and output voltage (blue) during input source transient steps. ........ 56
Figure 4.31: Power MOSFET model and symbol used in efficiency calculation simulation............................... 57
Figure 4.32: Efficiency vs. Output load power for input voltage equal to 28 V.................................................. 57
Figure 4.33: Output voltage plot of a buck converter toggling between PWM and PFM modes. [3] .............. 58
Figure 4.34: PFM flag generation circuit schematic. ............................................................................................ 59
Figure 4.35: PFM flag generation waveforms. ...................................................................................................... 59
Figure 4.36: Main output step load transient in PFM mode. Main output voltage (red) and main output
current (green); power transistor current (blue)........................................................................................................ 60
Figure 4.37: Control circuit block diagram featuring PWM and PFM operation and toggling circuit............... 61
Figure 4.38: Simulation results showing toggling between PWM and PFM modes........................................... 61
Figure 5.1: Magnetic insulation circuit schematic. ............................................................................................... 62
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Figure 5.2: Forward converter operating with magnetic feedback. a) Output voltage with (green) and
without (red) magnetic insulation; b) Output voltage undershot detail: S&H capacitor voltage (red), output
voltage (green) and S&H switch control signal ........................................................................................................... 63
Figure 5.3: PFM mode with magnetic feedback. Output voltage (red) and the S&H capacitor voltage (green).
........................................................................................................................................................................................ 64
Figure 5.4: Forced PFM mode with magnetic feedback. Each 4µs the power MOS is turned ON just to sample
the output voltage. Green is the output voltage and blue is the gate to source voltage in the power MOSFET. . 64
Figure 6.1: a) Startup circuit schematic; b) Reference voltage waveforms during startup. .............................. 66
Figure 6.2: a) D Flip-Flop schematic with reset functionality; b) D Flip-Flop with triple modular redundancy.
........................................................................................................................................................................................ 67
Figure 6.3: D-Flip-Flop waveforms in counter topology. Red: input clock; green: D output; violet: negated D
output; blue: reset signal; purple: power down signal .............................................................................................. 67
Figure 6.4: (a) Digital to analog converter circuit schematic; (b) corner simulations of the vramp signal for
Rramp = 464 Ω. ................................................................................................................................................................. 67
Figure 6.5: a) 4-bit counter circuit schematic; b) transient simulation waveforms. .......................................... 68
Figure 6.6: Averaging circuit used to implement a sum. ...................................................................................... 69
Figure 6.7: (a) Sample and hold circuit schematic; (b) Two-stage operational amplifier circuit schematic..... 69
Figure 6.8: AC simulation exhibiting the open loop characteristic of the S&H amplifier for various corners. 70
Figure 6.9: (a) PWM comparator topology; (b) Upmost wind represents the input voltages; the windows
bellow show three different output signals for three different corners (red represents the worst case, yellow
the nominal and green the best base)......................................................................................................................... 71
Figure 6.10: AC simulation exhibiting the open loop characteristic of the error amplifier for various corners.
........................................................................................................................................................................................ 71
Figure 7.1: Top simulation results.......................................................................................................................... 73
Figure 7.2: Top simulation results – detail of a load step transient with input voltage of 28 V. ...................... 74
Figure 7.3: Top simulation results – detail of a load step transient with input voltage of 21 V. ...................... 74
Figure 7.4: Pad, bonding wire and pin model uses in top simulation. ................................................................ 75
Figure 7.5: Top simulation results with bonding wire models, except for supply and ground pads. ............... 76
Figure A.1: Three output forward converter with cross-regulation. ................................................................... 84
Figure A.2: Transformer generic geometry used to calculate the inductance and number of turns. .............. 86
Figure A.3: Output inductor current (a) and voltage (b) waveforms in one switching period. ......................... 87
Figure A.4: Sketch waveform of the capacitor current (a), output current (b) and capacitor voltage (c),
during a load step transient. ........................................................................................................................................ 89
Figure A.5: Small signal model of the two-stage OTA with compensation. ........................................................ 96
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List of Tables
Table 1.1: Output specification table from the European Space Agency ............................................................. 4
Table 3.1: Flyback converter advantages and disadvantages. ............................................................................. 19
Table 3.2: Forward converter advantages and disadvantages. ........................................................................... 20
Table 3.3: Comparison between studied benchmark topologies. ....................................................................... 21
Table 3.4: Comparison between studied DC/DC converter control techniques. ............................................... 26
Table 3.5: Comparison between studied galvanic isolation techniques. ............................................................ 32
Table 6.1: Implemented blocks summary table presenting the obtained relevant circuit parameter values.
The shaded lines are referent to blocks that were implemented in previous works on this subject. .................... 72
Table A.1: Transformer design values used for the parameter calculation. ....................................................... 90
Table A.2: Transformer parameter values. ........................................................................................................... 90
Table A.3: Output passive component values....................................................................................................... 90
Table A.4: Transistor and compensation capacitance values for the designed two-stage operational
amplifiers. ...................................................................................................................................................................... 98
Table A.5: Controller circuit calculated parameter values. .................................................................................. 99
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List of Acronyms
CCM Continuous conduction mode
CM Current-mode
CME Coronal mass ejection
CTR Current transfer ratio
DCM Discontinuous conduction mode
DD Displacement damage
ELT Enclosed layout transistor
EMI Electromagnetic interference
ESA European Space Agency
ESL Equivalent series inductance
ESR Equivalent series resistor
GBW Gain-bandwidth product
IST Instituto Superior Técnico
IT Instituto de Telecomunicações
LET Linear energy transfer
NASA National Aeronautics and Space Administration
OPAMP Operational amplifier
OTA Operational transconductance amplifier
PCB Printed circuit board
PFM Pulse frequency modulation
PT Piezoelectric transformer
PWM Pulse width modulation
RHBD Radiation hardening by design
RILC Radiation induced leakage current
S&H Sample and hold
SEBO Single event burnout
SEE Single event effect
SEFI Single event functional interrupt
SEGR Single event gate rupture
SEL Single event latchup
SEPIC Single ended primary inductance converter
SET Single event transient
SEU Single event upset
SMD Surface mount device
TID Total ionizing dose
UTL Universidade Técnica de Lisboa
V2 Voltage-voltage
V2C Voltage-voltage-current
VM Voltage-mode
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List of Symbols
Transformer winding inductance of winding ‘i’ [H]
Transformer winding resistance of the winding ‘i’ [Ω]
Inductor current perturbation [A]
Output current transient variation [A]
Output voltage variation due to load step [V]
Conductor total section area [m2]
Effective transformer cross section area [m2]
Conductor effective conduction area [m2]
Maximum transformer magnetic flux density [T]
Capacitance value of output ‘i’ [F]
PWM Switch subharmonic oscillation capacitor value [F]
Maximum duty cycle
Minimum duty cycle
Open loop crossover frequency [Hz]
Frequency of the pole introduced by a type-2 amplifier [Hz]
Switching frequency [Hz]
Frequency of the zero introduced by a type-2 amplifier [Hz]
Open loop power stage gain at the crossover frequency (linear)
PWM Switch active port current [A]
Output capacitor current [A]
PWM Switch common port current [A]
Inductor current [A]
Maximum output current of output ‘i’ [A]
Maximum value of the primary inductance current [A]
Peak value of the primary inductance current [A]
CM control inner current loop steady state gain
Portion of the maximum load at which PFM is preferable to use
Quotient between the compensation slope and the OFF time slope ⁄
Safety margin constant
Maximum relation between the OFF time slope and compensation slope
Inductance value of output ‘i’ [H]
Transformer winding ratio of winding ‘i’
Number of wound transformer turns of the ‘i’ winding
Number of wound turns of the primary winding
Reset winding ratio
Charge supplied by the output capacitor during a positive step load transient [C]
Output parasitic equivalent series resistance value [Ω]
Conductor radius [m]
Load resistance value of output ‘I’ [Ω]
Power switch current sensing resistor value [Ω]
Compensation slope [V/s]
Magnetizing current slope [A/s]
Falling inductor current slope during OFF time [A/s]
Rising inductor current slope during ON time [A/s]
Rising primary inductance current slope during ON time [A/s]
Voltage rising slope sensed by the current sensing resistor [V/s]
Converter response time to load step [s]
Switching period [s]
Maximum Input voltage [V]
Minimum input voltage [V]
Diode 1 anode to cathode voltage [V]
Diode 2 anode to cathode voltage [V]
PWM Switch active to passive port voltage [V]
Control voltage [V]
PWM Switch common to passive port voltage [V]
Power voltage of CMOS logic [V]
Power switch gate driving voltage [V]
Average voltage drop across the diodes and parasitic resistances considered in transformer relation calculation [V]
Power switch maximum tolerable reverse drain to source voltage [V]
Offset voltage added to the CM control PWM comparator positive input, putting it under its linear region [V]
Current sampling signal [V]
Sensed current signal value for optimal PFM toggling [V]
ii
Voltage across the output inductor [V]
Output voltage [V]
Overdrive voltage of MOS transistors [V]
Output nominal voltage of output ‘i’ [V]
Output maximum voltage of output ‘i’ [V]
Pulse signal feed the Latch Set input [V]
Voltage signal feeding the positive input of the CM control PWM comparator [V]
Ramp compensation voltage signal [V]
Reference voltage [V]
Sawtooth voltage signal [V]
Error voltage [V]
Copper resistivity temperature coefficient [oC-1]
Forward converter voltage efficiency
Relative magnetic permeability of ferrite [H/m]
Absolute magnetic permeability of vacuum [H/m]
Subharmonic oscillations fundamental
angular frequency [turns/s]
Effective transformer/inductor length [m]
Transformer/inductor single wound turn conductor length [m]
Copper resistivity at 125 oC [Ω.m]
Step load time interval [s]
Output voltage ripple of output ‘i’ [V]
Duty cycle instantaneous value
Number of outputs of a generic forward converter
Nominal input voltage value [V]
Skin effect depth [m]
Temperature value [oC]
Absolute magnetic permeability [H/m]
Voltage feedback static gain
Relation between a circumference perimeter and radius,
k-factor parameter
3
1. Introduction
1.1. Overview
DC/DC converters are high efficiency power supplies that transform a time continuous voltage level into a
different voltage level, utilizing semiconductor devices switching at high frequencies and passive filtering.
These types of converters have become essential in diverse applications as power supplies for electronic
circuits, such as sensors, data acquisition systems and telecommunication systems and most recently in grid
connected renewable energy power supply systems and in electric vehicle’s motor control.
The Aerospace Industry, as a strong user of electronic circuitry, is an example of an application that does not
exempt the usage of these converters with high efficiency. The main source of energy in these applications is
Photovoltaic Cells or Radioisotope Thermoelectric Generator, for when the Sun’s radiation is scarce. Both of
these power supplies generate energy at voltage levels higher than what electronics can withstand, hence
there is a need to use DC/DC converters to regulate and lower the voltage level, while maximizing efficiency.
However, the design of such circuits for space applications is significantly more complex than in terrestrial
applications. Problems due to the harsh and extreme environments, like cosmic radiation, electromagnetic
interference (EMI), vacuum and high temperature gradients make these circuits extremely challenging to
design.
In addition, current efforts are made to reduce the load of a spacecraft as far as possible, in order to reduce
the weight, reducing fuel needed, making the spacecraft project cheaper. In this sense, an increasing need on
integrating and miniaturizing controller circuits for power supplies is observed. However, designing special
techniques for integrated circuits to tolerate radiation is expensive, and currently the “Sate of the Art” circuits
are not tested to work in such conditions. On the other hand, circuits that were tested to withstand radiation
are becoming slowly outdated.
In this context the European Space Agency (ESA) in the past recent years has been compelled to resort the
North American market of control circuits for these power converters, due the supply in Europe territory being
low or even non-existent. Unfortunately this kind of electronic circuits has military applications, making it
difficult to be purchased, since the importation of this material must pass a long chain of bureaucracy imposed
by the United States Ministry of Defense. This not only causes costs to increase, but also slows the spacecraft
project, delaying the launch date, which sometimes can eventually compromise the entire project.
In order to solve this problem, ESA is now looking for an integrated control circuit for DC/DC converters
totally “made in Europe” to prevent such delays in spacecraft launches and also to reduce import costs. This
controller must be completely integrated, radiation tolerant, with complete galvanic isolation between input
and outputs and with minimal costs, but also maximizing the overall converter efficiency.
4
1.2. System specifications
The electrical specifications are presented in the table below. Note that there are two different power
ratings (3 and 10 W) and two different input voltage levels (28 and 50 V), creating a total of four specified
converters. However, this dissertation will focus on the design of the 3 W and 28 V converter. The design
procedure for the remaining three converters is analogous.
Table 1.1: Output specification table from the European Space Agency
Output Voltage
Parameter Symbol Total output power
3 W 10 W
5.0 V
Control type - Regulated output
Load ,
0.02 to 0.60 A 0.02 to 2.00 A
Output voltage tolerance ,
2% (4.90 to 5.10 V)
Output voltage ripple (low frequency) 50 mVpp
Output voltage ripple (high frequency) - 100 mVpp
Step load transient output voltage variation*
0.3 V
4.5 V
Control type - Cross-regulated output
Load ,
0.07 to 0.67 A 0.07 to 2.22 A
Output voltage tolerance ,
10% (4.05 to 4.95 V)
Output voltage ripple (low frequency) 100 mVpp
Output voltage ripple (high frequency) - 150 mVpp
Step load transient output voltage variation*
0.25 V
3.5 V
Control type - Cross-regulated output
Load ,
0.03 to 0.86 A 0.10 to 2.86 A
Output voltage tolerance ,
10% (3.15 to 3.85 V)
Output voltage ripple (low frequency) 100 mVpp
Output voltage ripple (high frequency) - 150 mVpp
Step load transient output voltage variation*
0.2 V
* Load step of 40% of max load with a slew rate of no less than 1 A/µs
1.3. Objectives
The purpose of this dissertation is to resume and improve the development already done regarding the
control circuit design for the DC/DC converter. In order to achieve this, the following dissertation will focus on
addressing the following issues:
Implementation of galvanic insulation that constitutes the feedback block for the regulated
output voltage;
Re-study the stability in closed loop in PWM mode to ensure a proper dynamic behavior under
load steps;
Study the need and the feasibility of PFM mode and improve the transient response when
alternating from PWM to PFM mode, and vice-versa;
Design an integrated circuit implementing the studied features;
Simulate the circuit, presenting the results and validating its functionality.
5
1.4. Terminology
For this document to be understood by as many readers as possible and to ensure symbolic coherence,
some notation rules will be taken in consideration, in which are presented below:
System of measurement: metric system.
Signal representation:
o Time variant signal: lower case.
o Signal DC component: lower case with
overbar.
⟨ ⟩
∫
o Signal AC component: lower case with
tilde.
⟨ ⟩
Laplace transform of a signal: capital letter.
∫
Sensitivity of a parameter in respect to a
design variable:
Voltage drop arrow: from higher to lower
voltage.
+ -VR
Parallel operator:
II
1.5. Design tools
Several software tools were used for the development of this dissertation. Below is presented a list of the
software used and for what purposes:
LTSpice: to perform system simulations of circuit topologies under study, such as the feedback
isolation circuit and to analyze closed loop stability of the whole converter model;
MATLAB: to perform complex mathematical computations and graphical plots of relevant quantities;
CADENCE: to perform all the microelectronic project design at electric schematic and layout levels and
to validate the requisites though Spectre or Ultrasim electric simulation.
6
1.6. Structure
This dissertation includes the following six chapters:
Chapter 1 provides a brief introduction, framing the reader into the subject and describing the
challenge that is to make microelectronics projects to operate in space. The thesis objectives are
listed, along with its structure and terminology used.
Chapter 2 lists the various stresses endured by integrated electronic systems in space environment. It
is also presented some possible solutions to mitigate these stresses.
Chapter 3 covers the state of the art regarding power stage topologies, control and feedback isolation
methods.
Chapter 4 comprises the study done regarding control and stability of the DC/DC converter, in
particular a detailed explanation on how the DC/DC converter is compensated in PWM mode. The
viability of PFM mode is also studied in this chapter.
Chapter 5 includes the explanation on how the feedback insulation will be implemented with both
PWM and PFM control modes.
Chapter 6 presents the list of some of the blocks implemented for this work.
Chapter 7 presents the top simulation results validating the implemented integrated circuit.
Chapter 8 finalizes this dissertation pointing out the most important conclusions and proposed future
improvements to the circuit functionality.
7
2. Electronics in space environment
This chapter presents various issues that affect electronic circuits in space environment and what are their
effects, especially in the DC/DC converters and controller integrated circuits under study. Among the following
presented issues, this study will mainly focus on problems derived from radiation, because it is the most
difficult phenomenon to mitigate and its effects are more damaging to electronic circuits. A summary table
presented electronic design constrains in space environment can be found in Appendix A.1.
2.1. Temperature
The converter in project must be able to operate over a large range of temperatures, depending on assigned
the spacecraft location. In an orbit around a planet, the spacecraft may experience changes in temperature
when moving from shadow to light or when entering atmosphere regions with different temperatures. Figure
2.1 shows the temperature in the Earth’s atmosphere in respect to altitude.
Figure 2.1: Temperature range and radiation in the Earth’s atmosphere. [4]
At altitudes between 100 and 500 km the average atmospheric temperatures range between approximately
100 and 1200 K (-170 and 900 oC), meaning that the behavior of a semiconductor device is highly affected.
Some semiconductor characteristics like quiescent currents, speed of response and threshold voltages can
experience significant variations when expose to abrupt temperature transients. Apart from that, these
transients cause materials to expand and contract, leading eventually to mechanical rupture.
2.1.1. Solution
Controlling the temperature within the spacecraft is critical to avoid component destruction or to prevent
variations in component parameters. Even if the temperature is controlled, the electronics have to be design to
support a wide range of temperatures, especially much colder temperatures than measure on ground earth. [5]
8
Assuming that the spacecraft has its own temperature control, the implemented circuitry will be designed
and simulated to withstand temperature values within the -50 to 125 oC limits.
2.2. Vacuum
The absence of an atmosphere can cause some materials to decompose or degrade, reducing their
operational life time. Materials manufactured at the surface atmospheric pressure may explode when
subjected to very low pressures. [5]
The heat sink is also a problem, since cooling in the form of convection cannot be used in vacuum due to no
atmosphere being present in space.
2.2.1. Solution
Electrolytic capacitors cannot be used in aerospace industry, since there is a high risk of explosion. However
ceramic or tantalum capacitors are a viable alternative.
The refrigerating system must be designed to dissipate energy by radiation and possibly also by conduction.
The material used in the support points that attach the converter’s PCB to the spacecraft has to be designed
with high heat conductivity, in order for heat to be dissipated by conduction. Installing thermal radiators near
the electronic circuits is also advised.
2.3. Shock and vibration
Vibration observed in the spacecraft launch and shocks from pyrotechnic deployments may introduce
mechanical stress in the circuitry. Circuits have to be mechanical resistant to these stresses. [5]
2.3.1. Solution
To reduce the stresses during launch the PCB has to be fixated to the spacecraft using five support points.
This mechanical support scheme distributes uniformly the forces applied to the board. The support points also
must be made of a shock resistant material. Figure 2.2 shows two possible schemes to fixate the PCB, whether
it has one (a) or two circuit boards (b).
(a) (b)
Figure 2.2: Support scheme for the converter PCB: (a) single board converter; (b) double board converter. [6]
Surface mount components (SMD) are preferred since they occupy less space and also benefit from higher
mechanical resistance. Proper vibration and shock isolation using mechanical dampers are a viable solution to
diminish vibration at the resonant frequency of the PCB material. Figure 2.3 illustrates an example of the
vibration a spacecraft suffers during launch, with and without vibration isolators.
9
Figure 2.3: Vibration during a spacecraft launch with (yellow) and without (blue) vibration isolators. [7]
2.4. Electromagnetic inference
Electromagnetic interference can cause signal degradation and therefore may induce errors in control
circuits due to appearance of excessive unwanted noise. Radio frequency telecommunications can also be
accounted for magnetic interference in open space. [8] [9]
The converter circuit not only is a victim of external electromagnetic interference (EMI), but it is also a
source of high EMI, especially when it has multiple outputs with each one with his own transformer winding
and filtering coil. The high switching frequency causes these magnetic components to create enough EMI to
affect nearby circuits.
2.4.1. Solution
To mitigate the EMI in the converter an input filter can be added, but with the risk of degrading the
converter’s stability if not accounted for. As far the PCB design is concerned, it is preferable to use the shortest
possible strip lines length and also ensure small loops. This reduces parasitic inductances that are responsible
for crosstalk.
2.5. Radiation
Although the previous outer space problems are important and must be accounted for, radiation exposure
becomes a much more severe issue, since it can affect directly and immediately the circuit performance.
2.5.1. Sources of radiation
Electronics in spacecraft are exposed to radiation from several natural sources, which mainly can be sorted
within two groups:
Trapped Radiation composed by charged particles (energetic electrons and protons) confined in
magnetic fields around planets, also called radiation belts. Figure 2.4 shows the Earth’s radiation belts, denominated “Van Allen radiation belts”.
Transiting Radiation associated with subatomic particles originating from outside of the solar system,
called Cosmic Rays and also from the Sun, in the form of high-energy plasma bursts, emitted
10
occasionally from solar flares and coronal mass ejections (CME), or lower energy plasma, also known as
solar wind.
Figure 2.4: Van Allen radiation belts (represented in dark gray). [10]
Galactic cosmic rays are constituted mostly by protons (85%), alpha particles (14%) and heavy nuclei (1%).
On the other hand, solar wind and solar flares are primarily composed by X-rays, heavy ions and subatomic
particles. Solar flares correspond to instants where the tension built up by the Sun’s magnetic field is locally
released, briefly increasing the solar wind density. They occur with more intensity near the first and last year of
the solar maximum. This period lasts up to 7 years and occurs every 11 years, corresponding to sun spot cycle.
Figure 2.5 summarizes all the previous radiation sources. [11] [12]
Figure 2.5: Sources of high-energetic particles that can cause damage to electronics. [13]
2.5.2. Effects of radiation in electronics
The previously mentioned sources of radiation can cause two distinct types of effects in electronics:
Cumulative effects caused by the accumulation of charged particles on the surface and dielectric
layers over the whole operational life of the exposed electric circuits;
Single event effects (SEE) happen when heavy ions or protons strike sensitive junctions in
semiconductors or certain critical electrical nodes.
a) Cumulative effects Unlike Single Event Effects, cumulative effects persist even when the spacecraft is not exposed to radiation
and its effects became more noticeable the longer the spacecraft is exposed. Cumulative effects can be
measured in two different ways according to the source of the damage, whether it is an ionizing or a non-
ionizing effect. Due to its time of exposure dependent nature, the cumulative effects are described by the
mean time to failure (MTTF). This indicates how much time the device can withstand a certain level of radiation
exposure before it cease to function.
Radiation
Trapped Transiting
Solar Flares Galactic Cosmic
Rays
11
i. Total Ionizing Dose
The Total Ionizing Dose (TID) is measure of how much energy is absorbed by the circuitry at a given time
instant and it is expressed in rad1. Cumulative effects caused by ionizing damage are measured by the TID
which indicates the long term damage caused by protons and electrons in the electronic components. An
electronic device can be compromised when the accumulated TID exceeds its tolerance, so it is possible to
estimate when the component failure will happen, knowing the rate of radiation exposure.
When a charged particle transit through the insulating oxide of a MOS transistor’s gate (gate thin oxide), its
energy is absorbed, sometimes causing the ionization of a SiO atom. Long term exposures to radiation increase
the density of atoms ionized by this effect, creating an excess of positive charges initially not present. These
charges would not be detrimental to transistor’s operation since the flow of electric current would remove
them from the oxide. However, the holes (positive charges resembling gaps of electrons) mobility is
approximately four times lower than the electron’s, causing the oxide to trap the excess of positive charges.
(a)
(b)
Figure 2.6: (a) Trapped positive charges in the gate oxide; (b) effects of trapped charges in the CV curve. [14]
Figure 2.7: Threshold voltage shifts in NMOS and PMOS technologies in respect to the TID. [15]
The trapped charges can alter the equivalent gate capacitance, meaning that the design of CMOS gates to
operate as a capacitor has to take into the account changes in the CV curve (capacitance versus gate voltage).
These trapped charges also cause the transistor’s channel between drain and source to be established whether
or not a gate voltage is applied. This phenomenon causes variations in the threshold voltage, leading to a loss
of control over the transistor’s state. The threshold voltage shifts can vary according to whether the transistor
is NMOS or PMOS technology, although PMOS shows to have a bigger threshold voltage shift in most
technologies. [16]
1 1 rad = 100 J/kg
12
In addition to the previous effects, the trapped charges also cause the oxide gate to lose some of its
properties as an insulator, thereby reducing the gate resistance, leading to the emergence of leakage currents.
The field oxide between transistors is also affected, contributing to not only the appearance of leakage currents
between two adjacent transistors, but also in between the source and drain of one transistor. In this case the
current leaks where the thin and the field oxide meet, creating the denominated edge or beak currents. The
previous effects are known as Radiation Induced Leakage Currents (RILC) and are illustrated in Figure 2.8. [17]
a)
b)
Figure 2.8: Trapped positive charges in the field oxide of MOS transistor technology: (a) leakage current between two adjacent MOS transistors [18]; (b) Edge current between the source and drain [19].
Bipolar technologies are also highly affected by trapped charges allocated near the base region. The main
observable effects are gain (hFE) degradation, increased leakage current through the base and higher leakage in
the off state. There have been also reports of several problems with DC/DC converters in space due to the
optocoupler use [20]. Figure 2.9 illustrates optocoupler transfer ratio (CTR) degradation due to long term
radiation exposure.
Figure 2.9: Optocoupler CTR degradation with increasing absorbed radiation dose. [14]
ii. Displacement damage Non-ionizing damage due to colliding protons, electrons and neutrons cause displacement damage (DD).
This effect is more predominant in bipolar junction technologies. Colliding charged particles alter the junction
molecular structure, creating additional holes that recombine with electrons when the transistor is biased. This
recombination excess reduces the collected current, and therefore it lowers the transistor gain. Eventually the
gain is too low and the device ceases to work.
13
Figure 2.10: Bipolar junction transistor working with excessive recombination due to displacement damage. [18]
Displacement damage has also been one of the higher causes for failure of power converters in space, due
to optocoupler degradation. The gain reduction of both the light emitting diode and the phototransistor has
caused several earlier than expected operating failures, when the design did not consider displacement
damage. [14]
b) Single Event Effects
Single Event effects (SEE) occur when a single charged particle collides with the component, depositing its
energy in the electronic device. This event can happen at any moment, so electronics sensitive to SEE can fail at
any given instant when exposed to radiation. This makes it difficult to predict when component failure will
occur, thus a circuit hardness to SEE is characterized by a random failure rate. These effects are not cumulative,
meaning that if the spacecraft is no longer exposed to radiation, SEE stop occurring.
Figure 2.11: List of Single Event effects.
In Figure 2.11 it is summarized the list of possible non-cumulative effects caused by radiation. They can
cause three different of effects:
Transient effects which modify briefly the device’s response for the duration of the event in the
form of a spurious signal that propagates through the circuit;
Static effects when the state of transistor is changed, leading to a possible corruption of data
stored;
Permanent effects that lead to the circuit’s destruction.
i. Transient Effects
Transient effect is the name given to temporarily spikes or signals caused by the energy of a particle that is
deposited on a semiconductor. They cause transient shits in voltages that sometimes can trigger changes in
logic levels, allowing the propagation of an error to an entire logic circuit. However, this level of stress that is
Single Event Effects
Transient
Single Event Transients
Static
Single Event Upset Single Event Functional Interrupt
Permanent
Single Event Latchup
Single Event Burnout
Single Event Gate Rupture
14
imposed on the circuit is not enough to permanently damage it. Figure 2.12 shows the cause of transient and a
typical waveform generated by it.
Figure 2.12: Single Transient effect in a semiconductor and a typical waveform associated. [13]
ii. Static effects
Static effects have the same source as transients but they can cause a change in stored memory state (Single
Event Upset, SEU), or even interrupt the circuit operation (Single Event Functional Interrupt, SEFI).
Single Event Upsets happen when a bit or state changes in a logic circuit, due to a charged particle colliding
with a circuit node. If this collision is critical or enough of these upsets happen, the electronic circuit can freeze
and must be rebooted in order to operate again.
Single Event Functional Interrupts are the worst case of an upset, and happens to circuits with multiple logic
blocks that are highly dependent with each other. A certain number of “bit-flips” can cause a block to stop
working and all other dependent blocks to be influenced too.
To quantify the ability of a circuit to resist the static effects the concept of Linear Energy Transfer (LET) was
defined. This measure is usually taken as a design specification and informs how much energy per area density
a circuit can withstand when a particle collides. This quantity is measured in MeV.cm2/mg.
iii. Permanent effects
Effects which cause the circuit to be permanently compromised or destroyed are called Permanent effects.
These events are triggered by heavy ions that transit through semiconductors and their energy is transferred to
the circuit, although significantly higher than in transient or static effects. There are three types of permanent
effects: Single Event Burnout (SEBO); Single Event Gate Rupture (SEGR) and Single Event Latchup (SEL).
Figure 2.13: Semiconductor before and after a Single Event Burnout.
Single Event Burnout happens when an ion passes in a transistor at cutoff state, generating a transient
current, which causes transistors to be biased in reverse, permanently destroying the device. P-channel
MOSFETs are much less sensitive to burnout than NMOS because the current positive feedback observed
15
during reverse bias is due avalanche effect. SEBO affects mostly power transistors such as MOSFET, BJT and
power diodes. The greater the reverse voltage is the most destroying its effects are. [16]
Single Event Gate Rupture is observed when a MOS transistor is in OFF state with a large bias voltage. When
a heavy ion hits the gate it leads a trail of charged particles that can cause the disruption of the oxide,
destroying the device. Once again like in SEBO, power MOSFETs are highly sensitive to this event, especially
those with high reverse bias voltages.
In integrated MOS technologies adjacent complementary transistors can form a parasitic circuit that is
equivalent to a thyristor, a semiconductor junction component with four layers like p-n-p-n (Figure 2.14). When
struck by a heavy ion, this thyristor is biased generating a feedback current loop, leading to a Single Event
Latchup. If there is no mean of control in the input current, this positive feedback mechanic can cause the
permanent destruction of the device.
(a)
P+
N
P
N+
+
(b)
Figure 2.14: Parasitic Thyristor created by two adjacent complementary MOS transistors. (a) Layout schematic; (b) Parasitic thyristor junction schematic.
2.5.3. Solution
In order to solve or mitigate the undesired effects originated by radiation there can be two different
approaches on the subject. Modifications can be made to completely eliminate the effects of radiation or when
this is not possible, special techniques can be used to mitigate radiation effects. These two different
approaches can be made either at project level, when changes are made regarding the structure of the circuit
blocks, or at layout level, when changes are made at the how the basic devices such as transistors are designed.
a) Cumulative effects To mitigate the effects of ionizing cumulative damage, electronic circuitry can be protected with metallic
enclosures that shield the components if the spacecraft own shielding is not sufficient. Aluminum shields can
prove somewhat efficient in blocking the incoming radiation, like Figure 2.15 shows:
Using aluminum to protect circuits in addition to the spacecraft normal shields increases weight of the
spacecraft and thus increasing the fuel needed and the overall cost of the circuit project. Figure 2.15 suggest
that incrementing the shield thickness offers diminishing returns in radiation shielding. An alternative way to
mitigate the radiation effects is known as radiation hardening by design (RHBD). This approach relies only on
circuit design techniques to mitigate the damage caused by space radiation. For example the edge leakage
currents induced by radiation can be significantly reduced if the transistors in an integrated CMOS technology
are designed with alternative geometries to the standard.
16
Figure 2.15: Total ionizing dose of a space station with aluminum shielding. [14]
One possible solution is to use Enclosed Layout Transistors (ELT). This geometry eliminates edges between
the gate oxide and the field oxide, by means of a radial polygonal shape transistor. The source is placed in the
center, followed by a ring shaped channel, which is surrounded by the drain ring. The current flows radially
from the center to the exterior reducing the possibility of leakage currents to form.
With this technique is also possible to isolate two adjacent transistors by adding a guard ring around the
drain, as shown in Figure 2.16. This effectively reduces the leakage currents between two transistors and
increases Linear Energy Transfer resistance. The overall area occupied by an ELT transistor is significantly larger
than with standard designs. This causes the parasitic capacitances to increase, leading to more power
consumption, which is a suitable price to pay for proper radiation hardening. [21]
GateSource
Drain
Guard Ring
Drain
Gate
Source
(a) (b) (c)
Figure 2.16: (a) Traditional integrated MOS transistor; (b) Enclosed Layout Transistor with guard ring; (c) layout of ELT CMOS inverter (b).
Decreasing the thickness of the thin silicon oxide in the gate can improve the resistance to radiation dose, by
giving charges less space to accumulate. However, this leads to an increase in gate capacitance, increasing the
propagation delay in a logic gate and decreasing the power efficiency.
If there is a need to have DC isolation in a circuit, optocouplers can be problematic to use thanks to their
high sensitivity to displacement damage and TID. Another means to implement the galvanic isolation must be
developed.
Passive components have also to be carefully chosen to operate in space. There are some devices that, due
to their immunity to radiation, can be used without restrictions in aerospace environment, such as: poly
resistors; poly-poly, fringe and metal inter metal capacitors; inductors and transformers. [22]
17
Digital blocks that have more than three transistors in series are also forbidden due to the possibility of
threshold voltage shifts overly affecting the circuit expected behavior.
b) Transient and static effects In a given circuit when steady state current levels are low, the effects of transients become noticeable thus
making it imperative to apply measures to prevent or remedy possible errors. Any branch in an analog circuit
must have a minimum of 2 to 5 µA in order to transient current spikes caused by particles to be considered
negligible.
(a)
(b)
Figure 2.17: (a) Simple triple modular redundancy; (b) fully triplicated Triple Modular Redundancy. [5]
In digital circuits Modular Redundancy can be used to ensure data is not corrupted or lost. Using this
mechanism, if one digital gate is targeted by a SET, other two identical circuits will ensure the redundancy. A
possible implementation of this method is shown in Figure 2.17 (a). The three different flip-flops without errors
will have the same outputs. A voter logic circuit is placed after the flip-flops to ensure that if one of these has
an error, and if the other two keep working as intended, the output of the entire block is not affected.
However, if the voter circuit is the one to be affected by the SET the output would be compromised as well. In
order to solve this, the voter circuits must also include redundancy, as shown in Figure 2.17 (b). This
implementation would surely be more robust to most SET but at a cost of larger integrated circuit areas and
lower power efficiency due to more additional logic elements consuming power. [5]
Static effects such as SFI can be mitigated by reducing the dependency between multiple blocks. The
Triple Modular Redundancy (Figure 2.17) can work as well to mitigate Static effects in digital circuits. [5] [18]
c) Permanent effects Since permanent effects are caused by heavy ions, shielding provided by the spacecraft own metal shields
or, for more sensitive devices, own circuit shielding can prevent most of the these effects.
The converter power stage topology must also ensure that there is no way to short circuit the input source
by having two or more semiconductors conducting at the same time caused by a particle collision. This implies
that there can only be one power transistor between the source and the return path.
Increasing the distance between complementary devices, using guard rings and having an input current
limitation circuit can solve the latchup and burnout effects.
The thickness of the gate oxide can be increased along with reducing bias voltage, to reduce the chance of
gate ruptures to happen, at the cost of higher complexity in driving circuits and more power consumption. [16]
18
3. State of the Art
This chapter will present the state of technology development to be employed in this dissertation. Firstly the
power stage circuit is analyzed and a list of benchmark topologies is presented. In order to choose the
appropriate topology for this application, the design specifications imposed by ESA were taken in special
consideration. These specifications include not only the standard electrical requirements (such as output
voltage ripple, total output power, etc.), but also reference the design constrains that must be respected for
electronics to operate in space.
Afterwards multiple implementation solutions for the control circuit are presented, taking into account
recent technological developments in analogue implementations. After this, three different solutions regarding
the feedback isolation will be presented and compared. And lastly, a list of DC/DC converters manufactured for
commercial use is presented. This will allow the comparison of some characteristics that can contribute for
improvements in the architecture under study.
3.1. Power stage circuit
In order to choose the power stage circuit topology it is necessary to take into consideration the following
ESA design specifications:
1. Galvanic isolation of any input connection to any output;
2. Three independent outputs;
3. Input to output voltage ratio;
4. Immunity to single event effects, such as SEBO and SEGR.
The first specification above puts aside any converter topology that does not include a transformer, as this
component is the only way to guarantee galvanic isolation of power converters. Transformers also enable the
existence of multiple outputs by adding additional windings around the same iron core. If the input voltage is
too high comparing to the output voltages, without a transformer the duty cycle is limited to low values, which
can become problematic if the input voltage increases above its nominal value. The forth specification requires
that between the input source and the return path, there cannot be more than one transistor connected in
series or parallel, so the risk of radiation induced short circuit is reduced.
The previous statements thereby exclude many benchmark topologies, remaining only the following:
Flyback converter;
Forward converter;
Isolated SEPIC converter;
Isolated Ćuk converter.
19
3.1.1. Flyback converter
The flyback converter can be obtained replacing the inductor of a buck-boost converter by a transformer
primary winding and with the secondary winding connected in opposite direction. Having only one switch to
control, this converter can assume two states of operation:
When S is conducting and the diode is in cutoff, the transformer’s secondary is in open circuit. The
primary winding acts like an inductor and the input source transfers energy to the transformer raising its
voltage approximately linearly;
When S is OFF and the output diode is conducting, the energy stored in the transformer’s iron core is
transferred to the load.
The converter topology and typical current waveforms are illustrated in Figure 3.1:
RoC
D
S
U
Vo
(a)
DTsw Tsw Tsw(1+D)
iS
iC
S ON S OFF
t
t
(b)
Figure 3.1: Single output flyback converter. a) Circuit topology; b) Output capacitor current and input current waveforms.
This converter is characterized as an indirect topology, because the energy transferred to the load has to be
stored intermediately in the transformer iron core. This requires the transformer to be over dimensioned in
order to avoid saturation. The following table summarizes the advantages and disadvantages of this topology:
Table 3.1: Flyback converter advantages and disadvantages.
Advantages Disadvantages
Simple transformer;
The transistor control circuit is referenced to the ground;
Low number of components.
Low efficiency in the transformer usage, since it has to store the energy, leading to a big transformer;
Transformer must have good magnetic coupling;
Control is complex since it is an indirect converter;
High ripple in input and output currents, causing high EMI.
3.1.2. Forward converter
This topology originates from the non-isolated buck converter by replacing the inductor with a transformer.
The controlled power switch is placed in series with the primary winding with its source connected to the
ground. In the secondary winding a half wave rectifier using diodes is connected to transform the intermediate
alternating voltage into DC, which is then filtered by a low pass passive filter.
In addition to the primary and secondary windings, the forward converter requires an additional winding to
reset the iron core. Without this coil, the magnetic core would most likely saturate, leading to its destruction.
In each switching cycle the DR diode is put on conduction, when the power switch is turned off, allowing the
20
excess current in the primary to flow off to the tertiary winding and recycle the magnetizing current back to the
input source.
The converter operates also in two stages as described below:
When S is conducting, the input current flows through the primary winding, putting D1 on ON state,
feeding the capacitor and the load directly. The inductor current ramps up in this state;
When S is in cutoff, D1 is reversely biased and the output inductor forces D2 to ON state. The energy
stored in the inductor and capacitor is transferred to the load, causing the inductor’s current to ramp
down. The transformer magnetizing current flows in DR, resetting the iron core.
The following figure presents the circuit topology and some typical waveforms:
RoC
S
U
Vo
LD1
D2
DR
(a)
DTsw TswTsw(1+D)
iCQ ON Q OFF
t
iDR
t
(b)
Figure 3.2: Single output forward converter. a) Circuit topology; b) Reset winding and output capacitor current waveforms.
Contrary to the flyback circuit, this converter is characterized as a direct topology, because during DT the
energy flows directly from the input source to the load passing through the transformer. The following table
summarizes the advantages and drawbacks of this architecture:
Table 3.2: Forward converter advantages and disadvantages.
Advantages Disadvantages
The transistor control circuit is referenced to the ground;
Low ripple in output current.
The need for an additional demagnetization circuit in order to protect the transformer;
High number of semiconductor devices in the output;
High ripple in input currents leading to high EMI.
3.1.3. Other topologies
Regarding power circuit topologies, in the past recent years, there were no significant developments for
space applications. Most of all new topologies eligible to operate in space that meet the considered
specifications are based on the benchmark topologies presented before. Innovation in this area, sparkling the
emergence of more complex topologies is often hard to achieve because the circuits must comply to tight
reliability specifications and have to be tested in harsh conditions, and such tests can be expensive to perform.
Other topologies such as the Ćuk and SEPIC converters could also be considered, but both of these
converters are difficult to implement and offer no practical advantage over the previously presented ones. [23]
A novel alternative of a DC/DC converters using switched capacitor technology was found. [24]
Solutions using multiple controlled power switches, instead of natural switching diodes were also found.
These approaches enable the control of multiple outputs independently of each other. However with the
21
penalty of greater control circuit complexity, efficiency degradation due to additional power switch driving and
more vulnerability to space radiation.
3.1.4. Comparison of benchmark topologies
In order to choose the appropriate topology for the application, a comparison is made between the previous
approaches. The comparison is summarized in the table below:
Table 3.3: Comparison between studied benchmark topologies.
Converter
Characteristic Flyback Forward
Input ripple - -
Output ripple - +
Control complexity - +
Losses + +
Component number + -
Transformer complexity + -
Transformer size - +
Legend: + Good; - Bad.
The table above covers a set of DC/DC converter properties that were put into comparison. Observing the
table the forward converter stands out, when taking into account the topology that has bigger number of
positive points. Even though this converter requires an additional transformer winding, the flyback converter
does not offer any special advantage, besides a simpler transformer and less number of components.
3.1.5. Chosen power stage topology
To implement the multiple output capability the chosen forward topology will have multiple secondary
windings connected to the same iron core of the transformer. The winding ratios are dimensioned having in
mind the voltage levels of the different outputs. The output inductors of each output will also share their iron
core, in order to ensure the cross-regulation feature. Here the winding relations must also be carefully
dimensioned, bearing in mind the output voltage levels.
The circuit topology schematic with the three output feature including the power stage parameter design is
presented in Appendix A.4.
3.2. Control circuit
In the last decade the integration of electronic circuits and controllers for power supplies has suffered major
developments, not only in miniaturization foreseen by Moore’s Law, but also with the emergence of new
control methods in order to significantly increase the performance of switched power supplies. Subsequently
various different approaches will be presented in regards to the recent developments in DC/DC converters
control architecture.
22
3.2.1. Pulse width modulation
Pulse width modulation (PWM) control techniques include a wide range of control schemes that generate
the duty cycle at a constant frequency by means of a control system in closed loop. Depending on how the duty
cycle is generated and what state variables are sensed and fed back to the control loop, there can be many
different methods in the PWM family. For instance if only the output voltage (vO) is sensed, there is Voltage-
mode. Otherwise if both the output voltage and the inductor current (iL) are fed back, Current-mode control
arise.
a) Voltage-mode control In this method the duty cycle is generated by comparing a control voltage (vc) with a sawtooth signal (vsaw)
which frequency is equal to the switching frequency (Fsw). The control voltage is generated by an error
amplifier that compensates and amplifies the error voltage (vε). This error voltage is obtained from the
difference between the sensed output voltage and a reference voltage. If the error amplifier is not saturated, it
generates the necessary control voltage, and therefore a duty cycle, to nullify the error voltage. This means
that the output voltage, assuming stability, will tend to equal the reference voltage. If the output voltage is
different from the reference, the error voltage increases, varying the control voltage and consequently the duty
cycle. This control scheme is presented in Figure 3.3.
Voltage-mode control (VM) is relatively easy to understand and implement but it suffers from some
limitations. Since there is no current information in the control loop, there is no intrinsic way to limit this
variable in case there is a short circuit. However some new systems have a current limitation circuit that resets
the power switch when a fault occurs, granting permanent short-circuit protection. [25]
+
-vref
Compensation
Error Amplifier
PWM Modulator
vsaw
vdrive
+
-vc vε
D
voPower Stage
(a) (b)
Figure 3.3: Voltage-mode control scheme. (a) Block diagram; (b) Example plot of control voltage (blue), sawtooth voltage (black) and power switch driving signal (red).
b) Current-mode control Current-mode control (CM) adds an internal current loop to the voltage-mode control scheme. The control
voltage is no longer compared to an artificial sawtooth, instead it is compared with the sensed current
waveform (vIsense). The resulting voltage drives the reset input of a SR Latch, in which Q output has the driving
signal that controls the power stage switch. A clock impulse sets the latch turning the power switch on, causing
the inductor current to rise. When the sensed current waveform equals the control voltage the comparator
23
output switches state, resetting the latch and turning the power switch off. The current-control scheme is
presented in Figure 3.4.
+
-
vref
Compensation
Error Amplifier
PWM Modulator
vIsensevdrive
+
-vc vε
D
R
S
Q
vpulse
voPower Stage
(a)
t
visense
vc
iL
vpulse vdrive
t
(b)
Figure 3.4: Current-mode control scheme. (a) Block diagram; (b) some characteristic waveforms (forward converter).
The most widely used and less complex way to implement the inductor current sensor is to place a small
value resistance in series with the inductor, and sample its voltage drop. However this sensing method can
degrade the converter efficiency and if the voltage drop is very low, background noise can interfere with the
current sensing. This gives the design a compromise between low losses and the risk of noise interference.
Depending on the power circuit topology, it is preferred to sample the power switch current instead of
directly sensing the inductor’s. For example in the flyback and forward topologies the sensing resistor is placed
in series with the MOS transistor, simplifying the current sampling to only one wire, since the resistor is
connected to the ground. As described before, the peak current value information is all that is needed to
operate in current-mode control and sensing the power switch current is essentially the same as sensing the
inductor current, as far as peak current value is concerned. Figure 3.4 (b) shows the waveform of the power
transistor sensed current.
Unlike the voltage-mode control, this method can include a current limit circuit. As Figure 3.4 (b) suggests
the control voltage limits the inductor current peak value. Introducing, for example, saturation in the error
amplifier can effectively establish a maximum current value, since the sensed current voltage can never go
above the control voltage.
3.2.2. Pulse frequency modulation
Pulse Width Modulation has become mostly widespread and dominating the DC/DC converter market.
However, it is proven that as the load power decreases the efficiency of PWM switched power converters is
also diminished. The switching losses become a significant portion of the load demand, due to the imposed
commutation of the power switch.
To solve the previous issue an alternative control method is introduced called Pulse Frequency Modulation
(PFM). This type of control method is based on hysteretic regulation of the output voltage, has exemplified in
Figure 3.5. The power switch is put into ON state only when the output voltage drops lower than a certain
value, and is turned OFF when this voltage is higher than a certain level. This effectively increases the efficiency
24
under low demand situations, since the power switch is turned ON only when needed, unlike the constant
frequency command in PWM control. The switching frequency becomes proportional to the load power,
reducing the contribution of switching losses compared to the total converter losses.
vo
vref
Hysteretic
Comparatorvdrive
+
-vε
D
Power Stage
Figure 3.5: Pulse Frequency Modulation control diagram block
3.2.3. Comparison between control techniques
Now that the three main control schemes were presented, a comparison between them is followed. Firstly a
comparison between PWM and PFM will be made, in order to decide which applications are designed for each
control method.
It seems that the presented control schemes do not add any
The main reason to choose PFM control over PWM is due to the increased efficiency under low load
conditions and to avoid controlling the converter under Discontinuous conduction mode (DCM). The additional
complexity imposed by this conduction mode can be completely eliminated by PFM control. However, PFM
control leads to higher voltage ripple (Figure 3.6) and the hysteric comparator has to be fast enough to ensure
that the power switch is commanded to change state with minimum delay possible. In addition, the
unpredictable frequency value of PFM can give birth to jittery behaviors. If the circuit is affected by a noise
source, the feedback voltage to be compared with the error voltage will inherit this noise, which can lead to an
incorrect output voltage sampling, leading to output voltage oscillations. [26]
PWM PFM
t
Less
ripple
More switches
Tsw 2Tsw 3Tsw 4Tsw
t
More
ripple
Less switches
Figure 3.6: Sketch of output voltage waveforms for PWM and PFM.
These design constrains suggest that utilizing both control methods depending on the load condition, might
be preferred, instead of using one of them individually.
Reference [27] comprises a study in which the efficiency in a buck converter was measured when the
converter was solely operating in PWM mode or toggling between PWM and PFM modes. This study suggests
that the toggling point depends on the load current value, but it also depends on the input voltage. A lesser
input voltage value will cause more switches in PFM mode, therefore having a bigger duty cycle in PWM
25
instead of higher switching frequency is preferred. Figure 3.7 shows the graphical plot of the efficiency curves
and the optimum mode toggle point.
Figure 3.7: The optimum transition point between PWM and PFM modes in a buck converter as a function of input voltage and load current. [27]
Reference [2] also includes a study of a buck converter with PWM/PFM mode and showed that the optimal
transition point between both modes was at 30% of maximum output current. However the converter suffered
from stability issues when alternating from PWM to PFM. The load step voltage overshoot could not be
avoided when the converter was in PFM, because the hysteretic controller is blind to quick load variations.
Both of the previous references studied only the buck converter in alternating modes between PFM and
PWM. The need and feasibility of this control scheme in a multi output converter is not yet known and will be
studied further on this dissertation.
(a)
(b)
Figure 3.8: Comparison between VM and CM dynamic responses. (a) Step load transient; (b) Input voltage transient. [25]
The two PWM control techniques presented before have meaningful use in specific applications. When it
comes to space applications, safety and reliability is the first characteristic to be considered in electronic
design, since there is no margin for failure. This means that the power supply to be design has to include many
fault detection and prevention circuits, including a short-circuit arrester. The need for this protection puts aside
the voltage-mode control, because it has only a voltage loop. Nowadays VM control include an external current
limiting circuit, but current-mode control technique offer this feature intrinsically and provides other
advantages, such as transient stability and less noise sensitivity. VM control is the slowest method when
26
analyzing load step response, because it only has one feedback loop that introduces lag, due to the
compensation block in the error amplifier. A comparison between dynamic responses of the two different
control techniques is presented in Figure 3.8.
Based on the previous descriptions, a table including several aspects of all analyzed control techniques was compiled, emphasizing the advantages and drawbacks of each control method.
Table 3.4: Comparison between studied DC/DC converter control techniques.
Control Technique
PWM PFM
Characteristic VM CM
Output voltage ripple - ~ --
Closed loop stability - + ~
Low load losses - - +
Load step voltage overshoot and undershoot - ~ ?
Load step settling time - ~ ?
Intrinsic current limitation and regulation - + -
Noise sensitivity ~ + -
Number of sensors + - +
Component design constrains and sensitivity ~ + -
DCM control complexity - - +
Legend: ++ very good; + good; ~ intermediate; - bad; -- very bad; ? not yet studied.
Current-mode control has been subject of many studies since the end of the 80’s and it is a well-known
control scheme. This leaves current-mode control to be the control technique chosen for this dissertation.
3.3. Feedback isolation
The DC / DC converter in this project has a topology with galvanic insulation, between the input and outputs.
This requires ensuring that there is no metallic connection between the primary and secondary sides of the
transformer. This includes not only the power circuit, but also the control circuit, since the output voltage in
the secondary needs to be sampled and fed back to the control circuit.
For regulation benefits, most of the today applications place the control circuit in the primary side of the
transformer since the controlled power switch is also in this side. If the current circulating in this switch needs
to be quickly sampled, as it is in most of the control techniques adopted nowadays such as current-mode
control, it is preferred that the sensing mechanic undergoes the least delays and signal degradation possible.
On the other hand the output voltage signal has to be sent from the secondary side of the transformer to the
primary side via a nonmetallic connection.
In chapter 2.5.2 of this dissertation, it was mentioned that radiation exposure highly degrades the
optocoupler transfer ratio, making these solutions unviable and unreliable for space usage. Temperature also
has a preponderant effect on these devices, although it is easily compensated with additional circuitry.
Knowing this, a research on galvanic isolation schemes was done in order to choose the right technique to be
used for space applications. In this investigation three design techniques were found which are: magnetic
isolation, acoustic isolation and capacitive isolation.
27
3.3.1. Magnetic isolation
Magnetic galvanic isolation comprises, as the name suggests, the isolation technique that exploits the usage
of the magnetic field, in practice by using transformers. This type of feedback has been the technique mainly
used for space applications, because magnetic components such as inductors and transforms are inherently
immune to radiation exposure.
This isolation technique can be implemented in two different methods: direct or indirect sampling.
Power Stage vo
+
-
vref
Compensation
-v
Sample Switch
Control
Control Circuit
vdrive
Power Stage
Compensation
Control Circuit
vdrive
Sample Switch
Control
vbias
vo
+
-
vref
(a) (b)
Figure 3.9: Indirect sampling magnetic feedback. (a) Flyback magnetic feedback topology; (b) Forward magnetic feedback topology.
The indirect sampling technique (Figure 3.9) requires using an amplifier on the secondary side of the power
stage circuit. This would require either implementing it with discrete components, or designing an additional
integrated circuit, needing a housekeeping power supply. There are two different studied indirect sample
techniques which originate from adaptations of power circuit topologies. This means that the output voltage is
fed back to the control circuit by a low power flyback or forward converter, using an amplitude modulation and
a sample and hold scheme.
The direct sampling magnetic feedback takes advantage of the voltage that the output filtering inductor
produces when the power MOSFET is off. The current circulating in this inductor generates a voltage value that
can be related to the output voltage by the relation in equation (3.1), which can be obtained by analyzing the
secondary circuit when the power MOS if off.
RoC
S
U
Vo
L
D1
D2
Sample & Hold
Switch
Vo+VD2
Control
Circuit
RoC
vo
LD1
D2
iL
vL
vD2
vD1
nU
a) b) Figure 3.10: a) Direct sampling magnetic feedback in a forward converter; b) Secondary circuit schematic.
(3.1)
28
According to equation (3.1), it is possible to obtain the output voltage during the OFF period, by connecting
a winding that samples the negative inductor voltage. The sample and hold circuit must do this as soon as the
power switch is turned off and the switching ringing is damped. If the sample is done too late, it can
erroneously sample the zero voltage during the D’Tsw period that occurs in DCM (Figure 3.11). Unfortunately
the diode forward conduction voltage is also sampled this way, therefore the sampling winding relation has to
be dimensioned taking this into consideration. [28]
a) b)
Figure 3.11: Inductor voltage waveforms in CCM and DCM. The sample time interval is highlighted in order to avoid ringing.
3.3.2. Acoustic isolation
In the last recent years, acoustic isolation has become one of the most promising alternatives to replace
magnetic transformer in many applications. This type of galvanic isolation utilizes the piezoelectric effect,
which is observed in some materials due to their crystalline structure. When subjected to a mechanical strain,
these materials generate an electric field caused by the reorganization of dipole moments composing its
crystalline structure. This effect is reversible, meaning that an applied voltage will cause an induced mechanical
stress to be exerted in the material.
This technology is recently widely used in many applications, such as pressure, audio and frequency sensors;
accelerometers; high voltage applications; novel energy harvesting techniques; actuators and oscillators.
One of the greatest uses of acoustic isolation is the piezoelectric transformers (PT). Like a magnetic
transformer, it is possible to implement this feature by using an interface between two piezoelectric
generators. The input piezo receives a voltage signal and generates a mechanical stresses. The output uses
these stresses and generates an identical voltage signal to the input side.
Since the 50’s piezoelectric transformers have been researched, but only since the 90’s they have found
commercial usage. Piezoelectric materials behave much like crystals used in oscillators, but with a much lower
quality factor. This resonant behavior is explained by the sound waves that are reflected and bounced back to
the source. If the frequency is the resonant frequency, the reflected wave adds to the source wave, amplifying
the signal. The simplest equivalent electric circuit model is represented by a resonant LC circuit which
translates the piezo’s frequency response (Figure 3.12).
29
voutvin
Cin
Lp Cp Rp
1 : n
Cout
(a)
vout
PT
vin
(b) Figure 3.12: Piezoelectric equivalent electric circuit. (a) Schematic; (b) symbol.
The usage of piezoelectric transformers to isolate feedback circuits has been subject of many works in the
80’s and recently this has been subject of investigation for use in innovative applications. This system is based
on passing a voltage signal digitally modulated by the acoustic isolation. The frequency of the digital
modulation has to be close to the resonant frequency, in order to maximize the transfer ratio. In the output
side a digital demodulator followed by a low pass filter, is all that is needed to reconstruct the original signal. If
the signal to be transmitted is already digital only the modulation and demodulation is needed, avoiding the
delay imposed by the filter.
Piezoelectric Transformer
PWM
Modulator
signal
clock
PWM
Demodulator
Low Pass
Filter
Figure 3.13: Piezoelectric feedback isolation block diagram.
Piezoelectric materials have been studied by NASA regarding several applications for future spacecraft,
including their usage in the power distribution system of small satellites. Due to the reduced sized and higher
power density when compared to magnetic transformers, PTs are preferable to be used in space. [29]
Acoustic technology behavior in high radiation environments is yet not well studied but since there are
already some applications in aerospace and military applications, such as sensors (accelerometers [30]) and
aircraft noise dumping device measurements [31], one can argue that this technology is radiation resistant. Yet
additional testing and investigation is needed to guarantee the reliability of these devices over long term
radiation exposure and also against transient effects.
3.3.3. Capacitive isolation
Unlike the previously presented isolation techniques, the capacitor isolation uses the electric field to
transfer data from one circuit part to another without the need of a metallic connection.
Input OutputPWM
Oscilator
R
S
Q
Low Pass
Filter
Figure 3.14: Capacitive isolation block diagram as described in reference [32].
Reference [32] presents a digital isolation system using two capacitors to isolate two parts of a digital circuit.
Data is transferred, but the DC current flow is eliminated. If the input is an analog signal instead, a PWM
modulator is used to temporarily converter the signal to digital, so it can be bypassed through the capacitors.
30
The output side includes two hysteretic comparators and a SR Latch to detect the rising and falling edges of the
digital signal passed. A low pass filter might be required to reconstruct the original analog signal, with the
drawback of introducing a group delay, having to be taken in to account in the overall stability study. This
implementation diagram block is presented in Figure 3.14.
Reference [33] presents an alternative way to reconstruct the digital signal using a differential transmission
scheme with a static logic block (denominated C-element by the author) which output switches only when it
detects a valid differential transition. This logic block is robust enough to be immune to ground bounce mainly
caused by parasitic inductances in the coupling capacitor’s ground path.
(a)
(b)
Figure 3.15: Capacitive isolation block diagram as described in reference [33]. (a) Main block diagram; (b) C-element digital block in CMOS technology.
Figure 3.16: DC/DC step down isolated converter operated in voltage-mode control with digital capacitive isolation. [33]
This reference also illustrates how this coupling method can be used in an isolated DC/DC converter,
operating in VM control (Figure 3.16). In this approach the control circuit is placed on secondary side and the
digital signal passed through the coupling capacitors is directly the power switch driving signal. This requires an
additional housekeeping power supply, isolated from the primary, in order to feed the control circuit.
In a CM control scheme the previous block diagram is impossible to implement because the power switch
current is sampled in the primary side, and there is no way to quickly transfer this data to the secondary. The
alternative way is to pass the output voltage modulated in PWM from the secondary to the primary where the
control integrated circuit is placed.
31
Primary
Power Stage
Secondary
Power Stagevo
PWM
Oscillator
C-elementControl
Circuit
vIsense
vdrive
Isolation barrier
Figure 3.17: DC/DC step down isolated converter operated in current-mode control with capacitive isolation.
Both of the previous references state that capacitive coupling has many advantages over optocouplers and
magnetic isolation. Higher data transfer rate, lower propagation delay, higher life expectancy and good
immunity to radiated electromagnetic field are the main advantages of this type of isolation technique over the
others.
The behavior of capacitive isolation technique in radiation rich environments was already tested and its
immunity to TID was verified. Reference [34] reports that circuits using capacitive isolation techniques were
still operative after being subjected to a dose of 23,5 krad. The most sensitive parameters were found to be the
offset voltages, transmission gain and the typical output error. All of these issues origin from the integrated
oscillator and the comparator. If these blocks are designed for radiation, the problems are highly mitigated. On
the other hand, the accumulation of charges in the capacitor dielectric material has little to no effect on the
isolation function.
3.3.4. Comparison between isolation techniques
After presenting all the different considered isolation techniques, a comparison between them is
subsequently presented. For this purpose a table was compiled summarizing the three different techniques’
advantages and disadvantages concerning seven key characteristics (Table 3.5).
The circuit complexity was chosen to be worse in acoustic and capacitive mainly because the signal to be
transferred needs to be first pulse-width modulated and for that it is needed an oscillator and a comparator,
and consequently voltage and current reference circuits. The magnetic feedback technique offers a more
simple approach using only a sample & hold circuit and an extra secondary winding connected to the output
inductor.
Magnetic isolation can be the cheapest of the three techniques, because both acoustic and capacitive
require an extra chip located in the secondary side. With the magnetic isolation all the circuitry responsible for
the control is placed in the primary side, eliminating the need of housekeeping power supplies on the
secondary side.
32
Table 3.5: Comparison between studied galvanic isolation techniques.
Isolation technique
Characteristic Magnetic Acoustic Capacitive
Circuit complexity + - -
Cost + - ~
Power consumption + - ~
Data transfer rate ~ ~ +
Life expectancy ~ - +
Total Ionizing Dose immunity + ? +
Single event effects immunity + ? ~
Legend: + good; ~ intermediate; - bad; ? not yet studied.
The magnetic isolation only requires a sample and hold circuit, including a buffer, which depending on how
much load it will have to support, the power consumption can be lower or higher. In the capacitive isolation
scheme, if a pre-modulation is required, the oscillator and comparator need to be fast causing additional power
consumption, which can reduce the overall converter efficiency. The power consumption of piezoelectric
driving is not yet well studied and depends highly on the application and material used. A piezoelectric
transformer also needs a powerful driver to effectively create enough mechanical stress.
The comparison of behaviors in radiation rich environments is also a good decision point. Magnetic material
is immune to radiation effects. Acoustic material is used in spacecraft for other purposes which confers it some
reliability, although the reliable operation as an isolator is currently under studying. Capacitive isolation was
proven to sustain relatively high doses of radiation, even if the circuitry is not design to account for it.
With all the above considerations, the magnetic technique proves to be the most straightforward galvanic
isolation technique, being also the most cost-efficient method.
3.4. List of market converters
Now that the main different architectures and control techniques were presented, it is pertinent to
elaborate a list of solutions offered by the aerospace industry market. A research of both American and
European enterprises that sell the type of power supplies under study was made, in order to determine at what
state of the art they are working. This market investigation was done to analyze the products specifications and
functionalities, with special consideration to the control method used, how the feedback insulation is
implemented and how efficient these power supplies are.
In addition to the aerospace industry, solutions provided by conventional international electronic retailers
were also investigated. Although not radiation hardened, some interesting feedback isolation and control
techniques were found.
The list of market DC/DC converts found is presented in Appendix A.6. The table only contains the power
supplies that respect the design requisites presented in Appendix A.2, or that introduce novel innovative
features, such as multiple output regulation, radiation hardening solutions, control methods or feedback
isolation techniques. Among the investigated market solutions, PWM current-mode control was found to be
the most used control technique in aerospace converters, yet some retailers offered also voltage-mode with
current limitation. Outside of the aerospace industry all types of control schemes were found, including two
33
PFM and one hybrid PFM/PWM products presenting very high efficiency, but only for very low output power
levels and with relatively high output voltage ripples (2,5%).
Reported efficiencies can be as low as 60% to as high as 93%, with an average efficiency in the 80’s % level.
Some converters or regulators report a power down current consumption of less than 100 µA, but without
radiation hardening.
TID tolerance was measured between the 25 krad and 1 Mrad. Most of the radiation hardened solutions
respect the ESA compliance table, in respect to TID and LET tolerances.
The isolated topologies found were mostly forward converters, but also an appreciable number of flyback
converters. Curiously a Half-bridge converter was found to operate in space, which goes against some design
rules that were established before in this dissertation. Most of the multiple output converters found work in
parallel topologies or in dual voltage mode. No converter was found that can individually generate the output
voltages levels imposed by ESA specifications (see Appendix A.3).
In regards to the feedback isolation, only two different types of architectures were found. Some solutions
still use optocouplers, one of which using a temperature compensation circuit, but with no radiation TID
compensation. The other feedback isolation architecture found was magnetic feedback with an amplitude
modulation scheme. No converter was found to use both PFM mode and an isolated feedback.
34
4. Control and stability
The control circuit’s function is to elaborate the exact duty cycle that will generate an output voltage
proportional to a reference. This can only be achieved in a closed loop control system.
This chapter will introduce what PWM control technique was chosen for this dissertation and will present
one model that mathematically describes it. The objective of this chapter is to use the model to obtain the
correct compensation network that stabilizes the closed loop control system, and then test its veracity with
simulations such as step load and input source transients.
According to chapter 3.2.3, where all the State-of-the-Art PWM control techniques were presented, current-
mode control was pointed to be the best candidate due to its good closed loop stability, simplicity and
widespread usage in many nowadays applications. Most of the aerospace DC/DC converter retailers use this
control method since it gives extra protection to faults due to his intrinsic current limitation and good load and
line regulation responses.
Afterwards, the feasibility of the PFM control technique will be studied, considering the advantages it offers
in efficiency. For this purpose the PWM and PFM efficiencies will be measured and the optimal transition point
will be determined, if PFM offers a huge efficiency boost over PWM.
4.1. PWM control
All closed loop control linear systems, whether included in switch-mode power supply design or not, can be
schematized by their equivalent block diagram. Each block corresponds to a mathematical model of an actual
circuit, characterized by its transfer function in the Laplace frequency domain.
Regardless of the converter control technique, the controller objective is to maintain one or more state
variables close to a certain value called reference (vref). In current-mode case the state variables to be
controlled are the output voltage and the power switch peak current value. To determine if the output voltage
is diverging from its reference, an output voltage sensor must sample its value and compare it with the
reference, originating an error voltage (vε). According to this error signal, the power switch will actuate in the
circuit in order to approach the output voltage to its reference value. The previously explained control scheme
can be expressed by its block diagram in Figure 4.1(a), where P(s) is the Laplace domain transfer function of the
converter’s power stage in current mode control and σ the output voltage sensor gain given by Equation (4.1).
(4.1)
However, the previous control scheme will not effectively control the output voltage alone. First the closed
loop steady state gain, presented in Equation (4.2) is very dependent on the power stage static gain P(0). If it is
not big enough, the output voltage will exhibit an error when compared to the reference. Second, the dynamic
behavior will most likely display unstable characteristics.
|
(4.2)
35
To increase the static gain and improve the dynamic response, a compensation block is needed right after
the error voltage. This compensation block, represented by its transfer function C(s), is implemented with an
error amplifier and a compensation network, and its output is denominated control or command voltage (vc).
Figure 4.1b shows the closed loop block diagram with a compensator.
The sensor gain was removed from the feedback loop because its effect is only noticed in steady state. The
sensor gain is realized with a voltage divisor using two resistors. One of the resistors ensures only the DC
operating point and makes sure the output follows the reference. Its effect on small signal gain is not relevant.
P(s)vref
+
-
vε vo
σ
P(s)vref
+ vε vo
σ1
-C(s)
vc
(a) (b)
Figure 4.1: Generic block diagram of the output voltage control in closed loop with (b) and without (a) compensator.
Compensators normally come with an intrinsic integrator, to ensure a very high static gain, and at least
another pole and zero pair that guarantees stability, by increasing the phase and gain margins. The challenge
now is to obtain an accurate model that describes the power stage – the control (vc) to output transfer
function, in current-mode control, in order to design the appropriate compensator that stabilizes the closed
loop control system.
4.1.1. Current-mode control model
There are many different approaches to model a DC/DC converter’s power stage in current-mode control.
The previous work done in reference [3] used a model created by Dr. Riddley that essentially is a voltage-mode
model with an internal current loop. This loop takes into account the current sampling mechanic which is
described in the discrete z domain and approximated to the continuous s domain. While this method can
produce somewhat accurate results, the obtained transfer functions include high order polynomials making the
poles and zeros very difficult to extract from the expressions.
According to reference [25], Prof. Christophe Basso states that the key to stabilize a switch-mode power
supply is to understand the converter parameter variations and how they alter the poles and zeros positions,
and how they ultimately affect the gain and phase margins.
a) Subharmonic oscillations How the duty cycle is elaborated in the current-mode control was described in Chapter 3.2.1 and
schematized in Figure 3.4. However this explanation did not include a widely known stability issue that CM
control suffers from. When the duty cycle approaches 50%, the output voltage starts to gradually exhibit an
oscillatory behavior frequency equal to half of the switching frequency. If the duty cycle exceeds 50%, the
output voltage becomes actually unstable, with increasing amplitude oscillations.
This phenomenon is intrinsically caused because the time instant where the switch is opened is determined
by the control voltage alone. At duty cycles close to and above 50%, if there is a current perturbation (ΔIL) and
if the control voltage does not react to this perturbation right away, the instant of time which switch is turned
36
off can vary greatly. The perturbation is amplified on the following cycle, creating an unstable behavior. This
abnormal current waveform is illustrated in Figure 4.2.
(a)
(b)
Figure 4.2: Inductor current waveform for duty cycles less than 50% (a) and greater than 50% (b). [25]
i. Solution
The most used method to prevent subharmonic oscillations is adding some sort of perturbation to the peak
current value to compensate the actual inductor current perturbation, reducing its amplitude in the following
switching cycles. This can be done by injecting a ramp signal called ramp compensation that can be either
added to the sensed current waveform or subtracted from the peak current value – the control voltage. This
ramp will ensure that if the perturbation is high at the start of a given cycle, it will diminish on the next,
eliminating the instability. The effect of this ramp compensation on the current waveform is illustrated in
Figure 4.3.
The amount of slope compensation (Sc) that is needed to inject will determine whether the converter will
oscillate or not. According to reference [25], the perturbation at the end of the cycle ( ΔIL(Tsw) ) can be written
as a function of the perturbation in the beginning of the cycle (ΔIL(0)), the inductor current on and off slopes
(Son and Soff, respectively) and the compensation slope (Sc), as equation (4.3) demonstrates.
(
) (4.3)
Figure 4.3: Inductor current waveforms (blue) influenced by the ramp compensation.
37
Considering now the succession of n cycles after the initial perturbation, the nth cycle perturbation value
can be written as:
(
)
(4.4)
Knowing the relation between Son and Soff with the duty cycle, the above equation can be rewritten as a
function of the duty cycles (D) and the relation between the off slope and compensation slope (kS).
(4.5)
(
)
(
)
(4.6)
The succession of Equation (4.6) will converge to zero if the absolute value of the term elevated to n is less
than unity, | | . The coefficient α can plotted in respect to the duty cycle and for different values of kS,
obtaining the Figure 4.4:
Figure 4.4: Coefficient α as a function of the duty cycle and the quotient between the compensation and off slopes (kS).
Observing the plot above, it is easily noted that without slope compensation (kS=0), the converter is
marginally stable (α=1) for duty cycle of 50%, according to predicted. For the duty cycle of 100% the minimum
compensation slope needed to ensure marginal stability is 50% of the falling slope.
+
-
vref
Compensation
Error Amplifier
PWM Modulator
vIsense
vdrive
+
-vc vε
D
R
S
Q
vpulse
voPower Stage
++vramp
KI
Figure 4.5: Current-mode control block diagram with ramp compensation.
38
Using ramp compensation, the block diagram of current-mode control changes from the original presented
in Figure 3.4. A ramp signal, synchronized with the latch reset clock, must be added to the sensed current
signal, creating the block diagram presented in Figure 4.5. The KI constant corresponds to the internal current
loop gain used to improve the PWM comparator sensitivity, instead of feeding it with very low voltage levels
and to allow a smaller current sensing resistor, reducing power losses.
b) PWM Switch model
A DC/DC converter is a highly nonlinear electronic circuit, making its modeling quite difficult based on linear
transfer functions. One possible approach is to linearize the waveforms by calculating their average values over
a switching cycle. This method is called state-space averaging, and Prof. Basso in his book [25] indicates how
difficult is to obtain a good small signal transfer function using it.
In the late 80’s, attempting to deal with the chopper non-linearity, Dr. Vatché Vorpérian introduced the
concept of the PWM Switch model. This concept is similar to the method used to analyze nonlinear circuits
with bipolar transistors. It replaces the DC/DC converter nonlinear components, constituted by the power
transistor and the diode, by a linear circuit composed only by dependent sources and passive components.
With this method it is possible to obtain the converter small and large signal transfer functions, assuming
linearity around a certain steady state point.
The PWM Switch model is composed by three ports: the active, the switch terminal not connected to the
diode; the passive, the diode terminal not connected to the switch; and the common, where both devices are
connected.
a
p
c
vcpvap
ia ic
Ro
Cvo
L
a
p
c
U
nU
nia
PWM Switch modelDC Transformer
rC
(a) (b)
Figure 4.6: PWM Switch model concept. (a) Symbol; (b) Single output forward converter with the PWM Switch model and a DC transformer simulating the real transformer.
The PWM Switch structure, voltage and current waveforms are invariant from the converter topology. The
DC transformer was used to simulate the actual power transformer. This linear model must not be confused
with the DC Transformer used in the Space-State Averaging method, where the transformation ratio is the duty
cycle, it merely represents the presence of the power transformer in a forward converter, distinguishing it from
the buck converter.
i. Large signal model
Prof. Basso derived the large signal model state equations in his book [25], by considering the state variables
ia, ic, vcp , vap, vc and d and averaging them over a switching cycle, as presented below:
(4.7) (4.8)
(4.9)
39
The state equation regarding the ic current is obtained by observing the inductor current waveform (Figure
4.3) and average it over a switching cycle. The state variable d represents the instantaneous time value of the
duty cycle, Rsense represents the sensing resistor that samples the power switch current and vc corresponds to
the control voltage at the output of the error amplifier, and not the common port voltage of the PWM switch
model. This large signal model is non-linear model, therefore it is not possible to derive a transfer function out
of it.
ii. Small signal model
The small signal model is obtained by perturbing the large signal equations, (4.7) and (4.9), and neglecting
the cross alternating products, or simply put, linearizing the large signal model. The state variables ia, ic, vcp , vap,
vc and d are replaced by a sum of their continuous and alternating components:
, , , , (4.10)
The final small signal derived equations are the following:
(4.11)
(4.12)
(
)
(4.13)
( )
[( )
]
(4.14)
The derived small signal mode in Equations (4.11) and (4.12) do not predict the subharmonic oscillations in
any degree. Figure 4.3 suggests that current-mode instabilities are due to a memory effect concerning current
perturbations, so this has to be included in the small signal model as well. One good way to do it is adding a
capacitive effect between the c and p nodes of the PWM Switch model, creating the desired voltage memory
effect, as described in reference [25]. The subharmonic oscillations were previously described as having a
fundamental frequency equal to half the switching frequency, so the capacitor value (Cs) can be obtained by
knowing the resonating angular frequency along with the output inductor value:
√
√
(4.15)
With all the previous equations, the small signal model of the universal PWM Switch can be represented by
its linear incremental model, constituted by linear components, such as conductances, dependent current
sources and a capacitor:
Figure 4.7: PWM Switch model in current-mode control in continuous conduction mode.
40
This model can be used to simulate the small signal behavior of the power stage in LTspice and also to derive
the forward converter transfer function, incorporating it Figure 4.6 (b).
c) Forward single output Power stage transfer function The CCM power-stage small signal transfer functions in CM control can be obtained replacing the power
switch and diode network by the model derived in chapter b). The control to output transfer function is
approximately equal to:
(4.16)
(
)
(4.17)
(4.18)
From the equation (4.16) it is simple to extract the first order pole and zero – Equation (4.18). Analyzing
their position in the bode plot is critical to determine what parameters can compromise the converter’s
stability.
d) Forward multiple output Power stage transfer function To derive the forward converter transfer function including the three output feature, it is necessary to find
the one output equivalent so that Equation (4.16) still holds. This exercise is done using impedance reflection
theory to transform the passive components in the cross-regulated outputs into the main output, using the
respective winding ratios (Figure 4.8).
C1vo1
L1
Ro1
a
p
c
U
PWM Switch model
rC1
n1
C2
vo2
Ro2
rC2
n2
n2 /n
1
ls1
ls2
Figure 4.8: Two output forward converter schematic using the PWM-switch model and cross regulation.
41
For the multiple output linear model, the PWM Switch is placed on the primary side of the DC Transformer,
to simplify the impedance reflection process. The PWM switch will now see a different value of inductance
because the real inductor is reflected by the power transformer, by the n12 factor. This has to be taken into
account when simulating this circuit because inductance parameter will determine the frequency of the
subharmonic oscillations, therefore the right value must be fed into the model.
Prof. Basso in this book [25] calculated the equivalent inductance, but unfortunately his calculations did not
account for the coupled output inductors. The model he used is presented in Figure 4.9 and the obtained
equivalent inductor equal to equation (4.19).
Figure 4.9: Multiple output forward converter model used by Prof. Basso to calculate the equivalent inductance.
∑
(4.19)
With coupled inductors the calculation is somewhat different. In fact all the output inductors sharing the
same iron core can be viewed as a transformer. With this approach only the primary inductance (L1), which acts
as the magnetization inductance of this transformer, is reflected back to the primary side of the power
transformer. The N factor, which in Prof. Basso’s calculations accounts for the existence of N outputs,
disappears because only one inductor (L1) is reflected back.
The resistances are divided by the square of the winding relation, while the capacitors are multiplied by the
same factor, as equation (4.20) shows.
(
)
(
)
(
)
(4.20)
The inductor in the regulated output does not suffer any transformation because it is already at the primary
of the transformer composed by the coupled inductors.
42
C1
Ro1
L1
rC1rC2
C2(n2/n1)2
(n2/n1)2
Ro2
(n2/n1)2
rCN
CN(nN/n1)2
(nN/n1)2
RoN
(nN/n1)2
. . .
Figure 4.10: Secondary portion of the single output equivalent circuit to the N output forward converter power stage.
The next step is to convert all the multiple equivalent passive components into individual ones. The output
load resistors are all in parallel therefore the final equivalent is given by equation (4.21)2.
(
)
(
)
II
(
) (4.21)
The capacitors and their ESR cannot be converted directly into one equivalent capacitor and resistor in
series, because each branch has its own time constant and an equivalent time constant cannot be defined. If
the ESR value is negligible, the capacitors appear in parallel so the equivalent capacitor is the sum of all
capacitors shown in Figure 4.10.
(
)
(
)
∑ (
)
(4.22)
Like it was done with the capacitor, the ESR can be assumed to be in parallel. This approach is valid if the ESR
and capacitors values are not significantly different from each other.
(
)
(
)
II
(
) (4.23)
The multiple output transfer functions can now derived by using the single output expressions presented in
equation (4.16), but replacing the C, L, Ro and rC parameters with their equivalents.
e) Transfer function parameters Now that the multiple output transfer functions were derived, their parameters have to be calculated and
sized. In the original PWM Switch model, the inner current loop gain is only characterized by the sensing
resistor. However, in order to improve the PWM comparator sensibility the sensed current signal can be
afterwards amplified. The KI parameter translates this amplification gain. The injected compensation slope (Sc)
value to improve the stability must also be calculated and along with it the sensing resistor value (Rsense).
2 The parallel operator used in this equation must not be confused with the product operator. See chapter 1.4 for its
definition.
43
i. Inner current loop gain
High current sense resistor values may degrade the efficiency, so it is preferable to later amplify vIsense inside
the controller using an amplifier. The KI parameter translates this voltage gain. In addition to this gain, an offset
voltage (VIos) can be added to the compensated current information, in order to ensure that the PWM
comparator works at its linear region. This does not affect stability because the control voltage will
automatically adjust itself to ensure the output voltage follows the reference.
The voltage feeding the PWM comparator’s positive input is then given by:
(4.24)
ii. Transformer primary inductance current slope
Unlike the buck converter, the slope parameter does not correspond to the output inductor current
slope during the ON interval. In the forward converter the current is sampled in the primary side, at the power
switch, making the parameter corresponding to the primary inductance current slope. The
parameter
is the amplified voltage slope generated by the sensing resistor.
(4.25)
The primary inductance current slope can be calculated using the equivalent single output model derived in
chapter d). The primary inductance is determined by the output inductor current slope and then has to be
reflected back to the primary side, meaning it has to be multiplied by the winding ratio. This is true if the
transformer’s primary inductance is much greater than the output inductance, making the magnetizing
negligible. When the magnetizing current is not negligible, its slope has also to be accounted for. Figure 4.11
illustrates how the primary current slope is obtained from the equivalent inductor slope.
RoeqCeq
S
vo
L1D11
D12
DR
U
iDr
iL1
iS
(a)
t
iS
DTsw Tsw
n1xiL1
iDr
iL1Son Soff
Sonp
Smag
(b) Figure 4.11: Forward converter single output equivalent circuit (a) and some waveforms used in the slope calculation.
(
)
(4.26)
Equation (4.26) depends on the input source value, which is not fixed. In order to understand how the duty
cycle affects the slope, it is rather preferable rewriting the equation as a function of it, knowing the definition
from equation (A.2):
(
)
[
]
(4.27)
44
The above equation dependence on the duty cycle reveals that the higher its value, the less steep the slope
becomes. When stability issues can be observed, for a duty cycle of 50%, the slope has its minimum value. For
simplicity purposes equation (4.27) was approximated into the next equation, considering a duty cycle of 50%.
(
)
(4.28)
iii. Compensation slope
Since the forward converter will never exceed duty cycles of more than 50%, the slope compensation must
be chosen in order to guarantee that the perturbations are attenuated in the least switching periods possible,
by forcing a small α coefficient. However, over compensating the converter will degrade his dynamic response,
because it will lose its CM characteristics and behave more like a VM controlled converter.
The compensation slope value that guarantees a perturbation is damped to a certain percentage (ξΔIL) can be
calculated as a function of the number of switching cycles needed. Picking (4.6) and solving for kS yields:
(
)
√
(
)
√
(4.29)
Plotting now kS as function of the number of cycles needed to attenuate the initial perturbation by 95%,
meaning that ξΔIL is equal to 5%, gives the following graph:
Figure 4.12: kS as a function of the number of cycles needed to dump the inductor current perturbation to 5% of the initial
value and for different duty cycles.
Figure 4.12 shows that for the compensation slope corresponding to 25% of the off slope, the maximum
number of cycles needed to dump the perturbation is 6, for the maximum duty cycle of 50%. This value can
then be defined as the maximum ratio between Soff and Sc ( ), that does not compromise CM control
dynamic behavior but also dumps the oscillations relatively fast.
The compensation slope can be written as a function of the on slope derived in (4.27) and knowing that the
relation between the on and off slopes given by (4.5) is equal to 1 for duty cycle of 50%:
(4.30)
iv. Sensing resistor value
The error amplifier saturation can be exploited to introduce primary winding current value limitation. This is
done ensuring that for the maximum current in the power MOS (
), the amplified sensed voltage of equation
(4.31) is close to the amplifier maximum voltage level VDD.
45
(4.31)
This is done ensuring that the Rsense value is such that for the maximum tolerable current, the sensed voltage
(vIsense) is close to the minimum supply voltage (VDDmin). To derive the equation for the sensing resistor value, it
is pertinent to analyze the sensed signal waveform after passing through the amplifier:
t
VDDmin
VIos
DTsw
KSM (safety margin)KIvIsense
peak
Ispeak
KIRsense
vIsenseKI
Figure 4.13: Voltage waveform at the output of the current sensed signal amplifier.
From the above figure the maximum value can be computed as followed:
(4.32)
A safety margin between the maximum value previously calculated and VDDmin must exist to avoid saturation
during transient load steps, therefore the following equality can be written and the resistor value can be
derived:
(4.33)
f) Validating the multiple output model In order to proceed with the DC/DC converter compensation, the derived single output equivalent model
has to be simulated and validated. Both the multiple output and the equivalent single output models will
undergo an AC simulation and will be compared with the analytical results from equation (4.16). The LTSpice
model schematics are shown in Appendix A.8.1 and A.8.2 (multiple output and equivalent single output
models, respectively) and the simulation results in Figure 4.14.
(a) (b)
Figure 4.14: Comparison between bode plots of the simulated models and the theoretical analytical model.
46
The results obtained confirm the validity of the derived model, since the plots are superimposed. There is a
slight difference between plots in high frequency, which is due to the ESR approximation already explained.
4.1.2. Compensating the forward converter
Now that the parameter variations effects on the open loop bode plot were studied, the actual multiple
output forward converter compensation can be carried on. In this section the adequate compensator topology
and respective parameters will be sized in order to guarantee certain stability criterions, in particular the gain
and phase margins.
The following analysis will be done assuming CCM. To validate the stability in DCM, the converter will be
tested in a transient simulation including the DCM operation. If the converter suffers from instabilities in DCM
then the compensator will have to be retuned, taking into account the DCM PWM Switch model.
a) Crossover frequency The crossover frequency is the frequency value at which the open loop gain is 0 dB. This is the frequency
value where the phase margin is measured and depending on its value, the converter will have a faster or
slower response time when subjected to a transient.
The chosen crossover frequencies for SMPS typically range from 10% to 20% of the switching frequency. In
CM control the crossover frequency must not be as high as the sub harmonic oscillations frequency, because
the converter would not guarantee that oscillations are sufficiently damped. This yields the following equation
for the crossover frequency:
(4.34)
b) Phase margin The minimum phase margin specified by ESA is 50o. Knowing that for phase margins bellow 45o the
converter exhibits an oscillatory behavior, designing the converter to have the minimum required phase margin
for nominal conditions can be dangerous, because any parameter drift can cause the phase margin to decrease,
eventually making the converter unstable. Higher phase margins reduce the overshoot but can slow down the
speed at which the converter recovers from a transient.
Figure 4.15: Transient response for different [25]
47
As the figure above illustrates, a good compromise between speed, low overshot and stability would be
choosing phase margins for nominal conditions in between 70o and 80o.
c) Compensator type CM control converters that do not include a right half plane zero only require a type 2 amplifier, according to
reference [25]. A type 2 amplifier includes an integrator, to ensure a high steady state gain minimizing the
output voltage static error, and a zero pole pair to adjust the phase and gain margins at the desired crossover
frequency. The compensator is implemented with an error amplifier with a compensation feedback network, as
presented in Figure 4.16.
+
-
vref
vc
voRf
Rbias
Cp
RzCz
Figure 4.16: Type 2 amplifier circuit schematic – integrator and zero-pole pair.
In the above schematic, Rbias only serves to establish the DC operating point, because it does not enter the
error amplifier transfer function. Considering an ideal operational amplifier the transfer function is given by:
( )(
)
(4.35)
d) Compensator parameters The compensator passive components are computed taking into consideration the gain and phase boost
required to satisfy the phase margin at the crossover frequency. Computing the passive component values is
basically determining the pole and zero position in the complex plane. The pole and zero can be either placed
manually, as long as the specifications are met, or automatically placed using the k-factor compensation
method.
The k-factor compensation method (described in reference [25]) adjusts the distances between the pole and
zero to achieve the desired phase boost at the crossover frequency. The bigger the k-factor, the more phase
boost is given and the more the pole and zero are further away from each other (Figure 4.17a).
The phase boost can be computed knowing the phase contributions of both the zero and pole at the
crossover frequency:
(
) (4.36)
(
) (4.37)
The phase boost required to achieve the desired phase margin takes into account the 90o phase shift
introduced by the integrator and the open loop phase value at the crossover frequency (Φopenloop). The sum of
these three contributions have to equal the phase needed at the crossover frequency to reach the desired
48
phase margin (Φmargin). The phase boost calculation is illustrated in Figure 4.17b and on the corresponding
equation:
(4.38)
Knowing now the static gain that the error amplifier must introduce, in order to force 0 dB at the crossover
frequency (Gc), the component values that compose the compensation feedback loop can be computed with
the following equations [25]:
(4.39)
(a)
Φboost
Φmargin
ΦopenloopCompensator
arg[C(s)]
Open loop
Power Stage
arg[P(s)]
-100
Open loop Power
Stage-90º
arg[P(s)]-90º
Φboost
(b)
Figure 4.17: (a) Type 2 k-factor compensation; (b) Phase boost calculation.
e) Compensated Power Stage transfer function Having calculated the compensator parameters the open loop compensated transfer function can be
obtained by combining both the compensator and power stage transfer functions, respectively equations (4.35)
and (4.16). Figure 4.18 shows the bode diagram of the compensated power stage transfer function and how
the k-factor compensation achieved the desired 80o phase margin at the crossover frequency.
(a)
(b)
Figure 4.18: Compensated power stage bode plot. (a) Magnitude [dB]; (b) argument [o].
f) Parameter shifts effects on stability The key to stabilize a switch-mode power supply is to understand the parameter drift and how they affect
the gain and phase margins. The parameters that are going to be swept will be the following: the duty cycle,
with and without the ramp compensation; equivalent output capacitance and its ESR; error amplifier gain-
bandwidth product; and the compensator discrete components.
Phase margin 80o
Crossover Frequency
49
The following presented bode plots correspond to the compensated transfer function P(s)×C(s). The
compensation parameters were computed assuming a duty cycle equal to 0.45 and with the sufficient slope
compensation calculated previously.
i. Duty-cycle
Plotting the bode diagram with duty cycles ranging from 0.15 to 0.5 yields the following results:
(a) (b)
Figure 4.19: Bode plot of the open loop transfer function for different values of duty cycle, without (a) and with (b) ramp compensation (Equation (4.30)).
Like it was predicted the subharmonic oscillation resonance peak occurs only for duty cycles close to 0.5 and
their fundamental frequency is 500 kHz, or half the switching frequency. The effect of ramp compensation is
clearly noticeable, dumping greatly the subharmonic oscillations for duty cycles close to 0.5.
According to what was intended for the duty cycle of 0.45 and with ramp compensation, a phase margin of
80o was achieved. Removing ramp compensation the phase margin suffers a decrease of 4.14 degrees.
Decreasing the duty cycle proves to decrease the phase margin, therefore having an important effect on
stability. However, for the minimum duty cycle plotted, the phase margin is only decreased by a little more
than 8o, preserving the intended non-oscillatory behavior (phase margin greater than 45o).
ii. Output capacitor and its parasitic resistance
The next two parameters that will be analyzed are the output capacitance and its ESR. These parameters
affect both poles and zeros of the transfer function, so their effect on the bode plot has to be quantified. The
capacitor’s ESR is described by prof. Basso in his book [25] as the most critical parasitic parameter that affects
the stability. To find out why, the transfer function will be plotted for different values of this ESR.
50
(a) (b)
Figure 4.20: Bode plot of the open loop transfer function for different values of output capacitance (a) and inductance (b). The colored dots and crosses represent the frequency values of the zero and pole, respectively, which the inductor and
capacitor influence.
Figure 4.20 (a) shows that bigger capacitance values will produce higher phase margins and also reduce the
crossover frequency value, creating a slowing down effect. If the capacitance is actually smaller than the
nominal value, phase margin appeared to decrease severely by more than 15 degrees. In Figure 4.20 (b) it is
clearly noticeable that both the magnitude and phase undergo severe changes and the higher the ESR the
lower the frequency the zero appears, according to equation (4.18). Higher values of ESR greatly increase in the
phase margin, which can deteriorate the speed of response of the closed loop system.
iii. Operation amplifier GBW and low frequency gain
To predict whether the non-idealities of the operation amplifier will influence stability, the error amplifier
transfer function has to include the limitations of gain-bandwidth product and the low frequency gain. This is
done assuming that the operation amplifier is modeled as single pole low pass filter with open loop gain of A0
and gain-bandwidth product of GBW. The transfer function of this type of amplifier is given by the following
equation:
(4.40)
Now combining the above equation with the compensator transfer function of equation (4.35) and using the
negative feedback formula (4.41), yields the following transfer function of the non-ideal error amplifier:
(4.41)
51
A(s)vref
+
-
vε vc
C(s)
1
Figure 4.21: Feedback scheme of the error amplifier with the operational amplifier single pole model.
C’(s) is the transfer function of the non-ideal error amplifier, which can be put to test by making A0 and GBW
grow close to infinity, resulting in C’(s) equal to C(s). To determine the effects of these two parameters being
finite, the compensated open loop power stage transfer function will be plotted with C’(s) instead of C(s):
(a) (b)
Figure 4.22: Open loop compensated transfer function for finite values of: (a) error amplifier GBW; (b) low-frequency gain.
It is clearly visible in Figure 4.22 that a GBW lower than 1 MHz will give rise to stability problems. This figure
suggests that the amplifier must be dimensioned to have at least 3 MHz of GBW in all operational
circumstances, in order to preserve a phase margin shift under acceptable values. The open loop gain does not
impact stability and phase margin, although it may increase the static error of the output voltage if a
sufficiently high gain is not attained (lesser than 60 dB).
iv. Compensator passive components
To understand the effect of shifts in the compensator passive components (Rz, Cz and Cp) on phase margin it
is important to notice their influence in the position of the pole and zero pair introduced by the compensation.
For this purpose a sensitivity analysis will be done in order to quantify the bode plot results.
The frequency of the pole and zero of the type-2 amplifier are given by equations (4.42), which yields the
sensitivity results of Appendix A.7.
(4.42)
Figure 4.23 shows how the bode plot and phase margin is transformed by shifting the above passive
component values. Varying Cp value has an inverse relation on phase margin, meaning that increasing it,
52
decreases the phase margin and vice-versa. Cz on the other hand has the exact opposite behavior when shifted
from his nominal value. This symmetric shift effect can work in favor of preserving the intended phase margin,
if both capacitors are made integrated. Generally when a parameter drift occurs in integrated circuits, all
similar passive components are affected the same way. The Rz resistor however behaves differently because
both the pole and zero gets shifted in the same direction. This causes that either a rise or decrease in
resistance, reduces the phase margin.
(a)
(b) (c)
Figure 4.23: Open loop compensated transfer function after shifting error amplifier passive component values: a) Cp; b) Cz; c) Rz. The colored dots and crosses represent the fp and fz values of equations (4.42), for the different passive component
values.
4.1.3. System simulations
Now with means to stabilize a multi output forward converter with cross regulation, using the model derived
and validated before, the next and final step is to simulate it in LTSpice environment. The compensator used in
the following simulations was dimensioned to have phase margin of 80 degrees and was implemented using
the single pole operational amplifier model with a GBW of 5 MHz and an open loop gain of 70 dB.
The power stage passive components were sized using the procedure presented in Appendix A.4.
a) PWM-switch averaged model vs. switched model The first simulation results that will be presented will prove that the switched model used is appropriate, by
comparing the step response with the averaged PWM-switch model. The simulated circuit schematics can be
53
found in Appendixes A.8.3, A.8.4 and A.8.5, respectively the PWM switch model top circuit, the switched model
top circuit and the controller circuit.
From Figure 4.24 it is visible that the two models produce similar responses when subjected to the same
step load equal to 40% of maximum main output current. With the switched model it is possible to observe the
ripple, but the simulation takes more time to generate the results. The switching loses cannot be estimated
with the PWM-switch model directly.
Figure 4.24: Output voltage during a step load transient using the PWM-switch average model (blue) and the switched model (superimposed in green).
b) Switched model simulations
i. Steady-state operation
The steady state operation was observed in order to validate whether or not the output voltages are stable,
exhibit low static errors and to determine their voltages ripples. The inductor currents were also scoped to
measure their ripples. This simulation was done the converter operating at 9 W (3 W per output) and with the
input voltage equal to 28 V. The soft start was implemented by adding a time constant to the reference voltage
of approximately 80 µs.
(a) (b)
Figure 4.25: Startup and steady state operation of a three output forward converter. (a) Output voltages and inductor currents; (b) Output voltages and inductor current zoomed in 20 switching cycles.
The simulation results presented in Figure 4.25 show that both voltages and current ripples are under the
intended specification values and that the steady state values of the output voltages are also very close to what
54
was intended. The main regulated output of 5 V shows little deviation from its nominal value (only 3 mV);
however, the two cross-regulated outputs error can be measured in the dozens of mV (due to cross-
regulation). No subharmonic oscillations were found even for the lower input voltage.
ii. Main output step load (CCM)
The next simulation will include a main voltage step load transient and the effects on the cross regulated
outputs will be observed. Figure 4.26 shows the results obtained.
Figure 4.26: Step load transient of 40% of maximum output current and respective output voltage response. Above: the output current plot; below: the output voltage plot.
From the figure above it can be observed that the response time is very close to what was predicted with
equation (A.19) and that the overvoltage specification is met for all input voltage levels, but the undervoltage
for the minimum input voltage undergoes a strange behavior. This excessive undervoltage is due to the duty
cycle limitation of 50%, built in the controller circuit model used in this simulation. To eliminate the
perturbation, the converter needs to increase the duty cycle above 50% to maintain the response characteristic
of a 80 degree phase margin system. Because the duty cycle is limited, the output voltage falls below expected
and by the time the inductor current reaches its steady state value, the converter needs to correct the bigger
than expected undervoltage, creating a temporary overvoltage as a result. This duty cycle limitation is used to
avoid the saturation of the transformer, guaranteeing that in the startup the duty cycle is maintained below
50%, as well during transients.
There are ways to avoid this behavior: for example the duty cycle limitation could be raised to 60% or even
70%, by increasing the reset winding ratio; however, at the cost of also increasing by the same proportion the
reverse voltage on the power transistor. Other way around the issue could dimensioning the transformer
secondary winding ratios to prevent the converter form operating at duty cycles very close to 50%. By
dimensioning the converter to operate at minimum input voltages, at duty cycles of 40% or even 30%, can
avoid this issue. Even though this undervoltage is bigger than normally expected, its amplitude is still under the
specification levels.
Figure 4.27 shows how the cross regulated outputs behave during the transient observed before. It was
predictable that a load transient in the main output would also affect the cross regulated outputs the same
Response time
55
way, due to the nature of the control scheme. The overshoot or undershoot in regulated outputs have similar
waveform as the main output, apart from a scaling factor associated with the transformer winding relation.
Figure 4.27: Mainly and cross regulated output voltages transient response to a step load in the main output, for different
input voltage levels.
iii. Cross regulated output step load (CCM)
If the step load happens to occur in one of the cross-regulated output, the converter will also attempt to
recover from the perturbation, but at the cost of disturbing the main output also, like next figure shows:
Figure 4.28: Output voltage response for a step load transient in the 4.5 V output.
iv. Main output step load (DCM)
The next simulation result that is going to be presented is the operation in DCM. The converter compensator
was dimensioned assuming CCM operation, therefore the correct DCM dynamic behavior needs to be
simulated and observed. For this simulation the cross-regulated outputs were put in open circuit and the main
output was loaded with its minimum current level, according to specification table of Appendix A.3.
In Figure 4.29 it is explicit that when the converter exits DCM by the occurrence of a load step, some
oscillations occur due to the compensator not being dimensioned to this conduction regime. Even though there
is an oscillation, it is completely dumped after 30 µs and its amplitude is still under the admissible limit. The
majority of the current levels of operation of this forward converter are not in DCM, which it can be safely
assumed that the converter is stable for the majority of operational points.
56
Figure 4.29: Output voltages, main output inductor [I(Ls1)] and load currents [I(S1)] during load steps in DCM conditions.
v. Input voltage step
The next and final simulation will show the DC/DC converter robustness to changes in the input voltage. The
input source will be stepped from the lowest to higher values, according to the specifications. The effect of this
step will be observed in the output voltage (Figure 4.30).
Figure 4.30: Input voltage source (red) and output voltage (blue) during input source transient steps.
4.2. PFM control
Pulse Frequency Modulation control is explained in chapter 3.2.2. This chapter will instead focus on
evaluating whether PFM is worth using and in what conditions it can be used to improve the converter
efficiency.
The forward converter will be simulated in steady state for both PWM and PFM modes and for several
different output load levels. The efficiency vs. load curve will be traced in order to determine the ideal point of
transition between the two control methods. Afterwards, a circuit topology to control the toggling between
control modes will be presented.
4.2.1. Determining efficiency
The losses in a DC/DC converter power stage can be characterized in two main types: conduction loses and
switching loses.
57
Conduction loses can be easily modeled in a circuit simulator by introducing parasitic resistors and voltage
sources in the semiconductor models to simulate both joule and conduction voltage drop losses.
Switching losses occur due to the inability of the power semiconductors to instantly nullify the current
circulating through them. Because the rise and fall times of the current and voltage across these devices are
finite, there are brief periods of time in which both current and voltage exists in the semiconductor, originating
loses. This finite fall and rise time can be simulated by introducing parasitic capacitances in parallel to the ideal
diode and switch model, as shown in the model used for the power MOSFET transistor in Figure 4.31.
Figure 4.31: Power MOSFET model and symbol used in efficiency calculation simulation.
Using this MOSFET model in the previous forward converter power stage schematic of Appendix A.8 and
replacing the PWM controller block by the PFM controller presented in Appendix A.8.6, the simulations can
now be done in PFM mode.
To plot now the efficiency vs. load curve, the converter was simulated for many different values of output
loads, ranging from 0.2 to 3 W and in both control modes. The obtained plot is presented in Figure 4.32.
Figure 4.32: Efficiency vs. Output load power for input voltage equal to 28 V.
From the figure it is noticeable that for loads greater than half of the maximum load the two methods offer
identical efficiencies, with the PWM method exhibiting slightly greater efficiencies than PFM. PFM method
0,7
0,72
0,74
0,76
0,78
0,8
0,82
0,84
0,86
0,88
0,9
0 0,2 0,4 0,6 0,8 1 1,2 1,4 1,6 1,8 2 2,2 2,4 2,6 2,8 3
Effi
cie
ncy
Output power [W]
PWM
PFM
Drain
Gate
Source
9%
PWM PFM
58
efficiency is decreased for higher loads because the switching frequency is approximately proportional to the
output load. If the load is high, the switching frequency tends to rise, increasing the switching losses. This along
with the higher voltage ripples puts aside the PFM method for high load conditions.
Although, for loads smaller than half of maximum load the PFM technique triumphs over PWM, due to the
lower ripple and also higher efficiency. For loads smaller than 800 mW (approximately ¼ of maximum load),
PFM mode shows a gain of up to 9% in efficiency comparing to PWM. This suggests that the optimal transition
point would be somewhere near between 20 and 25% of maximum output load, if the voltage ripple is lower
than the design specifications.
The plot of Figure 4.32 was done with simulations using an input voltage of 28 V. Different input voltages
were tried but no major effect on the efficiency curve was observed, unlike what Figure 3.7 presented. [27]
4.2.2. Control mode toggling
One of the most delicate issues found by previous works addressing a DC/DC converter toggling between
PWM and PFM was the technique used to execute the toggling. The dynamic response of PFM method is
known to create high output voltage over and undershoots, therefore it is not recommended to allow PFM to
deal with step loads, when they occur.
Figure 4.33: Output voltage plot of a buck converter toggling between PWM and PFM modes. [3]
To know when the right time to toggle, the control circuit has to sample the output power or some other
variable related to this quantity. The only state variable the control can access circuit in a forward converter is
the current in the primary side of the transformer, therefore the decision to toggle will depend on this variable,
more precisely one fourth of its maximum value.
However, the mode toggling cannot occur exactly when the current changes its value, in order to avoid the
behavior of Figure 4.33. The mode swap must happen only after the transient perturbation has been corrected
by the PWM mode. When the output load resumes its steady state value again, it is safe to toggle the control
method, with no risk of a large output voltage perturbation. This suggests that a delay must be introduced
between the instant the current reaches the threshold value of ¼ of maximum current and the mode swap.
a) PFM flag generator In order to implement this delay two different flag signals are needed for this circuit. The first flag signal ( )
will tell when the current is below its threshold value. When this flag is activated it enables a counter that after
PWM PFM PWM
59
a certain number of switching periods will trigger the second flag ( ), issuing a mode swap from PWM to
PFM. In order to return to PWM mode the current level needs to surpass its threshold level, in which the PFM
flag is immediately deactivated. This way the delay only exists when entering PFM mode, as intended.
Sample
&
Hold
KI (vIsense+Vios)
+
-
vref
vclock
nbit
COUNTER
RST
b0
b1
b2
...
bn
R
SQ
Counter Reset
Latch Reset
Figure 4.34: PFM flag generation circuit schematic.
Figure 4.34 shows the proposed PFM flag generation circuit schematic. The sample & hold circuit samples
the sensed current signal into a continuous signal that can be compared using the hysteric comparator. This
comparator generates the flag, which assumes the logic level ‘high’ when the current is under the threshold.
In this situation the counter is enabled, counting switching cycles until all bits have logic level ‘high’. The n-
input AND gate detects this condition and sets the SR Latch, putting its Q output ( ) on ‘high’. This toggles
the converter from PWM to PFM mode. If switches from ‘high’ to ‘low’, before the counter has all its output
bits at ‘high’ or in any other time instant, the latch and the counter are immediately reset, thanks to the
inverter and OR gates, and is set to zero, forcing the converter to PWM mode.
In Figure 4.35 is presented the waveforms of the PFM generation circuit. When the (green) assumes logic
level ‘high’, a 5 bit counter would take 30 switching cycles to set all its outputs to logic level ‘high’. After this
the flag is set to one. The instant goes to zero, is also set to ‘low’. Analyzing the reset signals it is
possible to understand that when the PFM flag is activated the counter is kept on reset, saving power.
Figure 4.35: PFM flag generation waveforms.
b) Toggling point voltage level The current circulating in the power MOSFET is translated to a voltage (vIsense) inside the controller circuit,
and it is this variable that will be compared against the reference voltage, in order to determine when the
control technique is toggled. Previously it was stated that this voltage is amplified and summed to an offset,
which has to be taken into account on dimensioning the voltage that the comparator will react. The maximum
Delay Delay
60
current can be estimated assuming nominal input voltage, its respective duty cycle (Dnom), the maximum output
power and the converter efficiency (η):
(4.43)
Now this current value needs to be translated into the voltage that will determine the toggling point:
(4.44)
4.2.3. System simulations
This section contains some system simulations carried out in LTSpice of the DC/DC converter controlled in
PFM mode alone and in both PWM-PFM with mode toggling.
a) PFM transient analysis Before testing the toggling circuit with the forward converter, it is important to check how PFM mode
behaves during load transients. To evaluate this, a simulation will be done in PFM mode, using the same
conditions has the PWM simulation presented on Figure 4.29. The top circuit schematic is the same as in the
PWM simulations (Appendix A.8.4) but replacing the PWM controller with the PFM controller circuit presented
in Appendix A.8.6. The results are presented in Figure 4.36:
Figure 4.36: Main output step load transient in PFM mode. Main output voltage (red) and main output current (green);
power transistor current (blue).
When the output current (green plot) raises from its minimum value to 40% of maximum load, the output
voltage does not seem to undergo any undershoot, as it is overshadowed by the voltage ripple. Despite this
ripple amplitude surpassing the low frequency voltage ripple specified by ESA (Appendix A.3), the control
technique toggling point can be set to somewhere lower than the current value of this simulation, avoiding
high ripple operation. In the falling current step there is an observable overshoot, but it complies with
specifications.
b) Control mode toggling simulation The next simulation will include both control modes and a load step will be aplied to the main output in
order to observe the toggling. The control circuit block diagram is presented in Figure 4.37, containing both
PWM and PFM control circuits, the toggling circuit and a multiplexer that selects what drive signal is fed to the
power MOSFET.
61
PWM
Control Circuit
PFM
Control Circuit
vIsense
vo
PFM flag
generator
vPWM
vPFM
vdriveDriver
Figure 4.37: Control circuit block diagram featuring PWM and PFM operation and toggling circuit.
In this simulation the toggling points were set to 1.4 V and 1.8 V, respectively the low and high values of the
hysteris flanks, and the power stage is loaded first with 50 Ω in the main output and 100 Ω in the cross-
regulated outputs, so that the power is low enough to trigger PFM mode. At 250µs a load step is introduced
with the value of 40% of the maximum main output current.
Figure 4.38: Simulation results showing toggling between PWM and PFM modes.
In Figure 4.38 it can be observed that the converter swaps successfully to PWM mode when the output
current increases. When switching back to PFM mode, the delay introduced between the two flags lets PWM
mode handle the transient, decreasing the overshoot amplitude, comparing to Figure 4.36.
PWM PFM PFM Delay
62
5. Feedback insulation
Having the control techniques explained, before presenting the integrated circuit design, it is important to
detail how the feedback insulation is going to be implemented. In chapter 3.3.4 the magnetic insulation was
pointed out to be the most straightforward to implement, and also the most cost-effective, given that it only
requires circuitry on the primary side of the forward converter’s main transformer.
This chapter will present how the magnetic feedback will be implemented and will show several simulation
results of the converter operating with the magnetic feedback.
5.1. PWM control with magnetic insulation
The only modification introduced by magnetic insulation is how the feedback output voltage is fed back to
the PWM control circuit. While without insulation the output voltage is sampled directly with a resistive
voltage divider, with magnetic insulation the voltage divider persists but it is preceded by the sample and hold
and a rectifier circuits, according to Figure 5.1.
Figure 5.1: Magnetic insulation circuit schematic.
The rectification circuit is placed to make sure that no negative voltage enters inside the integrated circuit.
The Dfw is a free-wheel diode makes sure that the sampling inductor current is kept continuous, avoiding
unwanted voltage spikes. The resistors connected to the rectification shottky diodes are placed to limit the
current and to diminish the power dissipation across the diodes. The bias resistors (Rf‘ and Rbias’) are used to
lower the buffer output to the reference voltage level that feeds the error amplifier.
Since the buffer maximum output voltage is VDD, which nominal value is 3.3 V, the sampling inductor winding
relation has to lower the sampled output voltage of 5 V to a voltage level lower than VDD. The chosen winding
relation will also determine the bias resistors dividing factor.
In order to preserve the same control dynamics of the forward converter without feedback insulation, the
bias resistors values must be such that the position of the poles and zero of the compensator is maintained.
This is done by ensuring that the parallel of the bias resistors is the same with or without magnetic insulation,
even after the voltage level reductions imposed by the winding relation. This originates because the voltage
63
that feeds the bias resistors has no AC component, therefore in small signal analysis, both resistors are in
parallel and shorted to the ground.
The winding relation nsamp has to be calculated taking into account both the forward voltages of the power
stage diode and the rectifier diode. The voltage level at the output of the buffer (vosample) will determine the
dividing factor (β) to be implemented with a resistive voltage divider.
(5.1)
The values of Rf’ and Rbias’ are computed knowing that their parallel equivalent is equal to the parallel of Rf
and Rbias from Figure 4.16. Solving the following equation system and Rf being the resistor value used to
calculate the compensator passive components – equation (4.39):
|| ||
(5.2)
Since the sampled voltage is only refreshed once per switching cycle, the OPAMP that composes the S&H
circuit must ensure that the voltage across the CH capacitor is buffered to the output, before the a new voltage
is sampled. This requires the GBW of the OPAMP to be greater than 1 MHz. GBW of at least between 3 and 5
MHz is a good compromise between speed and current consumption can be achieved, judging for their
respective time constants.
5.1.1. System simulations
a) b)
Figure 5.2: Forward converter operating with magnetic feedback. a) Output voltage with (green) and without (red) magnetic insulation; b) Output voltage undershot detail: S&H capacitor voltage (red), output voltage (green) and S&H
switch control signal
Having the magnetic feedback insulation technique explained, now it is important to check its viability by
simulating it in operation. Figure 5.2 shows some simulation results for the forward converter with each output
loaded with 1 W. At 500 µs the main output is loaded with an additional 240 mA and is loaded back to 1 W at
600 µs. It can be observed that when magnetic feedback is used the output voltage exhibits a static error when
comparing to the non-isolated converter. This occurs because the sampled inductor voltage not only includes
the forward conducting voltage of the diode but also the resistive voltage drops across the inductor and the
Sampling delay
64
diode itself. The method of compensating this voltage is static, independent of the ohmic losses, therefore
static errors appear. However, these errors retain the voltage under the specified levels.
Observing Figure 5.2 (a), it is visible that the undershot is also greater when using magnetic feedback, due to
the fact that the sampling introduces a delay of one cycle (maximum length), which can be noticed in Figure
5.2b. This delay allows the voltage undershoot to develop further without being corrected. Again the over and
undershoot amplitude are within the specification values and the converter is proven to be stable.
5.2. PFM control with magnetic insulation
Using magnetic feedback introduces the limitation that the voltage can only be sampled when the power
MOSFET is turned OFF, and if there is current circulating in the output inductor. While in PWM mode the power
MOSFET is always turned ON once per switching cycle, in PFM mode that may not happen. If the load is low, it
is very likely that PFM control will not turn the power switch ON for more than one cycle, which poses a
problem of when the output voltage sampling is done. At the same time, if the PFM controller does not know
that the voltage is falling, it will not turn on the power switch.
These two issues combined result in the incompatibility of having magnetic feedback with PFM control,
because the controller will lose track of the real voltage value. The power switch has to be turned ON, for
afterwards be turned off, producing a voltage sample in the process. The result is a voltage level that rises until
the comparator maximum comparing value, and then starts to fall as the controlled loses sight of the real
voltage. This behavior can be shown in Figure 5.3.
Figure 5.3: PFM mode with magnetic feedback. Output voltage (red) and the S&H capacitor voltage (green).
There are two ways to force the voltage sampling. Either by slowly discharging the S&H capacitor, artificially
feeding the PFM comparator the illusion that the output voltage slowly drops if it the power switch is not
turned on; or by forcing the power switch ON at a frequency much lower than the PWM switching frequency.
However, both of the previously described methods would force a switching frequency value in PFM mode,
which goes against the very nature of this variable frequency control mode and reduces the efficiency benefits.
Figure 5.4: Forced PFM mode with magnetic feedback. Each 4µs the power MOS is turned ON just to sample the output
voltage. Green is the output voltage and blue is the gate to source voltage in the power MOSFET.
65
6. Implemented integrated circuit
Now that the circuit implementation was studied and decided, the new proposed top level diagram block
will be presented. This diagram block is presented in Appendix A.9. Note that some blocks that were not
implemented for this dissertation are represented with a dark gray tint. Their functionally had to be tested and
edited to accommodate the new proposed features.
The projected diagram block contemplates all the proposed pins; reference circuits, such as the band gap
voltage reference and the reference current generators; the oscillator; undervoltage lockout block (UVLO);
short-circuit protection and the PWM control circuit blocks. The oscillator was chosen to have a frequency of
16 MHz, because the compensation ramp signal is implemented with a counter and a digital to analog
converter. In order to have the highest precision in its slope, the counter needed also a relatively high bit value.
In this case, 16 MHz makes 4 bits for a switching frequency of 1 MHz. The soft-start block guarantees that the
reference voltage that feeds the error amplifier ramps up slowly, preventing an overshoot in the startup. The
four input AND gate ensures that the power transistor is only driven when supposed to, that is, when the
circuit is not powered down, when the input voltage is over the lockout value, while the PWM controller
commands it and when the clock signal has logic value ‘high’. This last condition is a restriction imposed by the
forward converter topology, since this converter was sized to work for duty cycles less than 50%, in order to
prevent the transformer saturation. The UVLO block is fed with a portion of the input voltage, created by a
resistive divider. The short-circuit block compares the amplified current signal with a reference and generates a
short circuit flag (vShCric) that when it assumes logic level ‘high’, resets immediately the SR latch, cutting off the
power transistor. This effectively limits the current circulating in the power transistor to a set value. The Irefbias
and OSCbias pins are connected to discrete resistors that determine the current reference and the oscillator
frequency values, respectively. The sensing winding responsible for the magnetic insulation is connected via
the circuitry presented before (Figure 5.1) to the VoSense pin. The S&H output is connected to the VoSample pin,
which connects to the compensation network of the error amplifier by the vfb (feedback voltage) and vc (control
voltage) pins. The reason why the compensation components were chosen to be discrete will be explained in
section 6.8 of this chapter. With discrete compensation components the controller becomes usable for more
than one single application. To preserve this flexibility, the compensation ramp slope also depends on an
external resistor (Rramp).
Given the reasons presented in chapter 5.2, this controller does not incorporate the PFM control mode. The
tight ESA specifications regarding the ripple and frequency value, (check appendixes A.2 and A.3) along with
the incompatibility with the implemented magnetic insulation, put aside this control mode. Forcing a switching
frequency to PFM mode would degrade the extra efficiency gain comparing to PWM, therefore there is no real
advantage in exploiting it.
A clear and straightforward example where PFM with magnetic insulation would fail would be if a step load
were to be applied to one of the outputs. If this extra load does not cause the PFM mode to toggle back to
66
PWM, due to its small value, the output voltage would undergo an undershoot, until the forced pulse caused
the output voltage to be sampled and fed back to the hysteretic comparator. Until that happens the controller
would not notice there was a perturbation, and it would remain unmitigated for that time period, which is
unacceptable for high reliability applications such as the space industry.
This chapter will present the circuit blocks that constitute the integrated circuit that will control the forward
DC/DC converter. The integrated circuit was implemented in CADENCE, using the Schematic tool and the
simulations were carried out in Analog Design Environment using Spectre or UltraSim, for individual block or
multiple blocks simulations, respectively.
6.1. Soft-start
The circuit also includes a soft-start feature with the startup time being controllable by an exterior discrete
capacitor connected to the vrefStartup pin. While the voltage at this pin is lower than the band-gap voltage, the
reference voltage that feeds the error amplifier and the PFM comparator is the vrefStartup voltage. When this
voltage is greater than vrefBG, then the band-gap voltage reference is used instead. The soft start
implementation is presented in Figure 6.1:
VDD3V3
Cstart
Rstart1
Rstart2
vrefStartup
Band gap
voltage reference
-
+
vrefBG
fstartup vref
PD
PD
a) b)
Figure 6.1: a) Startup circuit schematic; b) Reference voltage waveforms during startup.
If Rstart1 and Rstart2 have the same values and equal to Rstart, to compute Cstart is rewriting the equation shown
in Figure 6.1 (b) in respect to the capacitance value. The transistors commanded by the power down signal will
make sure that when the power down signal has logic value ‘high’, the reference voltage drops to zero,
shutting down the DC/DC converter. The implemented circuit schematic is presented in Appendix A.12.2.
(
) (6.1)
6.2. D Flip-Flop with triple modular redundancy
The D Flip-Flop will be the basic building block of the 4-bit counter which will generate the clock signal that
sets the switching period. It is very important to ensure that these blocks are radiation hardened so if a SET
occurs the clock signal has less probability of being perturbed, which can lead to the an involuntary and
erroneous power MOSFET conduction command. For this purpose the RHBD philosophy was employed in each
D flip-flop, in particular the triple modular redundancy that was presented in chapter 2.5.3b).
Each individual D flip-flop topology is the classical master-slave architecture with one feedback loop in each
portion of the circuit (Figure 6.2a). The redundancy is ensured by having three D flip-flops connected to two
voters, one for each output (Figure 6.2b).
67
RST
RST
____
CLK
CLK
____
CLK
CLK
PD
D
Q
__
Q
a) CLK
D Q
__
Q
CLK
D Q
__
Q
CLK
D Q
__
QVOTER
A
B
C
Y
VOTERA
B
C
Y
D
CLK
Q
__
Q
b) Figure 6.2: a) D Flip-Flop schematic with reset functionality; b) D Flip-Flop with triple modular redundancy.
Now simulating the D flip-flop with redundancy and in counter arrangement gives the following waveforms.
Note the outputs have exactly half the frequency of the input clock.
Figure 6.3: D-Flip-Flop waveforms in counter topology. Red: input clock; green: D output; violet: negated D output; blue:
reset signal; purple: power down signal
6.3. Digital to analog converter – ramp generator
The compensation ramp is generated by taking each output of the 4-bit counter and converting their bit
values into an analog output. The topology chosen is presented in Figure 6.4.
vDD
Iref
vDD
2Iref
b0 b1
vDD
4Iref
b2
RSTRramp
Cramp
(a)
(b)
Figure 6.4: (a) Digital to analog converter circuit schematic; (b) corner simulations of the vramp signal for Rramp = 464 Ω.
68
The counter output bits drive the gates of transistor switches. When the switches are turned ON, they let a
current (proportional to the sum of the total bit weight) through a resistor (Rramp). This resistor converts the
current into a voltage, which its maximum value is determined by the resistance value used:
(6.2)
Since the forward converter will not be used for duty cycles greater than 50%, the ramp will only be summed
to the current sensed signal during half of the switching period, in order to save current consumption. The
voltage across the resistor must be two times greater than the actual intended ramp voltage, because the sum
of the amplified current signal with the compensation ramp voltage is implemented with a resistive divider.
The switch controlled by a reset signal will make sure that for the second half of the switching cycle the
output is shorted to GND. The current mirrors feeding the Rramp resistor will also be shut down to avoid the
appearance of a residual voltage across the switch during the reset period. The implemented circuit schematic
is presented in Appendix A.12.1.
6.4. 4-bit counter
The 4-bit counter designed must ensure that the duty cycle is very close to 50% in all corners, because the
generated clock signal will also be used to limit the duty cycle of the DC/DC converter to 50%, in order to avoid
transformer saturation. The 4-bit counter topology is presented in Figure 6.5 (a) along with simulation results in
Figure 6.5 (b) proving that the duty cycle and frequency are close to the intended values.
CLK
D Q
__
Q CLK
D Q
__
QCLK
__
b0
b0CLK
D Q
__
Q
__
b1
b1CLK
D Q
__
Q
__
b2
b2
__
b3
b3
a)
b)
Figure 6.5: a) 4-bit counter circuit schematic; b) transient simulation waveforms.
69
6.5. Ramp and current signal summing circuit
The current signal to be compared with the control voltage must be summed with the compensation ramp,
in order to dump the subharmonic oscillations (described in chapter 4.1.1a)). To avoid using an operational
amplifier to implement this sum, the circuit is implemented instead with two resistors each one connected to
the signals that are intended to be summed (Figure 6.6).
v2v1
voRR
Figure 6.6: Averaging circuit used to implement a sum.
Ensuring that the resistors have equal resistance value, the node in between the two resistors develops a
voltage that is given by the following equation:
(6.3)
6.6. Sample and Hold circuit
In order to avoid the very well-known issue of clock-feedthrough among sample and hold circuits, caused by
unintended charge injections, the S&H circuit that will be used cannot simply be composed by a CMOS switch
and a capacitor. In order to mitigate this abnormality, the S&H circuit topology was chosen according to
reference [35] (Figure 6.1a). When Q1 and Q2 are turned on, the circuit behaves like a classical S&H, meaning
that Vin value is sampled to the C1 capacitor. The OPAMP will respond to the voltage change in the input, and
since Q2 closes the negative feedback loop, the output will approach to Vin. If both capacitors are identical, then
the charge feedthrough in Q1 will be equal to Q2, which ideally would cancel out in the output.
(a)
1 M8: : M5
Iref
IDS2
Cc
CL RL
ILoadQ1 Q2
Q3 Q4
Q5
Q6
Q7 Q8
IDS6
v+v-
vo
IDS5
Rc
b)
Figure 6.7: (a) Sample and hold circuit schematic; (b) Two-stage operational amplifier circuit schematic
The OPAMP that implements the buffer must be design to have low impedance, since it will drive a resistive
load and to guarantee the charge feedthrough cancelation.
For these specifications the chosen topology is the two-stage operational transconductance amplifier (OTA)
presented in Figure 6.7b. The design steps for this amplifier can be found in Appendix A.10
The obtained operational amplifier has the following open loop bode plot for several corners.
70
Figure 6.8: AC simulation exhibiting the open loop characteristic of the S&H amplifier for various corners.
The implemented circuit schematics are presented in Appendixes A.12.3, A.12.5 and A.12.6, respectively the
S&H amplifier, the sample clock signal generator and the actual S&H circuit.
6.7. PWM comparator
The PWM comparator was implemented with a PMOS differential pair in the previous works, which meant
that for high levels of input voltage the comparator would stop comparing correctly. For this dissertation the
PWM comparator will be designed with an NMOS differential pair, since the input voltage will never be below
the minimum input voltage at which the comparator can handle, because an offset voltage is introduced in the
current signal amplification stage.
The comparator topology chosen is presented in Figure 6.9 (a), which offers fast response times with less
power consumption, ideal for DC/DC converters. The transistors M3 and M4 were chosen to be equal to the M3‘
and M4’, in order to minimize the intrinsic hysteresis introduced by this topology. [35]
Figure 6.9b shows minimum input voltage value of 750 mV needed to ensure the comparator operates
correctly.
The implemented circuit schematic is presented in Appendix A.12.4.
71
Iref
M1 M2
M3 M4
M9 M10
v+ v-vout
M3' M4'
M5 M6
M7 M8 M11
M12
(a)
(b) Figure 6.9: (a) PWM comparator topology; (b) Upmost wind represents the input voltages; the windows bellow show three different output signals for three different corners (red represents the worst case, yellow the nominal and green the best
base).
6.8. Error amplifier
The error amplifier is a crucial component in the PWM control loop. The way this amplifier is implemented
will impact the stability of the whole DC/DC converter, therefore a sufficiently high GBW and a stable phase
margin must be ensured. It was considered in 4.1.2f)iii that the GBW of the error amplifier must be greater
than 3 MHz, in order to maintain a good overall phase margin, being the target GBW of 10 MHz with minimal
impact to stability. (Figure 4.22)
The error amplifier was put to test in corner simulations and the resulting open loop bode plots are
presented below, showing a GBW greater than 10 MHz for all corners:
Figure 6.10: AC simulation exhibiting the open loop characteristic of the error amplifier for various corners.
72
The compensation network passive component values were computed using equations (4.39) and the values
for the 3 W output power and 28 V input voltage converter are presented in Appendix A.11. Due to the large
capacitance and resistor values, these components were chosen to be place outside of the integrated circuit,
otherwise it would require large integrated circuit areas to design such components. However, using discrete
components makes the compensator vulnerable to bonding wires, which will have to be taken into account for
the top simulation.
The larger capacitor could have been implemented in a MOSCAP, using a transistor thin oxide gate, but
since the DC/DC converter is operating in space environment, radiation can cause the CV curve (Figure 2.6) of
these capacitors to undergo significant changes, having a major influence on stability and which can be hard to
compensate.
The obtained compensation parameters values, along with other relevant computations, are presented in
Appendix A.11.
6.9. Implemented blocks summary
The following table summarizes all the important parameters values that could be achieved for each circuit
block presented before.
Table 6.1: Implemented blocks summary table presenting the obtained relevant circuit parameter values. The shaded lines are referent to blocks that were implemented in previous works on this subject.
Circuit blocks Parameter Typical value Worst case corner value
Minimum Maximum
Band-gap voltage reference
Reference voltage 1,227 V 1,213 V 1,237 V
Reference current 10,23 µA 10,12 µA 10,32 µA
Startup time 16 µs 12 µs 20 µs
Average current consumption 121,2 µA 110,7 µA 192,8 µA
Ring oscillator
Frequency 15,84 MHz 9,98 MHz 28,48 MHz
Duty cycle 51,83% 49,19% 55,61%
Rise time 0,598 ns 0,355 ns 1,466 ns
Startup time 16 ns 5 ns 22 ns
Average current consumption 49,61 µA 29,99 µA 97,31 µA
Under voltage lockout Voltage threshold 19,56 V 17,94 V 19,98 V
Average current consumption 102,2 µA 96,12 µA 112,7 µA
Driver + Non-overlap + Level Shifter
Delay 13,14 ns 7,80 ns 23,18 ns
Average current consumption 4,231 mA 4,188 mA 4,382 mA
Error Amplifier
GBW 19,1 MHz 11,5 MHz 40,9 MHz
Phase margin 82,8º 72,2º 86,3º
Low frequency gain 81,4 dB 83,7 dB 78,3 dB
Average current consumption 137,8 µA 134,6 µA 143,0 µA
Sample & Hold Amplifier
GBW 7,6 MHz 5,8 MHz 10,4 MHz
Phase margin 77,4º 74,2º 80,9º
Low frequency gain 72,4 dB 68,4 dB 75,6 dB
Average current consumption 183,6 µA 177,3 µA 192,8 µA
3-bit Digital to Analog Converter
Maximum voltage 36,33 mV 32,18 mV 37,43 mV
Average current consumption 52,15 µA 49,21 µA 56,71 µA
4-bit counter
Clock signal frequency (Fsw) 1,005 MHz 1,000 MHz 1,006 MHz
Duty cycle 49,74% 49,71% 50,00%
Average current consumption 78,73 µA 66,20 µA 99,91 µA
PWM Comparator Delay 1,82 ns 2,84 ns 3,85 ns
Average current consumption 45,98 µA 42,69 µA 51,34 µA
73
7. Top simulations
This chapter contains the results taken from the top simulation of the forward converter carried out with
Ultrasim. The simulated circuit schematic is presented in Appendix A.15, along with the test-bench used in
Appendix A.14 and the entire parameter sizing computations are presented in Appendix A.11.
In this top simulation both line and load regulation will be put to test. The simulation lasts 700 µs, and for
the first 300 µs the converter is started with input voltage equal to 28 V. At 300 µs the input voltage is stepped
down to 21 V, and at 500 µs it assumes the maximum level of 37 V. During these intervals the load applied to
the main output is stepped by a value 40% of the maximum current value (240 mA). The main output is
permanently loaded with 200 mA and the secondary outputs are loaded with 0.5 W each. The circuit is
powered down at instant 690 µs, in order to observe the power down current consumption and the effect on
the output voltage.
The first simulation is done without including bonding wires between the converter and the outside discrete
components. The results are presented in the figure below:
Figure 7.1: Top simulation results.
From the results is clearly observable that the controller circuit can maintain the output voltages very close
to their nominal values, and that the ripple is under the specifications. It can also be observed the reference
voltage with the soft-start feature, only reaching the bandgap voltage about 100 µs after the startup, according
to intended. The short-circuit block also limits the inductor current at the value of 1.5 A, by automatically
closing the power switch when this value is reached, for example, during the startup. It is also noticeable that
Output voltages
Main output inductor current (white) and main output load current (blue)
Sensed current signal
Reference voltage
Short circuit latch reset voltage
Power stage input voltage
74
shortly before the end of the simulation, the voltage starts to ramp down as a result of powering down the
circuit.
The power consumption of both the 3,3 and 5 V supply rails were measured in 390,6 µA and 3,595 mA,
respectively, totaling a power consumption of about 20 mW for the controller circuit. The magnetic insulation
circuitry alone consumed 189,6 µA, proving in fact its power consumption superiority over other methods. The
power down current was measured in less than 10 µA, less than some market available solutions (chapter 3.4).
About the dynamic behavior, the output voltage level is very resilience against input voltage steps, which is a
good advantage of current-mode control. Despite, for output load steps, the output voltages display some
oscillatory behaviors that were not predicted in the LTSpice system simulation results (see section 5.1.1). This
oscillatory behavior can be observed in Figure 7.2 and Figure 7.3, for two different input voltage values (28 and
21 V, respectively).
Figure 7.2: Top simulation results – detail of a load step transient with input voltage of 28 V.
Figure 7.3: Top simulation results – detail of a load step transient with input voltage of 21 V.
Main output voltage
Sample & Hold voltage
Main output current
Control voltage (orange) and vpwm+ (purple)
Driver voltage
Main output voltage
Sample & Hold voltage
Control voltage (orange) and vpwm+ (purple)
Driver voltage
Main output current
75
For the input voltage of 28 V, the causes may be related to the 50% duty cycle limitation, because shortly
after the step load was applied, the duty cycle is capped at 50%, and that has a big impact on the way the
controller mitigates the perturbation. Also when comparing the waveforms of the S&H voltage with the output
voltage, it shows that there is a slight delay in between the two. This delay is caused by the fact that the
voltage sampling is only done after the power transistor has actuated in the circuit. Errors in the output votlage
that are sampled in a given time instant are only mitigated one switching period after. This delay is more
predominant in the first switching cycles after the step load, because the voltage variation is greater in this
period. These two factors combined lead to this abnormal oscillatory behavior that without magnetic feedback
would not occur.
When the input voltage assumes the minimum value (21 V), the duty cycle limitation effect is more
predominant (Figure 7.3). In this case, the control voltage greatly increases to the point where the vpwm+ signal
cannot reach it because of the limited duty cycle, therefore not generating the reset pulse naturally.
As it was stated in the previous chapter, it is important to determine the effect of the bonding wires, in
order to determine the resilience of the chip against these parasitic effects. All the pins, expect for the supply
voltages and ground pins, were connected to the outside circuitry passing first by the pad, bonding wire and
pin model that is presented in the figure bellow.
Figure 7.4: Pad, bonding wire and pin model uses in top simulation.
The 2 pF capacitance simulates the pad parasitic capacitance; the inductance and resistance, the bonding
wire parasitic inductance (5 nH) and resistance (10 mΩ) and the 4 pF capacitor represents the capacitance of
the pin to PCB ground. Note that 5 nH of bounding wire parasitic inductance is a worst case value, depending
on the IC packaging technology used. For example if a BGA (Ball Grid Array) packing is used this bounding wire
inductance can be greatly diminished to less than 1 nH.
The supply voltage and ground pins were not connected with the bonding wire model because it would
cause ground bounce issues. This phenomenon is a variation in the supply voltage level caused by the parasitic
inductances of the bonding wires. When there is a quick current transient, primarily caused by digital blocks,
the current spike flowing through the inductance creates a voltage drop that can cause the supply voltage
inside the chip to undershoot or oscillate. This can be avoided by placing large capacitors on-chip.
Assuming that these capacitors will be connected to the supply buses, and that the ground bounce issue is
solved, the circuit can be simulated without the bounding wire models connected to the supply voltage pins.
The simulation results are presented in Figure 7.5.
76
Figure 7.5: Top simulation results with bonding wire models, except for supply and ground pads.
The output voltages exhibit oscillations greater than tolerable, because the duty cycle is varying from cycle
to cycle, when the output voltage is supposed to be stable and continuous.
The reason why this happens is because the sample and hold circuit is still sampling a small ringing due to
the bonding wires, even though there was given a slight delay between the drive and sample clock pulse signal.
This creates an erroneous perturbation in the sensed voltage that is fed to the error amplifier and interpreted
as a real perturbation. This causes the control voltage to undergo some perturbations and therefore to impact
the duty cycle stability, creating high ripples. The solution to this would be either increasing the delay at which
the output voltage is sampled, or increasing the time constant of the sample and hold capacitor, in order to
reduce the current spike, therefore reducing the ringing caused by the bonding wire parasitic inductance. This
can be done by placing a resistor in series with the sampling switch, which effectively damps the ringing and
slows the sampling time constant.
Output voltages
Main output current
Reference voltage (pink) and S&H voltage (yellow)
Power stage input voltage
Drive voltage (red) and S&H clock voltage (pink)
S&H voltage (yellow) and VoSense (red)
Control voltage (orange) and vpwm+ signal (purple)
77
8. Conclusions
A DC/DC converter with magnetic insulation designed for space environment was studied in this
dissertation. Most of the objectives of this dissertation were achieved since the galvanic insulation was
successfully implemented (yet with some reliability issues), the PWM current-mode control model was put to
test and its theory validated, the practicality of the PFM mode was carefully analyzed, and the integrated circuit
was design and simulated, however no layout was produced due to time constrains.
It is important now to point out many of the critical design decisions that were taken during this
dissertation. Firstly the feedback insulation was chosen to be implemented with magnetic insulation, because
theoretically it would be the cheapest and less power demanding of the three studied techniques. However, it
turned out that magnetic insulation, as it was implemented for this dissertation, may not be reliable enough
due to parasitic second order effects, for example, the bonding wire parasitic inductances. The critical circuit
block for this magnetic insulation is the sample and hold circuit, because if the output voltage is not sensed
correctly, the whole control scheme is put in jeopardy. For future developments it is recommended that the
feedback insulation scheme has to ensure more reliability. Capacitive insulation technique might be the
solution for a reliable feedback insulation scheme, however the cost of the overall project would most likely
increase, along with power consumption. The second choice that completely overhauled this project is
associated with the exclusion of PFM control mode. The main objective of this dissertation was to design a
DC/DC converter with feedback insulation, being the efficiency second priority when comparing to this
specification. It was realized that with the way feedback insulation was implemented, PFM control is virtually
worthless, since it would offer no additional benefit over PWM, while still giving arise to several stability issues.
Also from the aerospace industry solutions that were found, no one included PFM control with magnetic
insulation.
When analyzing the DC/DC converter control one of the most critical steps in obtaining the right model of
the power stage for the forward converter was acknowledging the mistake Prof. Basso did when deriving the
single output equivalent to the cross-regulated multiple output converter. Prof. Basso did his calculations
assuming the inductors were not sharing the same iron core, which is entirely not true in a cross-regulation
scheme. The considered approach was proven right by system simulations, by observing the converter’s
response to a load transient. AC simulations also proved the multiple output model right, since three different
approaches (two simulations and the bode plot from the analytical model) yielded similar results.
There are still several issues that need to be addressed for future developments, in order for the converter
to pass the ESA specifications. First, the duty cycle limitation to 50% caused some transient stability issues. This
can be mitigated by sizing the transformer winding relation in order to guarantee that the maximum steady
state duty cycle is much lower than 50%. Second, the 16 MHz oscillator exhibits a large frequency value
variation for different corners. In the ESA specification table it was required that the frequency value could not
drift more than 10% of its nominal value, therefore it is preferable to redesign this circuit block to take that into
78
account. Third, the MOSFET driver is consuming too much power (4 mA average). In a future redesign of this
circuit, it is probably advisable to resize the driver to reduce the demanded current. And finally, the corner
simulations were realized by only varying the CMOS transistor parameters. The passive components, such as
capacitors and resistors, which can have 60% drifts from their nominal values, and current and voltage
references shifts, that can also impact the correct operation of the designed circuit, must also be simulated in
corners.
The proposed implemented integrated circuit offers a new high efficiency solution for a fully galvanic
isolated multiple output DC/DC converter for aerospace industry. The used technology (AMS 0.35) led to small
power dissipation in the controller circuits when comparing to other radiation hardened solutions available in
the aerospace market. In addition, this controller circuit is flexible regarding the configuration of the power
stage. It can accommodate any number of outputs, with diverse voltage levels; any range of input voltages; any
level of output powers, where the only alteration that needs to be done is to recalculate the compensation
component values, and size the transformer winding ratios for a proper cross-regulation feature, replace the
current sensing resistor along with all other external components to accommodate the specific application.
This multiple application flexibility can lead to the reduce cost since scaling economics can be applied when the
chip is mass produced for multiple different applications.
79
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82
A. Appendices
A.1. Space design constrains, effects and solutions
Summary table of aerospace design constrains, their effects and proposed solutions.
Parameter Constrain Effects Solution
Temperature
Abrupt temperature variation (between -170 and 900
oC)
High temperature range
Variation in semiconductor parameters: Response time
Threshold voltages
Quiescent currents
Mechanical stress
Corner simulation between -50 and 125 ºC Accommodate electronic circuits
inside spacecraft
Vacuum
Absence of atmosphere
No heat sinking by convection
Material degradation Electrolytic capacitors
explosion
Use ceramic or tantalum capacitors
Heat sink by radiation / conduction (thermal radiators)
Shock and Vibration
Shock of pyrotechnic deployments
Vibration during launch
Mechanical stress Use SMD discrete components
PCB fixated using more than 4 points
Mechanical dampers
Electromagnetic interference
Incoming and outgoing EMI
RF telecoms
Errors in control circuit Noise in input and output
Input filter installation Careful signal integrity PCB and
chip layouts design
Radiation
Cumulative
TID
Threshold voltage shifts
Leakage currents Optocoupler transfer ratio
degradation
Radiation shielding
ELT transistors with guard rings Lateral BJT
Optocouplers not recommended
Not more than three MOS in series
DD Bipolar transistor gain (hFE)
degradation Optocouplers and bipolar
transistors not recommended
Transient SET Transient voltages that
cause logic errors to propagate
Triple modular redundancy
Static SEU SEFI
Change in stored memory bits
Interruption of circuit operation
Test LET immunity
Reduce digital block dependency
Permanent SEL SEB SEGR
Circuit or component permanent destruction
Reduce distance between contact to substrate and transistor
Install guard rings
Reduce reverse cutoff voltage
Power stage must not include more than one power switch in series
Radiation shielding
83
A.2. Compliance table
ESA specifications table
Specification Parameter Symbol Value
3 W 10 W
Electrical specification
Input specification
Voltage nominal value 28 V, 50 V
Voltage range , 21 to 37 V (nominal 28 V) 30 to 52 V (nominal 50 V)
Output specification
Load capacitance < 500 µF
General Specification
Galvanic Isolation between input and output
- < 5 nF, > 1 MΩ
Efficiency > 70 % > 65 %
Switching frequency 1 MHz
Power 3 W 10 W
Startup overshoot - 2% of output nominal voltage
Voltage regulation loop phase margin
50o
Voltage regulation loop gain margin
10 dB
Audio susceptibility attenuation
40 dB
Mechanical Interface specification
Mass - < 34 g < 75 g
Dimensions (width x depth x height)
- < 40x40x20 mm < 60x60x20 mm
Lifetime specification Operational lifetime - (15 years + 3 years of storage)
Thermal specification Operating temperature - -50º C to 125º C
Reliability specification Shock resistance - 2000g, 0.5 ms, 3 axis
Vibration resistance (sinusoidal)
- 20-20000 Hz, 50g, 3 axis
Radiation specification
Total Ionizing Dose capability
> 50 krad
Immunity to SEBO, SEL and SEU
- Immunity to LET of 60 MeV.cm2/mg
Immunity to SEGR - Failure rate 10 times lower than inherent failure of the device
Price specification Cost (production lot of 10) - < 2500 € < 3000 €
84
A.3. Output specifications table
Output Voltage
Parameter Symbol Total output power
3 W 10 W
5.0 V
Control type - Regulated output
Load ,
0.02 to 0.60 A 0.02 to 2.00 A
Output voltage tolerance ,
2% (4.90 to 5.10 V)
Output voltage ripple (low frequency) 50 mVpp
Output voltage ripple (high frequency) - 100 mVpp
Step load transient output voltage variation*
0.3 V
4.5 V
Control type - Cross-regulated output
Load ,
0.07 to 0.67 A 0.07 to 2.22 A
Output voltage tolerance ,
10% (4.05 to 4.95 V)
Output voltage ripple (low frequency) 100 mVpp
Output voltage ripple (high frequency) - 150 mVpp
Step load transient output voltage variation*
0.25 V
3.5 V
Control type - Cross-regulated output
Load ,
0.03 to 0.86 A 0.10 to 2.86 A
Output voltage tolerance ,
10% (3.15 to 3.85 V)
Output voltage ripple (low frequency) 100 mVpp
Output voltage ripple (high frequency) - 150 mVpp
Step load transient output voltage variation*
0.2 V
* Load step of 40% of max load with a slew rate of no less than 1 A/µs
A.4. Power stage parameter design
C1
S
U
vo1
L1D11
D21
DR
C2
vo2
L2D12
D22
Ro3C3
vo3
L3D13
D23
Ro2
Ro1
1
n1
1
n2
n3
1
n2/n1
n3/n1
Figure A.1: Three output forward converter with cross-regulation.
85
This appendix contains the detailed parameter design of the multi-output forward converter in study. The
specification tables provided by ESA (appendices A.2 and A.3) suggest that it is intended to optimize four
different converters regarding different input voltages (28 or 50 V) and total output power (3 or 10 W). To
concretize the calculations and component dimensioning, the converter to be designed will be dimensioned to
support the input voltage of 28 V and output power of 3 W. The design of the other three converters is
analogous. The dimensioning results of all the following computed parameters are presented in Appendix A.5.
A.4.1. Transformer
An important feature of the forward converter transformer is the inclusion of the reset winding that recycles
the magnetizing current in each switching period. The calculation of the winding ratio between the primary and
reset windings is related to the maximum voltage the power switch has to withstand and it is given by the
following equation:
(
) (A.1)
A power switch designed for space must withstand the lowest possible reverse voltage for reasons pointed
out in chapter 2.5.2. The minimum value for this voltage is when nr is equal to one, which will be the design
option. nr cannot be greater than one, or else the transformer would not have time to demagnetize. Designing
nr smaller than one enables duty cycles greater than 50%, but puts more reverse voltage stress on the power
switch, which is advisable to keep as low as possible for space applications, in order to prevent a SEBO.
The maximum duty cycle, corresponding to the lowest input voltage, will be set to 45%, leaving a small
safety margin between the absolute maximum of 50%. To calculate the primary to secondary winding ratio one
must consider that the input voltage is reflected to the secondary winding multiplied by the winding ratio. This
voltage is then subjected to several voltage drops, which include on the primary side the current sensing
resistor and the power switch voltage drop; and on the secondary side the parasitic voltage drops across the
transformer and output inductor wound turns and the output diodes forward bias voltage.
To compute the winding ratio, an efficiency (ηV) of 90% is assumed, meaning that the power switch must
impose a voltage in the secondary slightly greater than the output voltage, to account for the voltage drops and
loses. The ratio for the 5 V controlled output is then:
(A.2)
For the other two outputs the winding ratio cannot be calculated with the same equation. These outputs are
cross regulated making voltage only dependent on the sensed regulated output voltage. The winding ratio will
be computed knowing that in the worst case there is a total voltage drop between the secondary windings and
the output of Vdrop. The winding ratios for the cross-regulated outputs are given by the following equation:
(A.3)
The minimum duty cycle, corresponding to the maximum input voltage is given by:
(A.4)
86
To compute transformer number of turns and winding inductance, the Ampère’s Law (Equation (A.5)) can be
used along with the Faraday’s Law of Induction (Equation (A.7)), assuming the generic transformer geometry of
Figure A.2:
SCS
B H Φ
C
i
N
Figure A.2: Transformer generic geometry used to calculate the inductance and number of turns.
∮
∬
(A.5)
∬
(A.6)
(A.7)
Assuming that the current that circulates in the primary winding has a square waveform with the maximum
duty cycle of 45%, when the input source exhibits its lowest voltage, then the number of turns of the primary
winding can be computed assuming the maximum flux density (Bmax) the ferrite material can withstand.
According to reference [25], the number of wound turns of the primary winding is giving by:
(A.8)
The winding inductance (LT) can be calculated knowing that the linkage flux is equal to the product between
the current and the inductance:
(A.9)
Finally, the winding resistance is calculated taking into account the skin effect. The skin effect translates a
diminution of the effective area from which alternating current circulates in a conductor due to the penetration
of the electric field through it. In conductors it is characterized by the skin depth (δ) which is the distance from
the surface of the conductor where the current density is e times less than in the surface. If the conductor is
cylindrical then its section area (Ac) and effective conduction area (AJ) are given by Equations (A.10) and (A.11),
respectively.
(A.10)
, since (A.11)
The skin depth is given by Equation (A.12), being ω the angular frequency (2πFsw), µ the magnetic
permeability of copper which is very close to the magnetic permeability of vacuum (µ0) and using the copper
resistivity at the highest tolerated temperature of θ=125 oC, calculated with the copper temperature coefficient
(αCu).
87
√
√
(A.12)
[ ] (A.13)
The total winding resistance including the skin effect can be calculated in respect to the conductor area
resulting in the Equation (A.14).
√
√
√
(A.14)
A.4.2. Inductor
The inductors that compose the filter of each output are essential discrete components which role is
ensuring the current does not have a high amount of ripple. The higher the inductance, the less the ripple, but
also the bigger and heavier the power stage will be, so it is preferred to use the smallest inductors possible.
There is no specification for the inductor current ripple in ESA’s compliance table. Switch-mode power
supply designers normally impose a current ripple equal to 10% the maximum load and compute the required
inductance to attain this. This ripple level requires a big inductance value, so higher ripple values, will have to
be considered in order to reduce the inductor’s size. To accomplish this, a ripple of one third of the maximum
output current was arbitrated.
t
Iomax
iL(t)
Tsw
ΔIo
1.1Iomax
0.9Iomax
DTsw
tTswDTsw
vL(t)
nU-vD1-Vo
vD2-Vo
(a) (b) Figure A.3: Output inductor current (a) and voltage (b) waveforms in one switching period.
The inductance value is computed based on the slopes of inductor current, during certain time intervals and
the voltage applied to it. The corresponding waveforms are illustrated in Figure A.3. Considering the time
interval from DTsw to Tsw, the current ramps down and the voltage is equal to the diode forward voltage
deducted of the output voltage:
(A.15)
Knowing that the duty cycle can vary, the inductance calculation must be calculated for the worst case that
returns the maximum inductance value, which is D equal to zero. The inductor value must be then:
(A.16)
The inductor number of turns can be computed using Equation (A.9) and solve it in respect of Ni.
88
√
(A.17)
The number of turns of the other cross-regulated outputs is computed knowing that the winding relation
from the transformer still holds for the coupled inductors:
(A.18)
The inductor equivalent series resistance can be calculated using Equation (A.14).
A.4.3. Capacitor
There are two criterions to compute the capacitance value. Either the capacitor is dimensioned to ensure a
voltage ripple less than the maximum acceptable low frequency voltage ripple ( ) or to guarantee that under
a load step transient the voltage under and overshoots are less than the maximum tolerable value ( ). The
first method yields typical smaller capacitance values than the second, since the maximum tolerable voltage
ripple and the switching frequency are relatively high.
To compute the capacitance with the second method, something has to be known about the control circuit.
The overshoot will be greater if the controller response time is large. If the controller is fast enough, it will not
let the voltage fall or rise too much. The response time (Tresp) can be defined as the time interval between the
instant the step load is established and the instant at which the voltage undershoot or overshoot reaches its
minimum or maximum value, respectively.
According to reference [25], the controller response time is deeply tied to the compensated open loop
crossover frequency (fc), which will be addressed further on this dissertation, and open loop phase margin. It
does not depend on inductance value, if its time constant combined with load equivalent resistance, is much
smaller than the response time. If the phase margin is designed for values around 70o, the response time can
be given by equation (A.19). This equation holds only if the capacitor’s ESR value is much lesser than the
capacitor’s reactance at the crossover frequency.
(A.19)
When a load transient occurs, the extra load demand is supplied by the capacitor for the duration of the
transient plus the response time that takes the inductor to charge up to the load average current. When the
inductor average current equals the output current, the capacitor starts to charge up, increasing its voltage,
eventually reaching the output steady state voltage. The waveforms that illustrate the previous statement are
shown in Figure A.4. Note that the actual rising current evolution of the capacitor is not linear, but it is
approximated this way to simplify the calculations.
89
t
iC(t)
-ΔIoload
Δtload Tresp
Charge supplied
by the capacitor
(a)
t
io(t)
TrespΔtload
Io
ΔIoload
Charge supplied
by the capacitor
Charge supplied
by the inductor
Io+ΔIoload
(b)
t
vC(t)
Vo
Vo-ΔVoload
ΔVoload
Tresp
(c)
Figure A.4: Sketch waveform of the capacitor current (a), output current (b) and capacitor voltage (c), during a load step transient.
The charge supplied to the load by the capacitor (represented in red shade in Figure A.4b) is proportional to
the capacitor voltage variation, being the capacitance the constant of proportionality. The charge equality is
then given by:
∫
(A.20)
( )
(A.21)
Now combining both equations (A.20) and (A.21), knowing that the charge supplied is symmetrical to the
charge received by the load, the capacitance value is given by:
(A.22)
For example in the 5 V output, and according to the specifications table presented in Appendix A.3,
is
equal to 300 mV, must not be less than 40% of maximum load, in this case 0.24 A, and
corresponds
the time needed to establish 0.24 A at a slew rate of 1 A/µs, or simply put 0.24 µs.
A.5. Power stage passive component values
This appendix contains the passive component values that were used in the design of the forward DC/DC
converter, and that were computed using Appendix A.4 considerations. The presented values are related to the
converter with output power of 3 W and input nominal voltage of 28 V. The design for other applications is
analogous.
90
The parameters values used for the transformer design are presented in the table below. The specific ferrite
values and transformer dimensions were taken from Philips® Components: E cores and accessories datasheet.
Table A.1: Transformer design values used for the parameter calculation.
Parameter Symbol Value
Transformer effective cross section area 2,66×10-6
m2
Maximum flux density of ferrite 0,03 T
Relative magnetic permeability of ferrite 615
Effective transformer length 0,012 m
Copper resistivity at 20 ºC
1,68×10-8
Ω.m
Copper resistivity temperature coefficient 0,0039 ºC
-1
Copper conductor cross section area 5×10-7
m2
Transformer single wound turn conductor length 0,00816 m
The obtained results are presented in the table below:
Table A.2: Transformer parameter values.
Parameter Symbol Value Rounded
value Equation
Winding ratio (5 V) 0,5879 - (A.2)
Number of turns (5 V) 38,677 39 (A.18)
Minimum duty cycle 0,2299 0,22 (A.4)
Winding ratio (4.5 V) 0,5238 - (A.3)
Number of turns (4.5 V) 34,809 35 (A.18)
Winding ratio (3.5 V) 0,4074 - (A.3)
Number of turns (3.5 V) 27,847 28 (A.18)
Number of turns primary 65,789 66 (A.8)
Primary inductance 741,5 µH - (A.9)
Primary inductance resistance 65,5 mΩ - (A.14)
The output filtering passive components values were also calculated and are presented in the table below:
Table A.3: Output passive component values.
Output Voltage
Index Parameter Symbol Value Rounded
value Equation
5.0 V 1
Inductance 25,00 µH 24,67 µH** (A.16)
Number of turns 12,08 12 (A.17)
Primary inductance resistance 11,9 mΩ - (A.14)
Capacitance 2,000 µF 2,4 µF* (A.22)
4.5 V 2
Number of turns 10,87 11 (A.18)
Primary inductance resistance 10,9 mΩ - (A.14)
Capacitance 2,680 µF 3,3 µF* (A.22)
3.5 V 3
Number of turns 8,7 9 (A.18)
Primary inductance resistance 9,0 mΩ - (A.14)
Capacitance 4,300 µF 4,6 µF* (A.22) * The capacitor values were rounded up to standard values assuming a tolerance of 10% (E12). If the rounded value discounted of the tolerance is inferior to the real value, then the next standard value is selected. [36] ** The inductance value was rounded to match an integer number of wound turns.
91
A.6. List of market available DC/DC converters
Selling Enterprise
Model Control
type Radiation resistance
Feedback isolation
Description Picture
CRANE Interpoint Aerospace &
Electronics [37]
SMSA
PWM (voltage-mode with
current limitation)
TID < 100 krad
SEU < 40 MeV
Optocoupler
Flyback converter with single output: 3.3 to 15 V Efficiency: up to 74 % Input voltage: 16 to 40 V Switching freq.: 500 kHz
Power: 5 W Size: 27.3x27.3x6.9 mm
SMHF Temperature compensated
optocoupler
Forward converter with single output: 3.3 to 15 V Efficiency: up to 82 %
Input voltage: 16 to 40 V Switching freq.: 550 kHz Power: 15 W Size: 37.1x28.7x8.4 mm
SMTR Magnetic feedback
Forward converter with up to 3 outputs: 3.3 to 15 V
Efficiency: up to 73 % Input voltage: 16 to 40 V Switching freq.: 600 kHz Power: 30 W Size: 49.5x34.3x10.3 mm
International Rectifier [38]
AHF2815T
PWM (current-mode)
“Radiation insensitive feedback”
Magnetic feedback
Forward converter with triple output: 5 and 15 V Efficiency: 68% to 75% Input voltage: 16 to 40 V Switching freq.: 550 kHz
Power: 8 W Size: 28.5x36.8x8.4 mm
M3G Series
LET up to 82 MeV.cm
2/mg
TID < 200 krad
Forward converter with triple output: 5 and 12 V Efficiency: 70% to 78%
Input voltage: 18 to 50 V Switching freq.: 500 kHz Power: 40 W
AMF28XXS
Series
LET up to 60 MeV.cm
2/mg
TID < 25 krad
Forward converter with single output: 3.3, 5, 7.5, 12 or 15 V Efficiency: 75% to 80 %
Input voltage: 16 to 40 V Switching freq.: 550 kHz Power: 12 W
VPT Inc. [39]
SVSA2800D Series
PWM (current-mode)
LET up to 44
MeV.cm2/mg
TID < 30 krad
Magnetic feedback
Flyback converter with dual output: 5, 12, 15 V
Efficiency: 66% to 77% Input voltage: 15 to 50 V Switching freq.: 450 kHz Power: 6 W
SVGA0510S
Series
LET up to 85 MeV.cm
2/mg
TID < 100 krad
-
Half-bridge non-isolated
converter with single output: 0.8V to 3.4 V Efficiency: 88% to 93% Input voltage: 3.5 to 7 V Switching freq.: 250 kHz Power: 33 W
HOLTEK [40] HT77XXA PFM - -
Step-up topology with single output: up to 25 V Efficiency: < 87% Output voltage ripple: 2.5%
Output current: < 200 mA
-
DIODESTM Incorporated [41]
AP1635 PFM/PWM - -
Step-down topology with single output Efficiency: < 93% Output voltage ripple: 2.5%
Switching freq.: up to 700 kHz
-
ON Semiconductor ® [42]
NCP1406
PFM
(with peak current control)
- -
Step-up topology with single output: 2.7, 3.0, 3.3, 5.0 V Efficiency: < 85% Output voltage ripple: 25mVpp
Output current: < 25 mA
-
92
Switching freq.: up to 1 MHz
LA5744 PWM (voltage-mode)
- -
Step-down topology Efficiency: < 84% Current limiter incorporated Thermal shutdown circuit Switching freq.: 300 kHz
-
LV5990M PWM (current-mode)
- -
Step-down topology
Low power down consumption: 90 µA Switching freq.: 360 kHz
-
CS5141 PWM (V
2 control)
- -
Low voltage buck regulator Efficiency: < 92% Power down current: 85 µA
Thermal shutdown Switching freq.:260 or 520 kHz Under short circuit frequency decreases to ¼ to reduce power dissipation
-
M.S. Kennedy Corp. [43]
BBF2800S Series
PWM Not specified Optocoupler
Isolated step down topology with one output Efficiency: 60% to 74% Switching freq.: 500 kHz
DAC2800D Series
Isolated step down topology with dual outputs: 12 or 15V
Efficiency: < 65% Switching freq.: 400 kHz
5059RH PWM (current
mode)
TID < 100 krad -
Step down switching regulator controller Efficiency: 81% to 87%
Switching freq.: 500 kHz (synchronizable to 1 MHz)
Aeroflex [44] PWM5032
PWM (current or voltage mode)
TID < 1 Mrad SEL: Immune to
100 MeV.cm2/mg
SEU: Immune up to 20 MeV.cm
2/mg
Not included
Controller for buck, boost, flyback or push-pull topologies. Switching freq.: max of 1 MHz
Texas Instruments
UC1825A-SP
PWM (current or voltage mode)
TID < 30 krad Not included High-speed PWM controller Switching freq.: max of 1 MHz
A.7. Sensitivity analysis of type-2 error amplifier
with
respect to
Passive components
Sensitivity of
Rz Cz Cp
Pa
ram
ete
rs
fp
fz
93
A.8. LTSpice simulation circuit schematics
A.8.1. Multiple output forward converter AC simulation
schematic using the PWM-switch model
A.8.2. Equivalent single output forward converter AC
simulation schematic using the PWM-switch model
94
A.8.3. Forward converter transient PWM simulation using the
PWM-switch averaged model
A.8.4. Forward converter transient PWM simulation using
switched model
Compensator feedback
Controller
circuit
95
A.8.5. PWM switched model controller schematic
A.8.6. PFM controller schematic
PWM Comparator Error Amplifier
Reference with soft start
96
A.9. Controller circuit complete block diagram
16 MHz
Ring oscillator
vosc16
4-bit Counter
b0b1b2
vCLK
DAC
Ramp Generator
Pulse Generator
vramp
vpulse
Under Voltage
Lockout
Uuvlo
OSCbias
vUVLO
Band Gap
voltage
reference
vrefBG
Current
reference
generator
iref10u
iref20u
Irefbias
irefBG
Soft start
vrefStartup
vref
-
+
Cp
RzCz
vcvfb
vramp
-
+
PWM
comparator
vR
R
S Q
Error
Amplifier
SR LatchvPWMvpwm+
vpulse
vref
vPWM
vPD
vCLK
vUVLO Driver
+
Non Overlap
+
Level Shifter
vdrive
X8+1.6vIsense vIsense
iref10uKI
Current
Amplifier
Sample clock
generator
Sample & HoldvoSense
voSample
Rf’
Rbias’
Short-circuit
protection
vShCirc
vShCirc
vCLKsample
vCLKsample
VDD5V VDD3V3 GND
Rramp Cramp
___
____
PD
A.10. Two-stage operational amplifier design
This appendix includes the steps used to design the two-stage operational amplifier used in the sample &
hold buffer, the error amplifier and the current signal amplifier. The objective is to achieve certain GBW and
power consumption specifications, along with as high as possible static gain. The two-stage amplifier topology
used is presented on Figure 6.7b. The transistor length was chosen to be 0.5 µm, in order to increase the
output incremental transistor resistance, without increasing the gate capacitance too much.
gm2(v+-v-)gm6vo1
ro6 CL
ro2||ro4
Cc Rc
v+-v-~ ~
RL
vo~
Cgs6
vo1~
~~ ~
Figure A.5: Small signal model of the two-stage OTA with compensation.
First the compensation capacitance is chosen to be half of the expected load capacitance:
(A.23)
97
The transconductance of the differential pair transistors is computed in order to achieve the intended gain-
bandwidth product for the calculated compensation capacitance.
(A.24)
With the transconductance value, the DC current flowing through the differential pair transistor can be
computed in order to achieve an overdrive voltage of 80 mV (Vov=Vgs-Vth). This value was chosen to ensure that
the transistor is not polarized in the weak inversion region, and it depends on the selected CMOS technology.
(A.25)
Using now the current equation in the saturation region, the width can be calculated:
(A.26)
According to reference [45], the amplifier stability requirement is met when the frequency of the non-
dominant pole caused by the gate capacitance of the Q6 transistor, must be at least three times GBW.
Assuming that the compensation capacitance is at least three times greater than the parasitic, the non-
dominant pole frequency can be written has equation (A.27) shows. The transconductance is thereby equal to
eight times the differential pair transconductance. This leads to a current flowing in Q6 drain (IDS6) also eight
times greater than IDS1.
⏟
(A.27)
The width of the Q6 transistor is now calculated knowing the drain current from equation (A.25) and the
transconductance.
(A.28)
The transistor Q5 width is calculated knowing how much current is needed by the Q6 transistor to keep the
transconductance at the sized level and by the load. The multiplicity is then calculated knowing the reference
current value and the width of the current mirror transistor.
(A.29)
Finally the compensator resistance Rc is calculated in order to place a zero in between the both poles
created by Cc and Cgs6. The frequency of the zero is given by the following equation:
⁄ (A.30)
If the compensation resistance is greater than 1/gm6, the zero introduced appears in the left half-plane.
However, if the resistor is equal to 1/gm6, no zero is introduced. This requires that the resistor value must be
much greater than the inverse transconductance. The limits to the resistance value are imposed by the non-
dominant pole at fgs6 (3GBW). This results in a resistance in between the following values (the geometric
average is taken):
√
√
(A.31)
98
Now materializing the previous results into actual values for all dimensioned amplifiers, the final values for
the transistor parameters are as presented in Table A.4. Note that some values may not correspond directly to
the values yielded by equations, since ELT transistors have W/L constrains [2], and also because some
parameters were rounded.
Table A.4: Transistor and compensation capacitance values for the designed two-stage operational amplifiers.
Parameter Value
Specification
GBW 10 MHz
CL 10 pF
Load 30 µA
Parameter Value
Technology parameters
kp 58 µA/V2
kn 170 µA/V2
Vov 80 mV
Value
Parameter L Wtotal W M Equation
Transistors
Q1, Q2 0,5 µm 33,9 µm 33,95 µm 1 (A.26)
Q3, Q4 1,0 µm 15,04 µm 15,04 µm 1 -
Q6 0,5 µm 92,4 µm 7,25 µm 13 (A.28)
Q5 1,5 µm - 10,60 µm 13 (A.29)
Q8 1,5 µm - 10,60 µm 3 (A.25)
Compensation Cc 5 pF - - - (A.23)
Rc 650 Ω - - - (A.31)
A.11. Controller circuit parameters calculation
The current sensing resistor was computed assuming a safety margin of 1.5, a current amplifier gain of 8 and
an offset voltage of 1.6 Volt, since the summing with the ramp voltage cuts this voltage in half and at least an
offset of 0.8 Volt must be ensured at the input of the PWM comparator. The primary peak current value was
set to 0.5 A for the 3 W converter.
The controller circuit static gain is calculated knowing the average value of the band gap voltage for all
temperatures.
The β factor is related to the maximum input voltage of the S&H buffer. If this factor is too low the voltage
becomes too high and the amplifier differential pair may longer be in saturation region. However, if the factor
is too low, the output voltage becomes very similar to the reference voltage and the one of the Rbias’ resistor
becomes too large. The input voltage at the buffer was chosen to be 1.5 V, yielding a β factor of 0.818.
The sampling winding ratio was calculated assuming that the power diodes have a forward voltage drop of
0,4 Volt and the rectifier shottky diode 0.2 Volt.
The compensation network parameters are calculated to ensure a phase margin of 80o. The feedback
resistor Rf was set to 50 kΩ because this value offers a good compromise between dissipated power and the
feasibility of the passive component values, so they are not small enough to be negligible when comparing to
parasitic and not large enough to overload the error amplifier.
99
Table A.5: Controller circuit calculated parameter values.
Parameter Symbol Value Rounded
value Equation
Current sensing resistor 0,194 Ω 0,2 Ω (4.33)
Controller circuit static gain (vref/Vo1) 0,2454 - (4.1)
Feedback resistor voltage divider factor 0,818 - (5.2)
Magnetic insulation turns ratio 0,278 - (5.1)
Bias resistor (without magnetic insulation) 16,26 kΩ 16,2 kΩ* (4.39)
Feedback resistor (with magnetic insulation) 15,00 kΩ 15,0 kΩ* (5.2)
Bias resistor (without magnetic insulation) 67,42 kΩ 68,1 kΩ* (5.2)
Compensation network capacitor ‘p’ 1,564 pF 1,54 pF (4.39)
Compensation network capacitor ‘z’ 141,4 pF 140 pF (4.39)
Compensation network resistor ‘z’ 107,9 kΩ 110 kΩ (4.39)
Compensator pole frequency 949,9 kHz - (4.42)
Compensator zero frequency 10,3 kHz - (4.42)
Primary transformer current slope 142 kA/s - (4.28)
Compensation slope 28,4 kV/s 30 kV/s (4.30)
Digital to Analog converter resistor 429 Ω 464 Ω* (6.2) * Rounded value assuming 2% resistance tolerance. [36]
100
A.12. Implemented blocks circuit schematics
A.12.1. Digital-to-analog converter
A.12.2. Soft-start
101
A.12.3. Sample & Hold amplifier
A.12.4. PWM comparator
102
A.12.5. Sample clock generator
A.12.6. Sample & Hold circuit
103
A.13. PWM controller top circuit schematic
104
A.14. Forward converter test-bench
Insulation barrier
105
A.15. Circuit schematic of the three output forward converter with magnetic insulation
Uuvlo
OSCbias
Irefbias
vIsense
voSense
PD
vramp
vc
vfb
voSample
Cp
Rz
Cz
Rf’
Rbias’
vrefStartup
VDD5VVDD3V3
GND
vdrive
VDD3V3
Cstart
Rstart1
Rstart2
PD
PD
Rirefbias
Rirefbias
RrampCramp
C1
S
vo1
L1D11
D21
DR
C2
vo2
L2D12
D22
Ro3C3
vo3
L3D13
D23
Ro2
Ro1
1
n1
1
n2
n3
1
n2/n1
n3/n1
Rsense
RUVLO
U
Dfw
Rfw
RRect nsamp
Isolation BarrierPrimary Side Secondary Side
Drect
Controller
Circuit