10/20/05

SILOS – Verilog Simulator

Compliant to VERILOG - 2001

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Agenda

ß Introduction

ß Starting Silos Project

ß Explorer and Analyzer

ß Source Code Debugging

ß State Machine Design Entry

ß Advanced Debugging Features

ß Finite State Machine Example

ß Gate Level Debugging

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What is SILOS™

ß Verilog(IEEE 1364) Digital Logic Simulatorß Analysis and Debugging Environmentß Waveform Viewer

ß Hierarchical Browser

ß Text editor

ß Code Coverage

ß Finite State Machine Tool

ß Single Step with Breakpoints

ß Trace Gate and RTL events

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Digital Flow

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SILOS Platforms

ß SILOS supportsß Windows

ß SUN Solaris

ß Linux platforms

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SILOS Markets

ß Currentß FPGA (Xilinx, Altera, QuickLogic, Actel, etc.)

ß PLD

ß General Digital Logic

ß Futureß Analog Mixed-Signal

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Agenda: Starting Silos Project

ß Introduction

ß Starting Silos Project

ß Explorer and Analyzer

ß Source Code Debugging

ß State Machine Design Entry

ß Advanced Debugging Features

ß Finite State Machine Example

ß Gate Level Debugging

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“Contents” will display the contents for the Silos User’s Manual. The “NewFeatures” menu provides a short help file on the new features for the Silosrelease.

Starting SILOS

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“User Registration” will show the security block number.

Starting SILOS

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“About Silos” will show the memory usage and version number.

Starting SILOS

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Highlight “Project/New” and press and release the “F1” key on the keyboard to see theon- line help.

Opening a Project

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Project name.rtl

Create a Project

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Double click on a file name toadd it to project.

Project Files

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Drop down arrow for library files.

Project Files

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Input files for the design.

Project Files

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Press “Go” button (F5)

Starting a Simulation

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SS Button for Singe Stepping

Starting a Simulation

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Output Window

Starting a Simulation

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Double clicking on the text in the Output window will open the source file...

Output of a Simulation

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…and highlight the $display statement that caused the text to be printed.

Output of a Simulation

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Agenda: Explorer and Analyzer

ß Introduction

ß Starting Silos Project

ß Explorer and Analyzer

ß Source Code Debugging

ß State Machine Design Entry

ß Advanced Debugging Features

ß Finite State Machine Example

ß Gate Level Debugging

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Open Explorer button

Explorer and Analyzer

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Open Analyzer button

Explorer and Analyzer

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Select signal “clock”

Explorer and Analyzer

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Hold down Ctrl or Shiftkeys while using themouse to selectadditional signals.

Explorer and Analyzer

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Click with the rightmouse button to openthe context menu andselect “Sort by Name”.

Explorer and Analyzer

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Drag and drop signalsto “Name” list box inData Analyzer.

Explorer and Analyzer

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Input ports point right.

Output ports point left.

Non-port variable symbols:

“dumbell” symbol is a wire

“flop” symbol is a register

is a real variable

is a parameter

is an integer

Explorer - Symbols

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Context menu (use right mouse button).

Explorer - Context Menu

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Click here to expand and contract hierarchy.

Explorer

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Use right mouse button to see the context menu.

Explorer

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Agenda: Source Code Debugging

ß Introduction

ß Starting Silos Project

ß Explorer and Analyzer

ß Source Code Debugging

ß State Machine Design Entry

ß Advanced Debugging Features

ß Finite State Machine Example

ß Gate Level Debugging

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“Open File” button toopen file “vendtest.v”.

Source Code Waveforms

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Double click on variable“pad” and drag and drop“pad” into the Namecolumn to see thewaveform.

Source Code Waveforms

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Highlight expression“enable ? clock :1’bz” and drag and dropit into the Data Analyzerto see the waveform forthe expression.

Source Code Waveforms

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Rearrange the signal names by dragging and dropping them in the SignalName list box.

Rearranging Signal – Drag and Drop

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If “Show Source” in inactive (SSF button not depressed) [1], holding down the “Ctrl” key willtemporarily activate Show Source [2]. You can then left mouse click on the waveform for “clock” tosee the statement that caused “clock” to toggle [3].

Show Source Code

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Setting the blue “T1” marker [1] determines the time point for tracing a signal. Right mouse clickingon the name “newspaper” brings up the context menu [2].

Visual Debug - Time Point for Tracing Signal

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Selecting the Trace Signal Inputs menu selection opens the Trace Signal Inputs window [3].

Visual Debug - Trace Signal Inputs

The top signal, “stimulus newspaper”, is the signal being traced. The next line is the module name “vend”, and instancename, “stimulus.vendY”, which drives the top signal. The next line is the driver, or assignment, in the instance. Subsequentlines indented with a space are the inputs or right hand side (rhs) variables to the driver/assignment. If the driver or rhs variable isa port of the instance it is shown using port name syntax. If it is not a port then just the name of the variable is listed. The signalname preceded by the period, “.newspaper”, is the local port name in module “vend”. The name in the parenthesis,“(newspaper)”, is the name in the module above “stimulus.vendY”. Signal names “coin[1]” and wire “PRES_STATE[1:0]”,the rhs variables in the assignment to “newspaper”, are listed below it and indented one space.

Visual Debug

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Red flashing message in status window warns user of multiple drivers orassignments at a time point while “Show Source” is on.

Visual Debug - Status Window

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To find the cause of the Unknown level on “pad”, right mouse click on thesignal named “pad”..

Visual Debug - “pad”

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..and choose Trace Signal Inputs from the context menu.

Visual Debug - “pad”

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Unknown level on “stimulus.pad” is caused by both enables being low. Left mouseclicking on either driver name “pad” will highlight the corresponding line of source forthat driver.

Visual Debug - “stimulus.pad”

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Red flashing message in status window warns user of multiple drivers orassignments at a time point while “Show Source” is on.

Visual Debug - “stimulus.pad”

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To find the cause of the Unknown level on register “reset”, right mouse clickon the signal named “reset”..

Visual Debug - “reset”

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..and choose Trace Signal Inputs from the context menu.

Visual Debug - “reset”

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The Trace Signal Inputs window shows that two statements assigned to register “stimulus.reset” at T1=.0.055us.The first assignment listed in the Trace Signal Inputs window is the last assignment to ‘reset’ that executed at thistime point. The second statement listed is the next to last assignment to “reset” that executed. Left mouse clickingon the first statement for “reset” shows line 27 of file “vendtest.v” is the last line executed.

Visual Debug - “reset”

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Tracing on “newspaper” in the Data Analyzer brings up the Trace Signal Inputs window, which shows“PRES_STATE[1:0]” and “coin[1]” are the right hand side (rhs) variables that assign the value for newspaper.Double clicking on “PRES_STATE[1]” will refresh the Trace Signal Inputs window, put “PRES_STATE[1]” at thetop, and display the rhs variables for “PRES_STATE[1]”.

Visual Debug

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Select the “Edit/Copy Image to Clipboard” menu to copy the Data Analyzer so it canbe pasted into MS Word. You can use the “Edit/Copy” menu, or “Ctrl+C” on thekeyboard to copy the full path name for a signal to the clipboard.

Report Generation

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Double click on vector “coin[1:0] to expand and hide the bits.

Vector Display

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Agenda: State Machine Design Entry

ß Introduction

ß Starting Silos Project

ß Explorer and Analyzer

ß Source Code Debugging

ß State Machine Design Entry

ß Advanced Debugging Features

ß Finite State Machine Example

ß Gate Level Debugging

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Use the drop down arrows to displaySymbol Table and coin_values.

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Select “coin[1:0]”.Right mouse click to seecontext menu. Then select“Set Radix”.

State Machine Values

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Make sure you click on theminus sign to save thenew radixes.

State Machine Values

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Symbolic names for state values for vectors.

State Machine Values

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Case statement for ASCII vector “info”.

Waveform Annotation

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ASCII text describes the simulation.

Waveform Annotation

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Click with right mouse button in

Signal list Box

Selections for groups.

Grouping Waveforms

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Expression “(clock && coin[1])”. Notice that if you click on theexpression a second time, you can modify the expression.

Conditional Search

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Scan left buttons Scan right buttons Scan Value

Data Analyzer - Scan Buttons

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Put the cursor here to display the timescale, T1 and T2 times, and the delta time.

Data Analyzer - Timescale

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T1 and T2 timing markers, set by the left and rightmouse buttons respectively. Hold down the shiftkey to snap to edge.

Valuefor thesignal

T1, T2, and delta time

Data Analyzer

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Scan to value does a character search, so you can scan a signal that is asingle bit, a vector, or that uses symbolic names.

Data Analyzer - Scan to Value

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Pan Last.Pan to T2 button.Pan to T1 button.

Data Analyzer - Pan Buttons

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Select instance “stimulus”, open thecontext menu with the right mousebutton, and then select “Go tostimulus”.

Data Tips display value, scope, radix, and simulation timepoint for variable clock. The time point can be set by the“T1” timing marker in the Data Analyzer. The Data Tipscan be turned on/off and the radix can be changed byusing the context menu in the source window.

Data Tips

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Agenda: Advanced Debugging Features

ß Introduction

ß Starting Silos Project

ß Explorer and Analyzer

ß Source Code Debugging

ß State Machine Design Entry

ß Advanced Debugging Features

ß Finite State Machine Example

ß Gate Level Debugging

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Click on the “Step” button to open the source window to the line that iscurrently executing.

Single Stepping

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Drag and drop expression “~clock” from file “vendtest.v” [1] to the Data Analyzer and WatchWindow [2].

Notice the Data Tipshows the instantenousvalue for expression“~clock” is “0” at thecurrent timestep.However, the DataAnalyzer is not updateduntil the end of thetimestep, so its valuefor “~clock” is “1”.

Single Stepping

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Single Stepping

Drag and drop expression “reset == 1’b1” [1] into the Data Analyzer [2] andWatch Windows [3].

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Set the value for register PRES_STATE to “3”.

Set and Force

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Breakpoints

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Breakpoints

Put the cursor on this line and click on the Toggle Breakpoint button [1] to set the red breakpointstop sign [2].

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Code Coverage

Code Coverage button should be depressed.Double click on the first line in the Operator report [1] to open the source file at that line. Lines notexecuted have a purple dot [2]. Click on a column header [3] to change the sort order.

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3

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Code Coverage

A large number of “hits” in the “Code Coverage Line Report” may indicate a looping problem in theuser’s design, such as:

always @outout = ~out2 | out1;

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Code Coverage

“Export Code Coverage Data” dialog box can use comma separated datafiles for importing into a spreadsheet program, such as Microsoft Excel.

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Operator Code Coverage

In the Explorer, the red circle with the slash through it means code coverageis disabled for this instance. The green “CC” means code coverage isenabled.

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Operator Code Coverage

The “<” and the “>” operators failed to be true. When expressions havemore than one operator, you can use separate lines to display the purple dotfor each failed operator.

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Operator Code Coverage

Deselecting the “DEFAULT” option, and selecting the other options for theOperator report will show which operands did not affect their correspondingoperator.

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Code coverage results can be merged from batch simulations that usedifferent test benches for the same design.

Merging Code Coverage

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Agenda: Finite State Machine Example

ß Introduction

ß Starting Silos Project

ß Explorer and Analyzer

ß Source Code Debugging

ß State Machine Design Entry

ß Advanced Debugging Features

ß Finite State Machine Example

ß Gate Level Debugging

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FSM Toolbar. State drawing button.

Finite State Machine (FSM) Entry

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Finite State Machine (FSM) Entry

Use the left mouse button when the State Mode is active to create the twostates.

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FSM Entry - Transition Mode

Transition Mode button.

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FSM Entry - Transition Mode

Notice the small circle on state “s1” for drawing the transition between “s1”and “s2”. The circle will move along “s1” as the mouse is moved.

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FSM Entry - Transition Mode

Notice a state symbol can be moved when there is a circle with cross hairs. If instead you seea star on the state symbol, this will change the shape of the state symbol instead of moving it.

Transition between states “s2”and “s1” will change at the next positive clock edge because theexpression has been deleted.

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FSM Entry - Transition Mode

The transition can be redrawn by moving the mouse cursor tangentiallyacross the transition line with the left mouse button held down.

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FSM Entry - Transition Mode

The “+” symbols are for positive edge clock and reset lines. Click on the“+” sign to change it to a “-”.sign for a negative edge reset clock.

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FSM Entry - Notes

Notes can be used to document output signals on the diagram.

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The `include “vending.v” compiler directive is used to include the VerilogHDL source code for the newspaper vending FSM.

FSM Debugging

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FSM Debugging

As the “T1” timing marker is dragged in the DataAnalyzer, the states change color as theybecome active.

Open Instance button

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FSM Debugging

“FSM Scan” button

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To select states for scanning, click on the statewith the left mouse button and hold down the“Ctrl” key.

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FSM Debugging - Finite State Machine Window

The minimized Finite State Machine window shows the active state as youscan in the Data Analyzer.

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Agenda: Gate Level Debugging

ß Introduction

ß Starting Silos Project

ß Explorer and Analyzer

ß Source Code Debugging

ß State Machine Design Entry

ß Advanced Debugging Features

ß Finite State Machine Example

ß Gate Level Debugging

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Gate Level Debugging

Highlight signal “newspaper” and click with the rightmouse button in the Signal Name list box. Select “TraceSignal Inputs” when the context menu opens.

At time=0.021us, “newspaper” changes from Unknownto Low.

1

1 1

x

x

x

newspaper

IN1

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Gate Level Debugging

The top signal, “stimulus.newspaper”, is the signal being traced. The next line is the module name,“VAND”, and instance name, “stimulus.vendY.U118”, which drives the top signal. The next line is thedriver in the instance. Subsequent lines indented with a space are the inputs to the driver. If the driver isa port of the instance it is shown using port name syntax. If it is not a port then just the name of the net islisted. The signal name preceded by the period, “.out”, is the local port name in module “VAND”. Thename in the parenthesis, “(stimulus.newspaper)”, is the wire name in the module above“stimulus.vendY.U118”. Signal name “out” is listed below it and indented one space.

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Gate Level Debugging- Resize Interface

To view the full signal name, use the mouse to drag the vertical bars andincrease the size of the Name column.

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Gate Level Debugging

Gate instance name. The $1 at the end of the name is an IEEE namingconvention for gates that do not have instance names.

Two input “and” gate.

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Gate Level Debugging

“in0” is the local name for the input pin. “\ PRES_STATE[0]” is the wire name in the module above“stimulus.vendY.U118”.

Since both inputs change from Unknown to Low at time=0.020us for this example, double click on

input “in0”.

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Gate Level Debugging - Buffer Gate

Buffer gate [1]

Double-click on the input to the buffer to continue tracing back through thetopology.

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Gate Level Debugging - Buffer Gate - “qqbar”

Three input “nand” gate [1].

Double-click on the “qqbar” [2] input because the Unknown to Hightransition on this input caused the output to change.

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2

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Gate Level Debugging - Buffer Gate - “o3”

Double-click on the “o3” [2] input to the “nand” gate because the High toLow transition on this input caused the output to change.

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Three input “nand” gate [1].

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Gate Level Debugging - Buffer Gate - “ck”

Double-click on the “ck” [2] input to the “nand” gate. The Low to Highchange on “ck” caused the “nand” gate to change.

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Three input “nand” gate [1].

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Gate Level Debugging

The original unknown to low transition has been traced back to signal “clock”in the testbench.

Buffer gate [1]

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Errors

Double click on the error message to automatically open the source file andsee the error.

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Errors

Error is caused by semicolon “;” missing from the module header.

SILOS III highlights the next line because the error could not be detecteduntil that line is interpreted.

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Errors

Error report for SILOS III.

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Analog Waveforms

Double-click to toggle between stepping function and piece-wise linear.

Piece-wise lineardisplay of analogsignal.

Stepping functiondisplay of analogsignal.

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SILOS Advanced Features

ß Supports Industry-Standard PLI 1.0 Interfaceß Currently implementing PLI 2.0

ß Silos supports the SDF language as defined by the IEEE1497 standard for SDF. Silos also supports a commonlyused extension used to specify the SDF file of delay values,the “$sdf_annotate” system task.ß $sdf_annotate(“file_name”, module_instance);

ß Interface for SystemC

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SILOS Future – Analog Mixed-Signal Solution

ß SILOS-AMS beta release in May 2004ß Integrated power of SmartSpice

ß Solver improvements for simulation speed

ß Common SILOS GUI on WINDOWS, SUN, and LINUX platforms

ß STA (Static Timing Analyzer) capability September 2004

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Analog and Mixed Signal Design Flow