SHIFT REGISTERSERIAL COMMUNICATION

System Digital

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POKOK BAHASAN Shift Registers

Definisi Model I/O : Serial, Pararel dan Kombinasi Arah pergeseran : Kiri, Kanan dan dua arah Applikasi/penggunaan Implementasi VHDL

MSI Shift Registers Komunikasi Serial

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D QInput

Clock

D Q D Q D Q

Q3 Q2 Q1 Q0

Enable

Output

SHIFT REGISTERSMemanfaatkan register untuk penyimpanan, manipulasi dan transfer (pemindahan) data

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DEFINISI Register adalah sebuah rangkaian digital dengan

dua (2) fungsi utama : Data storage dan Data Movement Shift register menyediakan fungsi data movement A shift register “shifts” its output once every clock

cycle Shift register adalah sekelompok flip flop yang

dipasang secara linier dengan masukan dan keluaran saling disambungkan satu dengan yang lain, sehingga data akan digeser dari satu alat ke alat yang lain ketika rangkaian tersebut diaktifkan

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PEMANFAATAN SHIFT REGISTER

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Komunikasi UART -> Universal

asynchronous receiver/transmitter

Konversi antara serial dan pararel

Penyimpanan sementara di processor scratch-pad memories

Operasi Aritmatika Perkalian, pembagian

Applikasi counter Johnson counter ring counter LSFR counters

time delay devices more …

SHIFT REGISTER CHARACTERISTICS Tipe

Serial-in, Serial-out Serial-in, Parallel-out Parallel-in, Serial-out Parallel-in, Parallel-out Universal

Arah Left shift Right shift Rotate (right or left) Bidirectional

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n-bit shift register

DATA MOVEMENT Bit – bit dalam shift register dapat digeser

sesuai gambar dibawah ini

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n-bit shift register

n-bit shift register

DATA MOVEMENT Blok diagram shift register dengan berbagai

variasi input/output

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n-bit shift register

n-bit shift register

n-bit shift register

SERIAL-IN SERIAL-OUT Bit data masuk satu persatu

dan keluar satu per satu Satu flip flop bertugas

untuk menyimpan satu data Pergerakan data dapat

geser kiri / kanan, pada umumnya satu register hanya bisa satu arah.

Masukan Asynchronous preset dan clear digunakan untuk set nilai awal

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SERIAL-IN SERIAL-OUT Rangkaian logika ini menunjukkan gambar secara umum

Serial in Serial Out Shift Register Menggunakan SR Flip Flop Dirangkai sehingga memiliki perilaku seperti flip-flop D Nilai masukan input akan digeser ke setiap flip-flop

berpadanan dengan clock pulse

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N-Bit Shift Register

0N 1

SHIFT REGISTERS Shift register paling sederhana hanya menggunakan flip-flops Keluaran dari flip-flop disambungkan dengan masukan D pada flip-flop

berikutnya di sebelah kanan Setiap pulsa clock akan menggeser nilai register satu bit satu posisi ke

sebelah kanan Serial input (SI) menentukan status masukan Flipflop paling kiri pada saat

terjadinya pergeseran, Serial output (SO) diambil dari keluaran flipflop paling kanan

Perhatikan animasi

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Q Q QQ

SERIAL-IN SERIAL-OUT Cara paling mudah untuk

mempelajari adalah lihat ilustrasi pada sebelah kanan

4 bit data word “1011” akan di geser pada 4 bit shift register

One shift per clock pulse Data di tunjukkan masuk

dari sisi sebelah kiri dan keluar dari sisi kanan

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1

2

3

4

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SERIAL-IN SERIAL-OUT Diagram di sebelah

kanan menunjukkan urutan 4 bit “1010” di load ke 4 bit SISO shift register

Setiap bit akan bergeser 1 posisi ke sebelah kanan pada setiap terjadi clock leading edge

dibutuhkan 4 pulsa clock untuk memasukkan seluruh bit ke register. 13

SERIAL-IN SERIAL-OUT Diagram disebelah

kanan menunjukkan urutan 4 bit “1010” unloaded dari 4 bit SISO shift register

Setiap bit akan bergerak satu bit ke kanan setiap signal clock

Dibutuhkan 4 clock untuk mengakhiri proses tersebut.

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SERIAL-IN SERIAL-OUT SISO di pergunakan

untuk komunikasi data : RS-232 modem transmission

and reception Ethernet links SONET etc.

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SERIAL-IN SERIAL-OUT IN VHDL Berikut ini adalah kode program implementasi VHDL untuk 8

bit shift register pada positif edge clock Serial in Serial Out

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library ieee;use ieee.std_logic_1164.all;

entity shift is port(C, SI : in std_logic; SO : out std_logic);end shift;

architecture archi of shift is signal tmp: std_logic_vector(7 downto 0); begin process (C) begin if (C'event and C='1') then for i in 0 to 6 loop tmp(i+1) = tmp(i); end loop; tmp(0) = SI; end if; end process; SO = tmp(7);end archi;

KONVERSI SERIAL-TO-PARALLEL Konversi serial ke pararel

dibutuhkan pada saat Misal setelah menerima

transmisi data secara serial Ilustrasi 4 bit serial in

pararel out Shift register di gambarkan di sebelah kanan

Output Q pada flipflop paling kanan juga dapat berfungsi sebagai serial out.

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n-bit shift register

SERIAL-TO-PARALLEL CONVERSION Digunakan serial in

pararel out shift register sepanjang N untuk mengubah N bit word dari serial ke pararel.

Di butuhkan pulsa N clock untuk load dan 1 clock pulse untuk unload

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SERIAL-TO-PARALLEL CONVERSION Dua buah shift

register di sebelah kanan digunakan konversi serial data ke pararel data

Register bagian bawah akan menyediakan untuk register bagian atas, ketika di geser oleh register bag bawah

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PARALLEL-TO-SERIAL CONVERSION Data di applikasikan ke bentuk

pararel, kemudian di umpan masukkan ke Pin A hingga D.

Kemudian dibaca secara sequential pada register 1 bit pada satu waktu dari PA ke PD setiap 1 siklus clock dalam bentuk serial

Satu pulsa clock untuk load Empat pulsa clock untuk unload

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n-bit shift register

PARALLEL-TO-SERIAL CONVERSION Logic circuit for a parallel-in, serial-out shift

register

21Mux-like

0

0

1

0

1

1

PARALLEL-IN PARALLEL-OUT Parallel-in Parallel-out Shift

Registers can serve as a temporary storage device or as a time delay device

The DATA is presented in a parallel format to the parallel input pins PA to PD and then shifted to the corresponding output pins QA to QD when the registers are clocked

One clock pulse to load One pulse to unload

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n-bit shift register

UNIVERSAL SHIFT REGISTER Universal shift register Can do any combination of

parallel and serial input/output operations

Requires additional inputs to specify desired function

Uses a Mux-like input gating

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L/SL/S

A

B

A

BF

1

01

0

UNIVERSAL SHIFT REGISTER Parallel-in, parallel-out shift register

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Mux-like

0

0

1

0

1

1

UNIVERSAL SHIFT REGISTER Parallel shift register (can serve as converting

parallel-in to serial-out shifter):

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MSI SHIFT REGISTERS 74LS164 is an 8-Bit

Serial-In Parallel-Out Shift Register

Typical Shift Frequency of 35 MHz

Asynchronous Master Reset

Gated Serial Data Input

Fully Synchronous Data Transfers

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MSI SHIFT REGISTERS 74LS164 8-Bit Serial-In Parallel-Out Shift

Register

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MSI SHIFT REGISTERS The 74LS164 is an edge-

triggered 8-bit shift register with serial data entry and an output from each of the eight stages.

Data is entered serially through one of two inputs (A or B); either of these inputs can be used

as an active HIGH Enable for data entry through the other input

an unused input must be tied HIGH, or both inputs connected together

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MSI SHIFT REGISTERS Each LOW-to-HIGH transition on

the Clock (CP) input shifts data one place to the right

This also enters into Q0 the logical AND of the two data inputs (A•B) that existed before the rising clock edge.

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MSI SHIFT REGISTERS

74LS164 logic diagram

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A LOW level on the Master Reset (MR) input overrides all other inputs and clears the register asynchronously, forcing all Q outputs LOW.

MSI SHIFT REGISTERS 74LS166 is an 8-Bit

Shift Register Parallel-in or serial-in

shift/load input establishes the parallel-in or serial-in mode

Serial-out Synchronous Load

Serial data flow is inhibited during parallel loading

Direct Overriding Clear

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MSI SHIFT REGISTERS 74LS166 is an 8-Bit Shift Register

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MSI SHIFT REGISTERS 74LS166 8-Bit Shift Register is a parallel-in or

serial-in, serial-out shift register

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MSI SHIFT REGISTERS 74LS166 is an 8-Bit Shift

Register

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MSI SHIFT REGISTERS 74LS166 is an 8-Bit Shift Register

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MSI SHIFT REGISTERS 74LS194 4-Bit

Bidirectional Universal Shift Register

may be used in serial-serial, shift left, shift right, serial-parallel, parallel-serial, and parallel-parallel

data register transfers

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MSI SHIFT REGISTERS 74LS194 4-Bit Bidirectional Universal Shift

Register

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MSI SHIFT REGISTERS 74LS194 control inputs S1 and S0

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MSI SHIFT REGISTERS 74LS194 4-Bit Bidirectional Universal Shift

Register

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01 11 10 00 01 11 10 0001 11 10 0001 11 10 00

MSI SHIFT REGISTERS 74LS194 4-Bit Bidirectional Universal Shift

Register

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“UNIVERSAL” SHIFT REGISTER74X194

Shift left Shift right Load Hold

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MSI SHIFT REGISTERS One stage of the 74x194

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VHDL DHIFT REGISTER Universal shift

register design

The 3-bit function select determines the operation of the register

Serial in and Parallel load available

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library IEEE;use IEEE.std_logic_1164.all;use IEEE.std_logic_unsigned.all;

entity Vshftreg is port (CLK, CLR, RIN, LIN: in STD_LOGIC; S: in STD_LOGIC_VECTOR (2 downto 0); -- function select D: in STD_LOGIC_VECTOR (7 downto 0); -- data in Q: out STD_LOGIC_VECTOR (7 downto 0) -- data out);end Vshftreg;

architecture Vshftreg_arch of Vshftreg issignal IQ: STD_LOGIC_VECTOR (7 downto 0);beginprocess (CLK, CLR, IQ) begin if (CLR='1') then IQ <= (others=>'0'); elsif (CLK'event and CLK='1') then case CONV_INTEGER(S) is when 0 => null; -- Hold when 1 => IQ <= D; -- Load when 2 => IQ <= RIN & IQ(7 downto 1); -- Shift right when 3 => IQ <= IQ(6 downto 0) & LIN; -- Shift left when 4 => IQ <= IQ(0) & IQ(7 downto 1); -- Shift circular right when 5 => IQ <= IQ(6 downto 0) & IQ(7); -- Shift circular left when 6 => IQ <= IQ(7) & IQ(7 downto 1); -- Shift arithmetic right when 7 => IQ <= IQ(6 downto 0) & '0'; -- Shift arithmetic left when others => null; end case; end if; Q <= IQ; end process;end Vshftreg_arch;

MSI SHIFT REGISTERS 74LS299 is an 8-bit

universal shift/storage register with 3-state outputs

Four modes of operation are possible: hold (store) shift left shift right load data

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MSI SHIFT REGISTERS 74LS299 universal shift/storage register

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MSI SHIFT REGISTERS 74LS299 universal shift/storage register

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S0S1

D Q

CPCD

MSI SHIFT REGISTERS 74LS299 logic circuit diagram:

The parallel load inputs and flip-flop outputs are multiplexed to reduce the total number of package pins.

Separate outputs are provided for flip-flops Q0 and Q7 to allow easy cascading.

A separate active LOW Master Reset is used to reset the register.

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SERIAL COMMUNICATIONSA practical application of Registers / Shift Registers48

SERIAL DATA SYSTEMS (E.G., TPC)

Read discussion and study circuits in text. 49

SERIAL DATA TRANSMISSION Parallel-to-serial conversion for serial

transmission

50serial transmission media

in: parallel data

out: parallel data

Destination moduleSource module

SERIAL DATA IN THE PHONE SYSTEM (E-1) 2.048 Mb/s links between phone switches

and subscribers partitioned into 32 64 Kb/s channels

Each channel gets a timeslot in a “frame” where it can send 8 bits every 125 sec. 8000 frames/sec

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TIMESLOT DETAILS

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count = 255

PARALLEL-TO-SERIAL CONVERSION

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256

LSBs are bit number

Assert shift-registerLOAD input during bit 7

Timeslot number canbe decoded and usedto select source ofparallel data

Serial data todestination

count = 255

SERIAL-TO-PARALLEL CONVERSION

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Synchronize destination’s counter to source’s

Shift in serial data

Detect that acomplete bytehas beenreceived

Holding registerfor completebyte

Note:loads0…0

DESTINATION TIMING

55Serial-in, parallel-outshift register outputs

Holding-register outputsGrab complete byte when available

SERIAL COMMUNICATION ON ONE WIRE Serial communication requires three signals:

CLOCK, SYNC, and DATA. Yet only one “wire” is used. How?

One solution: Manchester code.

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• Or use a phase-locked loop (analog circuit)to extract clock from the data:

STILL A COUPLE OF PROBLEMS Framing -- SYNC signal

Solution: Use a unique data pattern for SYNC PLL clock recovery -- what if too many zeroes

are transmitted? PLL can’t stay in sync. Solution: Use a code that guarantees a minimum

number of ones Phone system: Map 00000000 --> 00000010

(creating slight voice distortion) Gigabit Ethernet: Uses 8B10B code, solving

both problems Map each byte into 8 bits Use only a “good” subset of 210 code words Use another code word for synchronization

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ASSIGNMENTS Completed Part 2 Midterm problems due

Wednesday

Continue working on the MIPS project Description available on the course web page

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