Post on 02-Apr-2015
Shared Pages
Segmentation
CPU
Example
Sharing of Segments
Protection Associate valid/invalid bit with
each segment table entry to indicate if the referenced segment is part of the process address space or not
Read, write, and execute bits to define legal operations on a segment
Paged Segmentation Divide every segment in a
process into fixed size pagesNeed for a page table per
segmentCPU’s memory management
unit must support both segmentation and paging
Paged Segmentation
1
3
2
4
logical memory
5
physical memory
Paged Segmentation
1
3
2
4
logical memory
5
physical memory
1
2
0
3
0
1
2
3
.
.
.
10
126 127
31
12610
page table
Paged Segmentation Logical address is still <s,d>,
with s used to index the segment table
Each segment table entry consist of the tuple <segment-length, page-table-base>
The logical address is legal if d < segment-length
Paged Segmentation
Segment offset, d, is partitioned into two parts: p and d’, where p is used to index the page table associated with segment, s, and d’ is used as offset within a page
Paged Segmentation p indexes the page table to
retrieve frame, f, and physical address (f,d’) is formed
s d
p d’index
segment table
index page table
offset within the page p
Paged Segmentation
GE 345 processor Logical address = 34 bits Page size = 1 KB s is 18 bits and d is 16 bits Size of p and d’, largest
segment size, and max. number of segments per process?
Largest segment = 2d bytes= 216
bytes Maximum number of pages
per segment = 216 / 1 K = 64 |p| = log2 64 bits = 6 bits |d’| = log2 1 K = 10 bits Maximum number of segments
per process = 2s = 218
s d
p d’18 bits
6 bits 10 bits
Consider a process with its segment 15 having 5096 bytes. The process generates a logical address (15,3921).
Is it a legal address? How many pages does the
segment have? What page does the logical
address refer to?
Is it a legal address? Yes How many pages does the
segment have? ceiling[5096/1024]= 5
What page does the logical address refers to? ceiling[3921/1024]= 4(i.e., page number 3)
What are the value of d’ and the physical address if page number 3 (i.e., the fourth page) is in frame 12?
d’ = 3921 – 3*1K = 849
Physical address = 12*1K + 849 = 13137
15 3921
3 849s
p d’
d
page table for segment 15
0
1
2
3
4
12
15 3921
3 849
3921
12 12 849
13137
IBM OS/2, Microsoft Windows, and Linux
Paged segmentation with two-level paging
Logical address = 48 bits 16-bit selector and 32-bit
offset Page size = 4 KB
4-byte page table entry 32-entry TLB, covering
32*4K (128 KB) memory … TLB Reach
13-bit Segment #
16-bit Selector
g p
32-bit Offset
s 2-bit field for specifying the privilege level
1-bit field to specify GDT or
LDT
Real Mode
20-bit physical address is obtained by shifting left the Selector value by four bits and adding to it the 16-bit effective address