Post on 04-Sep-2019
SADC developments for PANDA
SADC Developments for PANDA
Pawel Marciniewski, PANDA Collab. Meeting, GSI, 12.12.2012
Initial SADC developments SADC Developments for PANDA
Pawel Marciniewski, PANDA Collab. Meeting, GSI, 12.12.2012
ADC Model AVM16 / AVX16
FQDC-240 FQDC-160 SQDC-80
No. of channels 16 16 16 16 Sampling rate 160/250 MHz 240 MHz 160 MHz 80 MHz
Input coupling DC /AC (5 μs) AC (5 μs) AC (5 μs) DC
Resolution 12-bit ±11-bit ±11-bit 12-bit
Baseline DAC controlled 0 V 0 V DAC controlled
Data retention 6.4 μs 6.4 μs 6.4 μs 12.8 μs
Input filter Passive CR Passive CR Passive CR Active filter
Interface VME-64x /VXS LVD-BUS(1) LVD-BUS(1) LVD-BUS(1)
Feature extraction: Signal search
within window Partial integrals
Arrival times Maxima, minima
Baseline and noise
SADC Evaluation board for PANDA EMC SADC Developments for PANDA
Pawel Marciniewski, PANDA Collab. Meeting, GSI, 12.12.2012
ADC Model PANDA_16 No. of channels 16 Sampling rate 125 MSPS Input coupling DC /AC (5 μs) Resolution (amplitude) 14-bit Baseline DAC controlled Input range ±1.0V or -2V..0V Noise 1.8 bit σ, 200μV Data retention 6.4 μs Input filter Passive CR-filter Interface Optical, SFP, LC-type, 2 Gbit/s Feature extraction:
Signal search within window Partial integrals Arrival times Maxima, minima Baseline and noise
SADC development for PANDA EMC SADC Developments for PANDA
Pawel Marciniewski, PANDA Collab. Meeting, GSI, 12.12.2012
ADC Model
ADC_32DR ADC_64V
ADC_64K
No. of channels 32 (64) 64 64 Sampling rate 80-125 MSPS Input coupling DC, positive, negative, diff Resolution (ampl)
14-bit dual range 14-bit
Input Connector uFL Samtec Baseline 0V Input range (dual)
±1.0V, ±100 mV
Noise ? Data retention ? Input filter Active-
filter/Amplifier CR-passive Active
filter/Amplifier Interface Optical, SFP, LC-type, 2 Gbit/s Feature extraction:
Signal search within window Partial integrals
Arrival times Maxima, minima
Baseline and noise
ADC for EMC-Endcap
- Ready prototype
Pawel Marciniewski, PANDA Collab. Meeting, GSI, 12.12.2012
4 dual-range channels (8 ADC 14-bit channels)
ADC for EMC-Endcap
- Layout details
Pawel Marciniewski, FEE Meeting, Rauischholzhausen 12.04.2012
ADC for EMC-Endcap
- Ready prototype
Pawel Marciniewski, PANDA Collab. Meeting, GSI, 12.12.2012
Pawel Marciniewski, PANDA Collab. Meeting, GSI, 12.12.2012
32 in
puts
Po
sitiv
e, N
egat
ive
or
Diffe
rent
ial
+/- 1
V FS
+/
- 60
mV
FS
16-ch dual range block
Shaper/Amplifier
G=1 G=16
8-ch ADC
14-bit 80 Ms/s
FPGA
Virtex-6 Optical Interface
16-ch dual range block
Shaper/Amplifier
G=1 G=16
8-ch ADC
14-bit 80 Ms/s
FPGA
Virtex-6 Optical Interface
Clocking, Configuration
Design Idea
ADC for EMC-Endcap
– Design Idea
Fully differential, BW > 100 MHz, SR > 100 V/us, Pd < 50 mW/ch, Active filter
EOB > 14-bit, Sampling rate ~80Ms/s, Pd < 100 mW/ch, 32 (64) ch. per board
Radiation immune (RT-Flash or Tripple Modular Redundancy) or partially reconfigurable with watchdog, 32/64 channels per board
Radiation immune, SODA-compliant, dual
High efficiency (DC/DC), ferrite-less (Air-Core)
Common, dual accessable
Pawel Marciniewski, FEE Meeting, Rauischholzhausen 12.04.2012
ADC for EMC-Endcap
– Design idea
CH0_L CH0_H
CH15_L CH15_H . . . . . 16 (32) .
channels . . . .
CH1_L CH1_H CH2_L CH2_H CH3_L CH3_H
8-ch ADC
8-ch ADC
8-ch ADC
8-ch ADC
8-ch ADC
8-ch ADC
8-ch ADC
8-ch ADC
CH31_L CH31_H
CH16_L CH16_H
. .
. .
. .
. 16 (32) . channels . . . . . .
FPGA 2
ARBITER
PLL M
UX
SFP Optical Interface
MU
X
FPGA 1
SFP Optical Interface
CFG PROM
CFG PROM
PLL
GTX
LOG JTAG PROG
GTX SER
PLL
GTX
LOG JTAG PROG
SER
GTX
DE-SERIALIZER
FEATURE EXTR.
FEATURE EXTR.
DE-SERIALIZER
8 X LTM9009-14
14-Bit, 80-Msps Low Power Octal ADCs
4 X XCF32PFS48C
64 X LTC6403
2 X XC6VLX130T-
3FFG484C
LMK03806 14-output
PLL
2 X Finisar
2.1 Gbit/s
KVI – shaper / active filter
ADC for EMC-Endcap
– identyfying componenets
(by Franz Schreuder)
Pawel Marciniewski, PANDA Collab. Meeting, GSI, 12.12.2012
ADC for EMC-Endcap
- 60 mV pulse - bipolar
G = 16
G = 1
Pawel Marciniewski, PANDA Collab. Meeting, GSI, 12.12.2012
ADC for EMC-Endcap
- 1V pulse - bipolar
G = 16
G = 1
Pawel Marciniewski, PANDA Collab. Meeting, GSI, 12.12.2012
ADC for EMC-Endcap
- Cross-talk
Pawel Marciniewski, PANDA Collab. Meeting, GSI, 12.12.2012
Adjacent channel, G = 16
1V input pulse, G = 1
Adjacent channel, G = 16
ADC for EMC-Endcap
- Noise tracks
G = 16
G = 1
Pawel Marciniewski, PANDA Collab. Meeting, GSI, 12.12.2012
ADC for EMC-Endcap
- Noise track
G = 16
G = 1
Pawel Marciniewski, PANDA Collab. Meeting, GSI, 12.12.2012
ADC for EMC-Endcap
Noise – amplitude spectrum
0
20
40
60
80
100
120
140
160
180
8170
8172
8174
8176
8178
8180
8182
8184
8186
8188
8190
8192
8194
8196
8198
8200
8202
8204
8206
8208
8210
8212
8214
8216
8218
8220
8222
8224
8226
8228
8230
8232
8234
8236
8238
8240
8242
8244
8246
8248
8250
8252
8254
Occ
uren
ce
ADC value
ADC noise
Series1
Series2
6 bin 21 bin
G = 16
G = 1
Pawel Marciniewski, PANDA Collab. Meeting, GSI, 12.12.2012
Pawel Marciniewski, PANDA Collab. Meeting, Bochum, 10.09.2013
9 40
9 70
Gain = 1
Gain = 1
Gain = 16
Gain = 16
Resolution improvment = 2 bit
Resolution improvment = 1 bit
ADC for EMC-Endcap
Improving resolution using dual-range by a 16x follower
Courtesy Malte Albrecht
ADC for EMC-Endcap
- Encapsulation and Cooling
Courtesy KVI
Pawel Marciniewski, PANDA Collab. Meeting, Bochum, 10.09.2013
ADC for EMC-Endcap
- Encapsulation and Cooling
Courtesy KVI
Pawel Marciniewski, PANDA Collab. Meeting, Bochum, 10.09.2013
ADC for EMC-Endcap
- Encapsulation and Cooling
Courtesy KVI
Pawel Marciniewski, PANDA Collab. Meeting, Bochum, 10.09.2013
ADC for EMC-Endcap
- Preparation for the PbWO4/VPTT tests at Max Lab
Pawel Marciniewski, PANDA Collab. Meeting, Bochum, 10.09.2013
PbWO4 + VPTT
ADC32DR
ATLB (VME Optical Data Concentrator
VME
ADC for EMC-Endcap
- Development - Time plan V1.1 – June 2013 * Design clean-up * Block connectors – Samtec ERF8-049-XX-X-D-RA * 64 – channels with individual gain, no filter
V1.2 – August 2013 * Block connectors * Low power op-amp ADA4940-2 * 32-ch. with gain G = 0.5, filtered 32-ch. with gain G = 5.0, filtered
V2.0 – October 2013 * Kintex-7
Pawel Marciniewski, PANDA Collab. Meeting, Bochum, 10.09.2013
ADC for EMC-Endcap
Thank You !
Special thanks to Frans Schreuder, Peter Schakel
Input Connector
Input Amp Config Full SODA
FPGA Comment Status
ADC32DR (V1.0)
64 x uFL 32 ch. Dual Range Filtered, gain x1 followed by 16x LTC6403
No Virtex-6 First prototype Manufactured and tested Operational
ADC64V (V1.1)
Samtec 64 ch. independent, No filter, Gain 1.0 LTC6403
Yes Virtex-6 Bug fixed ADC32DR with input modification
Design ready.
ADC64VA (V1.2)
Samtec 64 ch. Independent 32 Filtered, Gain 0.5 32 Filtered, Gain 5.0 ADA4940-2
Yes Virtex-6 Bug fixed ADC32DR with input modification
Design ready. Purchase interest expressed by KVI
ADC64K (V2.0)
Samtec 64 ch. Independent 32 Filtered, Gain 0.5 32 Filtered, Gain 5.0 ADA4940-2
Yes Kintex-7 Bug fixed ADC32DR with input modification Major FPGA change
Design in progress. Expected ready by 30.09
Pawel Marciniewski, PANDA Collab. Meeting, Bochum, 10.09.2013
ADC for EMC-Endcap
- Connections
0,80 mm Edge Rate™ High Speed Twinax Cable Assembly
ERDP 0,80 mm Edge Rate™
High Speed Coax Cable Assembly
ERCD
Direct cable connection solution
Board Connector Backplane solution
ERF8-049-XX-X-D-RA
Pawel Marciniewski, PANDA Collab. Meeting, Bochum, 10.09.2013
ADC for EMC-Endcap
- Power requirements
Analog (LDO filtered) V1.0 V2.0 +2.2V (1.8V) – 3.2A (ADC) 7.0 W 7.0W +2.9V (2.5V) – 1A (AMP) 2.9 W 0.4W
Digital +1.0V – 6A (FPGA) 6.0W 4.0W +1.2V – 1.2A (FPGA) 1.5W 1.0W +1.8V - 0.8A (ADC) 1.5W 1.5W +2.5V – 3.0A (FPGA) 7.5W 4.5W +3.3V – 0.4A (PLL), 0.5A(SFP) 1.3W 1.3W _____________________________________________
TOTAL NETTO POWER 28 W 20W
Pawel Marciniewski, PANDA Collab. Meeting, Bochum, 10.09.2013
ADC for EMC-Endcap
Thank You !
Special thanks to Frans Schreuder, Peter Schakel
Pawel Marciniewski, PANDA Collab. Meeting, GSI, 12.12.2012