PM432 Stratix II GX FPGA PMC Module with four HSSDC2 ...PM432 SPECIFICATIONS PROCESSING FPGA •...

Stratix II GX FPGA PMC Module with four HSSDC2 connectors and 90Mb ZBT RAM

PM432 SPECIFICATIONS

PROCESSING FPGA

• EP2SGX90 ALTERA• EP2SGX90 ALTERA® Stratix® II GX FPGA• 90,960 Logic Elements, 192 18x18 multipliers and 4.3 Mb RAM• On-board non-volatile storage of configuration data (2 banks)• Automatic configuration of FPGAs after power-up

MEMORY

• Standard: Five 512Kx36 (18Mb) ZBT® memories• Optional: Five 1Mx36 (36Mb) ZBT® memories

PCI INTERFACE

• 32/64-bit 33/66MHz 3.3V PCI bus in ALTERA® Stratix® FPGA• Peak PCI data rate (533MBytes/s) supported• Up to 420 MBytes/s sustained DMA data rate

PMC USER I/O

• 64 User I/Os with LVTTL signal level (3.3V)

FRONT PANEL I/O

• Four HSSDC2 connectors• Up to 3.125 Gbps full-duplex bandwidth per connector• Serial RapidIO™, Fibre Channel, Gigabit Ethernet and SerialLite II protocols are supported via the use of IP cores

SOFTWARE SUPPORT

• Software utility to program Processing FPGA configuration data• Device driver for Windows 2000/XP and Linux• Sample application and source code• Matlab API via Mex DLL file available• Application / driver development services available on request

FIRMWARE SUPPORT

• Shipped with SerialLite II reference design• FFT reference design available• Firmware development services available on request

REV 3 Tel: +27 12 678 9740 | E-mail: sales@parsec.co.zawww.parsec.co.za

The PM432 is a single PMC module that leverages on ALTERA® Stratix® II GX FPGA technology to provide a high-speed,high-bandwidth processing platform, ideally suited for Software Defined Radio (SDR), WiMAX, Radar, Video, as well as other computation and bandwidth inten-sive applications.

An EP2SGX90 Stratix II GX FPGA imple-ments a processing node with an unprece-dented combination of serial I/O band-width, logic and memory resources and DSP performance. Four Stratix II GX trans-ceiver channels each provide up to 3.125 Gbps fullduplex bandwidth via HSSDC2 front panel connectors.

Five 512Kx36 (18Mb) ZBT® memories individually connect to the Processing FPGA, yielding 2.66 GBytes/sec of memory bandwidth. An ALTERA EP1S10 Stratix FPGA implements a PCI-to-Local-Bus bridge with a 64-bit 66MHz PCI bus inter-face, supporting maximum PCI bandwidth to and from the Processing FPGA via sepa-rate 64-bit Target and DMA busses. From Pn4, 64 PMC user I/Os connect to the Processing FPGA.

The EP2SGX90 configuration data is storedin on-board flash memory that is program-mable via the PCI bus.

Stratix® is a registered trademarkof Altera Corporation

REV 3 Tel: +27 12 678 9740 | E-mail: sales@parsec.co.zawww.parsec.co.za

TYPICAL APPLICATIONS

• Software Defined Radio (SDR)• Radar processing (Doppler fi lter, Pulse compression, CFAR)• Image processing (DCT, 1D/2D convolution, etc.)• Vector processing• Real-time DSP functions (DDC, FFT, FIR, NCO, etc.)

ORDERING INFORMATION

PM432 - Y - ZY: ZBT Memory Size (18Mb or 36Mb)Z: HSSDC2 polarity (IN or FC)(IN=Infi niband, FC=Fibre Channel)

(Standard order code: PM432-18-FC)

APPLICATION EXAMPLES

• High-bandwidth sampling • Radar and Sonar• Wideband receiver sub-systems • IF Sampling• Multi-channel digital receivers • Software-defined radio

Stratix II GX FPGA PMC Module with four HSSDC2 connectors and 90Mb ZBT RAM

PM432 Stratix II GX FPGA PMC Module with four HSSDC2 ...PM432 SPECIFICATIONS PROCESSING FPGA •...

Documents

Transcript of PM432 Stratix II GX FPGA PMC Module with four HSSDC2 ...PM432 SPECIFICATIONS PROCESSING FPGA •...

Stratix II GX Device Handbook - Farnell element14 · Stratix II GX Architecture chapter in volume 1 of the Stratix II GX Device Handbook Document Revision History Table 1–4 shows

Stratix 10 GX/SX Device Overview - intel.com · 1. Intel® Stratix® 10 GX/SX Device Overview Intel’s 14-nm Intel ® Stratix 10 GX FPGAs and SX SoCs deliver 2X the core performance

Transitioning APEX Designs to Stratix & Stratix GX Devices, Stratix … · 2021. 1. 16. · Transitioning APEX Designs to Stratix & Stratix GX Devices cascade primitives in APEX II

Using Pre-Emphasis and Equalization with Stratix GX

Intel FPGA SDK for OpenCL · — Intel Arria 10 FPGA Development Kit Reference Platform Scripts and its content was merged with Contents of the Intel Stratix 10 GX FPGA Development

Remote System Upgrades with Stratix II & Stratix II GX Devices - Altera

Stratix 10 GX/SX器件概述 - Intel · 2020. 12. 24. · Intel Stratix 10 器件包含在FPGA (GX)和SoC (SX)系列中。 • Intel Stratix 10 GX 器件实现高达1 GHz 内核架构性能，在单片式架构上包含550

Configuring Stratix & Stratix GX Devices - Altera€“2 Altera Corporation ... CCIO of the I/O bank they reside in or ground. V CCSEL Pins ... Configuring Stratix & Stratix GX Devices

Intel® Stratix® 10 GX FPGA Development Kit User Guide · 1. Overview The Stratix® 10 GX FPGA development board provides a hardware platform for evaluating the performance and features

Configuration Handbook, Volume 1, Chapter 3: Configuring Stratix & Stratix GX Devices · 2021. 2. 17. · This chapter discusses how to configure one or more Stratix or Stratix GX

Stratix IV E FPGA Development Board Reference Manual€¦ · 101 Innovation Drive San Jose, CA 95134 MNL-01048-1.2 Reference Manual Stratix IV E FPGA Development Board Subscribe Stratix

256 10 GX Transceiver Signal Integrity Development Kit ... · Intel® Stratix® 10 GX Transceiver Signal Integrity Development Kit ... • Generate and check pseudo-random ... Stratix

Selectable I/O Standards in Stratix II and Stratix II GX Devices · 2018-06-16 · Selectable I/O Standards in Stratix II and Stratix II GX ... other 2.5-V devices. This standard

Stratix IV GX FPGA Development Board Reference … · August 2012 Altera Corporation Stratix IV GX FPGA Development Board Reference Manual 1. Overview This document describes the

AN 208: Configuring Stratix & Stratix GX Devices

Altera Stratix II FPGA Architecturecwcserv.ucsd.edu/~billlin/classes/ECE111/lectures/Lecture13B.pdfAltera Stratix II FPGA Architecture . 2 ... • Also contains Quad ARM Cortex-A53

Stratix V GX FPGA Development Board Reference Manual (PDF)

JESD204B Intel FPGA IP User Guide - Altera. TX Data Link Layer ... Cyclone V, Stratix V, ... • JESD204B Intel Cyclone 10 GX FPGA IP Design Example User Guide • Intel FPGA Software

Cyclone IV GX FPGA Development Kit User Guide · Cyclone IV GX FPGA Development Kit Subscribe Cyclone IV GX FPGA Development Kit User Guide. ... Altera, The Programmable Solutions

Stratix IV GX FPGA Development Board Reference Manualridl.cfd.rit.edu/products/manuals/Altera/Stratix IV GX... · 2009-05-22 · development board. Figure 2–1 illustrates major