Post on 02-Jan-2016
description
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Multi-Bend Bus-Driven Floorplanning
Jill H.Y.Law & Evangeline F.Y.Young
The Chinese University of Hong Kong
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Outline
Introduction Background Sequence Pair
Methodology Shape Validation Bus Ordering Floorplan Realization
Experimental Results Conclusion
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Introduction
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Background
Why is bus-driven floorplanning important? Previous work:
Hua Xiang, Xiaoping Tang and Martin D.F. Wong “Bus-Driven Floorplanning” ICCAD 2003
0-bend is not enough for buses going through many blocks
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Problem Formulation
A set of n blocks B = {b0, b1, …, bn-1}
A set of m buses U = {u0, u1, …, um-1}, where each bus is associated with a width ti
Decide the position of blocks, such that Buses go through their blocks Chip area minimized Bus area minimized
Buses can have at most 2-bends
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Problem Formulation
What is meant by “going through” ? Assume block height > bus width
A
B
C
bus i >= ti
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Problem Formulation
AB
E
C
D A
F
J
H
E
DB
C G
I
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Sequence Pair (SP)
A pair of sequences of n elements (…a…b…, …a…b…), a is on the left of b (…a…b…, …b…a…), a is on top of b
Example: (acbde, daceb)
d
a c
e
b
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Methodology
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Overview
While Temp > threshold Apply a move to obtain a new SP Evaluate the floorplan
Shape Validation Bus Ordering Floorplan Realization
Accept or reject according to Cost and Temp
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Steps
Assumption 2 layers for bus routing
Evaluation Shape Validation
0-bend 1-bend 2-bend
Bus Ordering Floorplan Realization
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Shape Validation
Check the bus one by one From the relative position of the blocks, check if a
bus of at most 2 bends can go through all blocks
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Shape Validation – 0 bend
Step 1: Extract the related blocks from the sequence pair Example: For a bus ABE Given a SP (ABCDE, ABCED) (ABE, ABE)
Step 2: Check relative position between blocks Example: For a bus ABC Horizontal bus: (ABCDE, ADEBC) (ABC, ABC) Vertical bus: (CDBEA , ABCDE) (CBA, ABC)
A
BC
A
B
C
(ABCDE, ADEBC) (CDBEA, ABCDE)
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Shape Validation – 1 bend
L-shape bus 1 horizontal component 1 vertical component
How to recognize them? Step 1: Extract the related blocks (X, Y) Step 2: Find the Longest Common
Subsequence (LCS) of (X, Y) Horizontal component
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Shape Validation – 1 bend
Step 3: Check if the remaining blocks in reverse order Example: (ABCDEF, ABCFED) LCSABCD, remaining blocks (DEF, FED)
Step 4: Check if T-shape T-shape also contains one horizontal component and
one vertical component T-shape is kept for later 2-bend checking
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Shape Validation – 1 bend
When will a T-shape be formed?
A
B C
A
B
C
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Shape Validation – 1 bend
Example: (ABCDE, ADCBE) Horizontal Component: ABE Vertical Component: CD
AB
EC
D
AB
E
C
D
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Shape Validation – 2 bend
C-Shapes, Z-Shapes, mirrored Z-Shapes … HVH or VHV Assume HVH (VHV is similar)
How to recognize them? Step 1: Extract the related blocks (X, Y) Step 2: Find the LCS of (X, YR) vertical
Example: (ABCDE, ADCBE) Find the LCS of (ABCDE, EBCDA): BCD
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Shape Validation – 2 bend
Step 3: Put the remaining blocks in different relationships with the vertical component
B
C
D
E
A
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Shape Validation – 2 bend
8 possible relationships
Step 4: Put the blocks into 2 horizontal components
B
C
D
Verticalcomponent
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Shape Validation – 2 bend
Example: (GHABCEFD, EFDCBGHA) (GHABCEFD, AHGBCDFE) vertical component Upper = {A, H, G}, Lower = {D, E, F} A C-shape can be formed
EF D
C
B
GH
AA, H, G
D, E, F
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Shape Validation – 2 bend
Example: (AEBCDF, EDCBFA) (AEBCDF, AFBCDE) vertical component Upper = {A}, Lower = {D}, LowerLeft = {E}, LowerRight =
{F} No valid 2-bend shape can be formed
D
C
B
A
F
E
A
D
E F
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Shape Validation
Extract the related blocks Check if 0-bend Check if 1-bend Assume HVH
Check if 2-bend Assume VHV
Check if 2-bend Mark it invalid if all “no”
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Steps
Evaluation Shape Validation Bus Ordering Floorplan Realization
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Determine Bus Ordering
AB C
DE
The two bus componentshave ordering constraint
A
B C
DE
FG
I
H J
A
BC
D
The two bus componentshave ordering constraintwhich contradict with one
another
A
B
C
D
The two bus componentshave ordering constraintwhich contradict with one
another
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Bus Ordering
Step 1: Split all the buses into 0-bend bus components
Step 2: Build vertical graph and horizontal graph by looking at each pair of bus components Use a node to represent each bus component If bus component a has to be on top of bus component b,
add an edge from node a to node b If there is cycle, at least one bus component in the cycle
has to be removed Horizontal graph can be built in a similar fashion
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Bus Ordering
Step 3: If there are cycles, remove nodes (bus components) to make the graph acyclic Aim at removing the least number of nodes NP-complete Maximum degree heuristic
Step 4: Remove the corresponding bus components in the other graph as well
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Steps
Evaluation Shape Validation Bus Ordering Floorplan Realization
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Floorplan Realization
Realization = obtaining the positions of the blocks and buses
This step is the same as that in Xiang’s work
X
B
C
AX
B
C
A
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Simulated Annealing
Simulated Annealing Framework Moves:
Swap Rotation
Cost Function Cost = A + ‧ B + ‧ I‧ A: chip area, B: total bus area, I: number of invalid bus
Can consider other aspects by adding more terms in the cost function Total wire length Routing congestion
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Summary
While Temp > threshold Apply a move to obtain a new floorplan Evaluate the floorplan
Shape Validation Bus Ordering Floorplan Realization
Accept or reject according to Cost and Temp
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Experimental Results
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Platform
Language Implemented using C ++
Machine Intel Xeon (2.2 GHz) with 1 G memory
MCNC benchmarks
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Experimental Results
The data set used in Xiang’s work* calculated by [(y1 – y0) / y0]*100%
Xiang’s Work Our Work Comparison*
Time (s) Dead space Time (s) Dead space Time Dead space
apte 15 0.72% 30 0.48% +100.00% -33.33%
xerox 15 0.95% 35 0.42% +133.33% -55.79%
hp 33 0.62% 51 0.29% +54.55% -53.23%
ami33-1 11 0.94% 93 1.00% +745.55% +6.38%
ami33-2 92 1.27% 144 1.19% +56.62% -6.30%
ami49-1 16 0.85% 71 0.56% +343.75% -34.12%
ami49-2 302 0.84% 713 0.58% +136.09% -30.95%
ami49-3 285 1.09% 865 0.60% +203.51% -44.95%
Average: +221.65% -31.54%
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Experimental Results In this data set, each bus has to go through 10 – 15 blocks
* calculated by [(y1 – y0) / y0]*100% Xiang’s Work Our Work Comparison*
Time (s) Dead space Time (s) Dead space Time Dead space
ami33-3 86 1.81% 32 1.01% -62.79% -44.20%
ami33-4 >1000 NA 92 1.90% NA NA
ami33-5 > 1000 NA 95 3.80% NA NA
ami49-4 73 19.34% 88 0.63% +20.55% -96.74%
ami49-5 > 1000 NA 261 1.17% NA NA
ami49-6 > 1000 NA 140 2.19% NA NA
Average: 118 1.78%
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Experimental Results
ami49 – 2
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Experimental Results
ami49 – 3
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Experimental Results
ami49 – 6
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Conclusion
Solve the bus-driven floorplanning problem for 0-bend, 1-bend, 2-bend buses
The presence of 1-bend and 2-bend buses is important, especially when the number of blocks that a bus goes through is large