Post on 30-Dec-2015
description
Workshop - November 2011 - Toulouse
Ronan LUCAS - Magillem Design Services
07/04/2011
AgendaRequirement Traceability Flow
Capture, mappingRefinement, implementation, generationCheckVerification
Documentation and Code GenerationEnvironmentJET Technology
Content ManagementConsistency and coherency
Traceability Management Main Process Phases:
• Capturing the requirements• Analysing the requirements• Validating the requirements• Analysing deviations• Allocating the requirements• Verifying the requirements.
All requirements must be:• identified by a single identification label,• allocated,• traced,• evaluated as regards maturity, priority, impact on the architecture,• validated,• verified according to an established procedure with defined means and
must have an established satisfaction criterion (reaching an expected result).
Specification
documentDesign
conception document
Verification plan
Result report
code
Specification Design Verification procedure
Verification Result Data
Level n(board)
Level n-1(fpga) Specificati
on document
Design conception document
Verification plan
Result report
Requirement traceability process
Phase 1: capture and mapping
Build the platform from the specification with Magillem Platform Assembly (MPA)
Load the requirements from the specification in a traceability tool
Export the requirements tree
Import the requirements tree in Magillem
Map the requirements on the platform described in IP-XACT Standard (drag&drop)
import
CSV
Specification implementation
Requirements
mapping
T1.2.3
Phase 2: Refinement, implementation and generation
Refinement of the Requirements done during the conception
update the mapping on the platform described in IP-XACT
generate Preliminary Conception document with Magillem Generators
Tags intrusive implementation in the code with Magillem tools (SystemC, systemVerilog, vhdl)
Preliminary Conception Document skeleton
wrapper
Netlist T1.2.1
T2.2.1
T1.3
Document and code generation by MAGILLEM
Refi
nem
en
t
Phase 3: Check
7
Cross checking the requirements in the spec, Preliminary Conception Document and source codes with a dedicated tool
IP-XACT requirement description manage only one single source along the flow, during conception and implementation steps
skeleton
wrapper
NetlistPreliminary Conception Document
100%
Phase4: Verification Each requirement must be
verified Map verification requirements
on the IP-XACT verification platform where the DUT is instantiated
generate Preliminary verification document, makefile
run verification generate a results requirement
document with the link between verification requirement and results
check requirement coverage with a dedicated tool and generate progress verification report
Verification requirement
s
generation
verification
IP-XACT Verificatio
n platform
Preliminary Verification document
makefile
Results
Results
Results
Generation&
link
Results requirement
s
mapping
Coverage
Requirements in IP-XACT schema
Vendors Extensions• Bus interfaces• Registers• Ports• ….
<spirit:vendorExtensions> <spirit:cover>E_HRD_TS_IP_0200</spirit:cover> <spirit:cover>E_HRD_TS_IP_0250</spirit:cover></spirit:vendorExtensions>
Requirements in IP-XACT schema
Vendors Extensions• Bus interfaces• Registers• Ports• ….
Files
Bit Fields
<spirit:vendorExtensions> <spirit:cover>E_HRD_TS_IP_0200</spirit:cover> <spirit:cover>E_HRD_TS_IP_0250</spirit:cover></spirit:vendorExtensions>
AgendaRequirement Traceability Flow
Capture, mappingRefinement, implementation, generationCheckVerification
Documentation and Code GenerationEnvironmentJET Technology
Content ManagementConsistency and coherency
Documentation and code generation
Documentation and Hardware Abstraction Layer facilitate HW and SW integration
Documentation html, pdf, RTF
IP-XACT description
Makefile
Hardware Abstraction Layer
Header SystemC, RTL
Needs: Write / adapt specific generators Easy output format management High level API
From IP-XACT description through TGI
Features: Automatic Completion JET Editor 2 execution modes: normal or debug 2 use modes: user or expert
Dedicated Environment for Template
template
Magillem
Generated file
IP-XACT
TGI
API for template JET
Template JET (Java Emitter Template)
IP-XACT description
TGI API
JET template
<%if (!registerCont.isEmpty()) { registerCont.fillArrayBitFieldC(little); arrayBitFieldC = registerCont.getArrayBitFieldC(); String volatil = new String(); if (registerCont.isVolatil()) { volatil = " volatile";} else { volatil="";}%>
typedef <%=volatil%> struct { uint<%=type%>_t <%=UsefulPublisher.publishString(1,bFName,false)%> : <%=bitFieldCont.getWidth()%>;
Java Model based close to IP-XACT
Java methods to handle easily datas
stored in IP-XACT
JAVA Doc associated
Hardware Abstraction Layer (C Language) - Astrium• Layer1 : Register and bitfield description usbhs_HAL1.h• Layer2 : read and write access method• Layer3 : method for validation• System Map
Header (ESL, RTL) - Airbus• Hardware Interface of component (Entity VHDL, Module Verilog,
Interface SystemC)
Makefile – Airbus
Code generation
AgendaRequirement Traceability Flow
Capture, mappingRefinement, implementation, generationCheckVerification
Documentation and Code GenerationEnvironmentJET Technology
Content ManagementConsistency and coherency
Consistence and coherence
Shared information between flows
Impact of modificationsRisk analysisUpdate generated files or
documentOptimize non regression tests
Documentation
Update
IP-XACT : shared information
SW Registers Abstraction Layer by MRV
IP-XACT database
Selection of the scenario for non regression test
SW Interface specification by DITA Generation Document
An up-to-date project An optimum management
about impact of modification
ModifIP-XACT
DITAGENERATIO
NDOC
Magillem Register View
typedef struct { uint32_t dataReady : 1; uint32_t transmitShift : 1; uint32_t transmitHold : 1; uint32_t brkReceived : 1; uint32_t overrun : 1; uint32_t parityError : 1; uint32_t framingError : 1; uint32_t reserved : 25; } tb_uartBlock_status;
typedef struct { uint32_t dataReady : 1; uint32_t transmitShift : 1; uint32_t transmitHold : 1; uint32_t brkReceived : 1; uint32_t overrun : 1; uint32_t parityError : 1; uint32_t framingError : 1; uint32_t reserved : 25; } tb_uartBlock_status;
typedef struct { uint32_t dataReady : 1; uint32_t transmitShift : 1; uint32_t transmitHold : 1; uint32_t brkReceived : 1; uint32_t overrun : 1; uint32_t parityError : 1; uint32_t framingError : 1; uint32_t reserved : 25; } tb_uartBlock_status;
scenario 1
scenario 1
scenario 1
scenario 1
scenario 1
Questions
?