1

A 1.1V 150GHz Amplifier with 8dB Gain and +6dBm Saturated Output Power in Standard Digital 65nm CMOS

Using Dummy-Prefilled Microstrip Lines

M. Seo1, B. Jagannathan2, C. Carta1, J. Pekarik3, L. Chen1, C. P. Yue1 and M. Rodwell1

1Dept. of Electrical and Computer Engineering University of California, Santa Barbara2IBM, Burlington, VT3IBM, Crolles, France

2

Outline

• Introduction• “Dummy-Prefilled” Microstrip Line

– Structure and Modeling• Design and Simulation• Measurement Results

3

Beyond 100GHz: What Applications?

0 50 100 150 200 250 300 3500

5

10

15

20

Frequency (GHz))

Atm

. Atte

nuat

ion

(dB

)A

ttenu

atio

n (d

B/k

m)

Frequency (GHz)

O2

O2

H2OH2O

94GHz 140GHz 220GHz

• Communication– Outdoor, indoor

• Imaging (Passive, active)– Security– All-weather radar– Medical

4

Beyond 100GHz: Why CMOS?

• Low-cost• Low-power• Large-scale Integration → Parallelism

– Large monolithic phased array, imager.• RF/mm-wave, IF/analog, DSP on a same die.

– System-on-chip– Digital calibration of RF/analog circuit imperfections,

process variations.– Reconfigurability and adaptability

5

What Challenges in 150GHz CMOS Amp?

• Low available FET gain, Low Supply Voltage– Careful FET layout & sizing– Multi-stage Common-Source

• Modeling uncertainties– Simple matching topology with microstrip (MS) lines

• Automatic “dummies” alter MS-line characteristics– Propose “Dummy-prefilled” MS-line

• Characterization– Full 2-port on-wafer TRL calibration

6

FET Layout

0

1

2

3

4

5

6

7

8

100 109 200 109

SFG_PFG_MSG_H21_U

MS

G (P

GF)

Frequency (GHz)Frequency (GHz)100 200 300

Max

imum

Sta

ble

Gai

n (d

B)

Parallel gate feed (PGF)

Series gate feed (SGF) S D

G

G

DSG

• Finger design: Reduce Rg,ext and Cgd (WF=1um)• Wiring multiple fingers: Parallel versus Series

10x1um/65n

7

“Microstrip Line” in Nanoscale CMOS

• “Automatic” dummies/holes to meet metal density rules.• Line capacitance increases

– ΔC depends on E-field orientation → Anisotropic• Direct E/M simulation nearly impossible

Ground plane

Signal

Line

8

Possible Shapes of Dummy Pre-fillers

S

ignal Line

S

ignal Linedummies

• “LINE” dummies• Parallel to current flow

• “LINE” dummies• Perpendicular to current flow

• “SQUARE” dummies• No preferred direction of

current flow S

ignal Line

9

Reducing Complexity in E/M Sim

Signal Signal

Dummy-free uniform dielectricwith adjusted diel. constant

E/M simulation feasibleby significantly reducing

# of dummies

W S

E-fieldlines

Dummy Pre-fillers

ε ε’

Successive dummy-layer substitutionby parallel-plate capacitor simulation

10

-40-20

02040

0 10 20 30 40 50 60

% c

hang

e

-40-20

02040

0 10 20 30 40 50 60

Fill Ratio (%)

% c

hang

eLine Inductance/Capacitance vs Fill Ratio

25% FillW:S = 1:1

56% FillW:S = 3:1

L per unit length(317nH/m w/o fillers)

C per unit length(103pF/m w/o fillers)

+17%+32%

11

Ground Plane Construction

• Solid GND plane not allowed• Put holes, and strap M1 & M2

Where current flow is uniform(e.g. under MS-line)

Where current flow is not uniform(e.g. under bends, T-junction,

radial stubs)

M1M2via

+

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THRU-REFL-LINE (TRL) Calibration

(1) THRU

(2) REFL

(3) LINE

AmplifierTest

Half THRU

450um Referenceplane

• REFL & LINE need not be accurately known• Measurements normalized to the line impedance

ΔL(ΔL= 90 deg @center freq)

(Open, short, etc)

13

3-Stage 150GHz Amplifier: Schematic

Half THRU Half THRUAmplifier30u/65n 30u/65n 30u/65n

TL1 TL2 TL3 TL4

M1 M2 M3V1

V2 V3

V4

All TL’s: Z0= 51.2 W=10u

(25% fill)

Radialstub

• No DC block: Forces VGS=VDS for M1 & M2, but eliminates loss and modeling uncertainties associated with DC-block cap

• FET size is chosen for low matching loss• Radial stub for lower loss than quarter-wave TL

14

FET Sizing

constant-gcircle (20mS)

constant-Q circle

S11

S22* (g22 g11)

Small FET

Large FET

Conjugate input/output/inter-stage match with shunt tuning stubs only.

Z0

15

0

1

2

3

4

5

6

7

140 150 160 170 180 190 200

Simulated 150-GHz Amplifier GainS2

1 (d

B)

Frequency (GHz)

Radial stub(45deg opening)

Open-stubZ0=34, W=20u

0.65V 1.1VAC short

Open-stubZ0=51, W=10u

¼λ

¼λ

PDC= 25mW

16

Die Photograph

Dummy-prefilled radial stub

Dummy-prefilled MS-lines

640m

Referenceplanes

640m

• Area = 0.4mm2 (w pads) = 0.16mm2 (w/o pads)

• Stack: 9 Cu + 1 Al

Automaticdummies

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S-parameter Measurement Setup

ProbeStation

140-220GHzmm-wave heads

8510CVNA

W/G Coax

WR05 IF/LO

OML Inc. AgilentGGB Probes

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Can we trust the calibration?

freq (140.8GHz to 199.3GHz)

TRL_

OPEN

3(2,2

)[i1::i2

]TR

L_TH

RU_s

el(2,2

)

freq (140.5GHz to 199.5GHz)

S22_

sel

S11LINE < -35dB

-0.4

-0.2

0

0.2

0.4

140 150 160 170 180 190 200

Frequency (GHz)

S21

(dB

)

S11THRU < -40dB|S21THRU| < 0.1dB

• Probe coupling < -40dB• Repeatability issues

– Probe placement– Probe contact resistance

|S11OPEN| < 0.2dB

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Prefilled MS-Line: Measurement

-5-4-3

-2-10

0 20 40 60 80 100 120 140 160 180 200Frequency (GHz)

|S21

| (dB

/mm

)

-120-100-80-60-40-20

0

0 20 40 60 80 100 120 140 160 180 200Frequency (GHz)

Phas

e (d

eg)

-2.0dB/mm @140GHz

-2.8dB/mm @200GHz

E/M Sim.

E/M Sim (8% error)

|S21

| (dB

/mm

)S2

1 Ph

ase

(deg

)

LINE standard

1mm-long Line

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Measured Amp. S-Parameters

-20

-15

-10

-5

0

5

10

140 150 160 170 180 190 200Frequency (GHz)

S-pa

ram

eter

(dB

)

S21

S22

S11meas

S11sim

MeasSim

0.65V 1.1V

Peak |S21|= 8.2dB

PDC= 25.5mW3dB BW= 27GHz

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S21 versus Current Density

3

4

5

6

7

8

010

2030

4050

60

100 200 300 400 500 600 700

10SF 3stg_150ghzS

21@

150G

Hz

[dB

]P

dc [mW

]

Iden [uA/um]

S21

(dB

)

Drain Current Density (uA/um)

DC

Pow

er (m

W)

V

0.5~0.9V

22

0123456789

0 10 20 30 40 50 60

DC power (mW)

S21

(dB

)S21 @Higher Drain Bias (M3)

V V V1.1V

V1=V2=V3<V4

0.5~0.9V

23

0

1

2

3

4

5

140 150 160 170 180 190 200

Amplifier Stability Factor

Frequency (GHz)

Stab

ility

Fac

tors

• Unconditionally stable over 140-200GHz.

B1 > 0

K > 1

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Large-Signal Setup

20 GHzSignalSource

x12Freq.

Multiplier

WR05Variable

Attenuator

PowerMeter

WR05-WR10

• Power correction: Insertion calibration using W/G THRU & On-wafer THRU

Virginia Diode Inc.

EriksonInstruments.

On-wafer DUT

PIN= -20dBm ~ +15dBmFreq= 153GHz ~175GHz

0.2dB lossWR05 GGB

probes

25

0

5

10

15

20

25

-20 -15 -10 -5 0 5-15

-10

-5

0

5

10

Large-Signal Characteristics

P out (d

Bm

), G

ain

(dB

)

Pow

er A

dded

Effi

cien

cy (%

)

Peak PAE= 8.4%

Psat= +6.3dBm

oP1dB= +1.5dBm0.65V 1.1V

freq= 153GHzPDC= 25.5mW

Pin (dBm)

26

0

2

4

6

8

10

140 150 160 170 180 190 200

Comparison of Measured S21

Frequency (GHz)

S21

(dB

)

S21 from VNA Meas.S21 from Power Meas.

• VNA Measurement: Full 2-port TRL calibration• Power Measurement: Insertion calibration

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Performance Summary

Technology 65nm digital CMOSTopology 3-stage Common-sourceCenter freq 150GHz3dB BW 27GHzPeak Gain 8.2dBInput RL -7.4dBOutput RL -13.6dBDC Power 25.5mWP1dB +1.5dBm

Psat +6.3dBm

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Conclusion

• Minimalistic Circuit Design Strategy• “Design-rule Compliant” Transmission Line

Structure and Modeling• Linear/Power measurement up to 200GHz• Highest frequency CMOS amplifier reported to date

29

Acknowledgement

• IBM for chip fabrication and support• OML Inc.• This work was supported by the NSF under grants

CNS-0520335 and ECS-0636621