Post on 05-Jan-2016
description
Luisa Pirozzi Luisa Pirozzi ENEA c-Si PV labsENEA c-Si PV labs
pirozzi@casaccia.enea.itpirozzi@casaccia.enea.it
Crystalline Silicon Solar Cells: from the Material to the Devices
ENEA Crystalline Si PV laboratory – Romehttp://wwwcas.casaccia.enea.it/sicri/
- -
II
-Cell fabrication processes
-Crystalline Silicon Solar Cells
I
-Introduction
-Cell Design
-Silicon technology
1839 (Becquerel): light-dependent voltage between electrodes immersed in an electrolyte
1941: first Silicon solar cell (announced in 1954)
1958: first space applications
• incident photons having energy higher than the band gap of the semiconductor are absorbed in the material generating electron and hole pairs
• carriers created at distance less than the diffusion lenght from the depletion layer are separated by the electric field there existing and a potential difference arises across the junction
• if the device is connected to a load the photoinduced voltage allows a current flow in the load
PV cell structure:• p-n junction with upper electrode shaped as a grid to allow light (photons) transmission
BACK CONTACT
DEPLETION LAYER
N - REGION
P - REGION
LOAD
+_
SUNLIGHT
+_+_
ANTIREFLECTIVE COATING
FRONT CONTACT(GRID)
2000
0.3 1.1 2.5wavelength m)
Energy distribution(W/m2 /
m)
1000
h < Eg
h - Eg
net energy
Spectral distribution of sunlight
As for IC, Silicon is not the best material for solar cells:
band-gap too narrow and low absorption coefficient (indirect gap)
0
5
10
15
20
25
30
35
0 0,5 1 1,5 2 2,5 3 3,5 4
Eg (eV)
Eff
(%
)
Single crystalline Si 24,7%
Multicrystalline-Si 19,8%
GaAs
1E-02
1E-01
1E+00
1E+01
1E+02
1E+03
1E+04
1E+05
1E+06
1E+07
300 400 500 600 700 800 900 1000 1100 1200
Wavelength (nm)
Ab
sorp
tio
n C
oef
fici
enct
(cm
-1)
1E-07
1E-06
1E-05
1E-04
1E-03
1E-02
1E-01
1E+00
1E+01
1E+02
Ab
sorp
tio
n D
epth
(
cm)
REG
ION
N
REG
ION
P
GR
ID
AR
C
PV CELL PARAMETERS
Pm = Vm Im
Vm
Im
Voc
Isc
V
I
Isc =short circuit currentVoc=open circuit voltagePm=maximum power output= Vm Im FF=Fill Factor=Pm / Isc * Voc
=efficiency =Pm / Pin= Voc IscFF/ PinPin=total power of incident light
0I
Iln
q
nkTV L
ocLsc II 0/ IIln
1nkT
qV1ln
1FFL
m
1exp0 nkT
IRVqIII(V) s
L
IL=photogenerated currentI0=diode saturation currentq=electron chargeRs=series resistance n=diode ideality factor (1 - 2)k=Boltzmann’s constant
0,0 0,2 0,4 0,6 0,80
1
2
3
4
I-V curves at different light Intensities
Volt
Am
p.
I1 = 1 kW/m2
I2 = 0,5 kW/m2
0,0 0,2 0,4 0,6 0,80
1
2
3
4
VoltA
mp
.
T1 = 20°C
T2 = 60°C
I-V curves at different Temperatures
-Cell Design
- the cell design must take into account its application:
Production-terrestrial, space, concentration, architecture, etc
Lab- high efficiency, theoretical limit
-process lay-out: from three to more than 20 steps
production line –clean room
-Si cells theoretical efficiency limit: 27%
-Record efficiency: 24.7%- Average efficiency (production): 14.5%
Cell Parameters
•Jsc- short circuit current optical absorption
base recombination (red light)
emitter recombination (blue light)
•Voc- open circuit voltage bulk recombination (Job)
emitter recombination (Joe)
Space charge region (Jor)
•Fill FactorIdeality factor (n)
Series resistance (Rs)
Shunt resistance (Rsh)
To optimise cell efficiency:-Increase carriers
generation-Increase carriers
collection
Recombination:Joe: Front surface
EmitterJr: space charge region Job: Base
Back
Resistive:Bulk
EmitterBack
Contact gridShunt
Losses: recombination, resistive
Crystalline Silicon
• over 90% of world-wide solar cell production
(1400 MW in 2005)
- Second most abundant element
- Only semiconductor employed in microelectronic industry
Large-scale production/Technology coming from microelectronics
-Silicon technology
Silicon is the second most abundant element, but about half of the cell cost is due to the substrate.
Silicon production steps:
1) From sand to metallurgical-grade Silicon (MG-Si)
2) MG-Si to semiconductor-grade Silicon (SeG-Si)
3) Crystal growth
“sand”coke
Arc Furnace Fluid bed Reactor
UMG-Si SiHCl3
HCl
1-2 $/kg
Siemens
ProcessIngots for electronics
poly
60 $/kg15 - 30$/kg
Scraps
Solar grade silicon
Silicon Silicon
Multi crystalSingle crystal
Low quality
Metallurgical-grade Silicon (MG-Si)
- Due to the relative impurity of sand, quartzite – 99% SiO2- is the starting material.
- Silicon is produced in an Arc Furnace, at T about 1900°C, reducing SiO2 by Carbon ( coke, coal and wood chips):
SiO2 + 2C Si + 2 COLiquid silicon is poured into shallow troughs.
MG-Si 98% pure (major impurities Fe and Al). Cost 1-2$/Kg
Metallurgical-grade Silicon (MG-Si)
Semiconductor grade Si (SeG-Si)For use in electronics, impurities must be almost completely removed
MG-Si purification (Siemens process)
MG-Si is converted to a volatile compound
Si + 3HCl = SiHCl3 + H2
Trichlorosilane is produced by multiple fractional distillation
SeG-Si is obtained reducing Trichlorosilane by H2:
SiHCl3 + H2 = Si + 3HCl
Result: polysilicon
Crystal Growth
-Silicon for electronic industry must be not only impurity-free, but also a single crystal, defect-free.
-Poly-Si is molten and grown into single-crystal ingots:
Czochralsky (CZ)Floating Zone (FZ)
-SeG polycrystalline Si is molten in a crucible, at T=1410 °C
-A crystal seed is dipped into the molten Si and pulled slowly out of the melt in the vertical direction while rotating: crystallization at solid/liquid interface
- SeG- Si residual impurities are confined in liquid phase
- dopants (B, P) can be added to the melt - Ld=200m sec
Czochralsky (CZ) method
-A zone of molten Si is slowly passed along the length of a poly-Si ingot.
-Material melts at one boudary and recrystallizes at the other.
-High purity regrown Si crystal: no crucible, liquid region prevents impurity from entering the growing crystal
-Ld>500m sec
Floating Zone (FZ) Method
•Microelectronics 1 Si wafer for >106 chips•Photovoltaic 1 Si wafer for 1,5Wp; 1,5KWh/year
•PV application requirements much less severe than in electronics: -impurity levels-carriers transport properties
•Silicon especially developed for PV: Multi-crystalline Si Ribbon Solar grade Si
-Crystalline grains random oriented.
-Grain boundaries: recombination centers - shunt paths for current.
-Columnar structures and large grains (some mm): comparable to single-crystal
Ld>150 m >10 sec
-Production less expensive
-55% Si cells production on mc-Si (record EFF: 19,8%)
Multi-crystalline Si
Casting
-starting material: scraps of ingots for microelectronics, molten in a quartz crucible.
- DS method:Solidification starts from the bottom: columnar ingot growth.
Ld 200m >10 sec
Multi-crystalline Silicon
- Almost half of the material is lost during wafering.
•Silicon is grown in ribbons (250-300m)-EFG method (Edge-defined-Film-fed-Growth): Molten Silicon moves up the interior of a grafite die by capillarity.
Ribbon
Solar grade Silicon
-some metallic impurities can be present in concentrations>1015/cm3
(100 times > SeG-Si)
-Preparation of Silane (SiH4) from metallurgical grade Si-Deposition of Si from SiH4
N
at/cm3
-Cell fabrication processes
Emitter formation
Ohmic Contacts
Anti Reflection treatments
Emitter
•photogeneration in blue region of spectrum•collection of photogenerated carriers
shallow, lightly doped, passivated (low recombination)
•Contribution to Series Resistance:
deep, heavily doped
•Compromise: junction profile
REGION N
REGION P
GRID
ARC
n/p Junction
-thermal diffusion of dopant atoms into the silicon (p doped during growth)
n type
(donors)
Phosphorus
Arsenic
Antimony
p type
(acceptors)
Boron
Aluminum
Gallium
Phosphorous thermal Diffusion in Silicon
-Phosphorus: most usedFick laws: I) J= -D grad C II) C/ t = D 2C/ x2
J = fluxC = concentration
Diffusion source:
Solid
Liquid
Gaseous
Doped Oxide, spin-on, screen printing, thin films
laser
Open tube
“open tube” diffusion:a) Predeposition on wafer surface
b) Drive-in: P atoms diffusion
T: 800-1000 °C; N2 and O2
N2
Quartz tube
Silicon Wafers
Exhaust
Quartz
O2
Carrier Gas
Reactive Gas
Carrier Gas
N2p
Thermostat
POCl3 25 ºC
Mass flowmeters
Source: POCl3
2POCl3 + 3/2O2 P2 O5+3 Cl2 Si + O2 SiO2
5Si + 2P2 O5 5SiO2 +4P
SiO2 : better control of diffusion process
•Temperature, time duration and dopant source determine:-P surface concentration,Cs
-xj=junction depth-resistance and of diffused region
- when Cs > P solubility limit (1021 at/cm3 a 1000ºC) dead layer: high defect density region , low
-Concentration profile:
C(x,t)=Cs erfc(x/2Dt)
D= D0 exp (-E/KT) P diffusion coefficient in Si (10-14 cm2/sec a 980 ºC)
Laser Assisted Doping laser beam creates dopant atoms (PCl3 pyrolysis or solid source) and simultaneously induces melting of silicon: dopant liquid phase diffusion. Localized process, low thermal budgetFast diffusion kinetics
p - Si
n+
p - Si
PP
P
PPP
PCl3
TEM picture of laser doped silicon after re-
crystallization Dopant concentration profile
Surface Passivation•Surface: critical discontinuity in the crystal structure-High density of allowed states within the forbidden gap
•Silicon: surface-state density reduced growing passivating oxide-interface between oxide and Si moves
towards bulk
•Thermal Oxidation: open tube, in O2
at T 800-1000 °C
•low T alternative: SiN layer
400 600 800 1000 1200
0.0
0.2
0.4
0.6
0.8
1.0
B sel23ox
D sel23
E om23
F sel23+om96
Y A
xis
Tit
le
X axis title
Ohmic Contacts
-Front contact must minimize series resistance losses, providing at the same time the maximum light amount to reach the cell surface.
-A good back contact allows to increase Jsc and Voc (confinement techniques).
-Good ohmic contact metal/silicon-Low metal resistivity
Front Grid: -Busbar are directly connected to the external load
-Fingers collect current to delivery to a busbar.
Ohmic Contacts
Rs=Rbase+Remitter+Rgrid
Contact technologies
- photolitography vacuum
evaporation
-screen printing
- electrochemical growth
Deposition technique/Metal
Electro-plating
Electroless
Evaporation Screen printing
Ni Front Front
Au F/B F/B F/B
Ag Front Front Front
Ti Front
Pd Front
Al Back Back Back
Metal/Si contact-Schottky barrierHigh contact resistance
-ohmic contact is obtained by reducing barrier width:
tunneling
- high P concentration at Si surface can reduce barrier
width:Highly doped emitters
Alloying
Annealing at T 450-800 °C
metal Silicon
Photolitography
- photosensitive polymer is deposited on wafer surface-Regions to metallize are exposed through a mask to UV light- Vacuum evaporation Front: Ti (400 A) adherence to Si
Pd (200 A) barrier layer Ag 1-5 m good conductivity
Back: Al 1m-Lift-off: photoresist removed in acetone-Annealing: 400- 600 °C N2 or forming gas ohmic contactResolution: few micronsShadowing < 4%
Screen printing
-contact grid is obtained by depositing on wafer surface, through metal screens, inks or conductive pastes-inks contain metal grains (Ag, Al), glasses, organic binders and solvent
-Firing:In a belt furnace, the glass melting temperature (about 800°C) is reached for few minutesContact to Si: alloy metal/Si (Al) through glass matrix (Ag)•Resolution: 80-100 micronShadowing:10%
0
100
200
300
400
500
600
700
800
900
1000
0 10 20 30 40 50 60 70
Tempo (s)
Tem
pera
tura
(°C
)
Selective Emitter
•Heavy doped emitter :low response in blue region -“dead layer”, photogenerated carriers have low probability to be collected-
•Selective emitter:regions under contacts are heavy doped, to reduce RcExposed region is low doped to increase collection in blue spectral portion
- double diffusion, laser doping
Back Surface Field
Bulk
Emitter
Wb WBSF
p
EF
BSFn+
p+
p e-
SfSeff Sb
T 577C
(b)
Al/Si-liquid
Si
T=25C
Al-layer
(a)
Si
T 577C cooling
(c)
Al/Si-liquid
p-Si
p+-Si
T 577Ccooling
(d)
Al/Si-layer
p-Si
p+-Si
AntiReflection treatments
•Silicon reflects 35% of incident light, and up to 54% at short(high refractive index n)
•Techniques to reduce losses:
-Deposition of one or more layers of thin oxides
- Surface Texturization
Thin AR layers
•losses due to reflection can be drastically reduced
10
101
nn
nnr
2cos1
2cos2
2121
2121
22
22
rrrr
rrrrR
2
02
02
nn
nnR
21
212
nn
nnr
112 dn
2
201
201
min 2
2
nnn
nnnR
minRR
4
011
dn
0min R
1
01
4nd
201 nnn
Thin AR layers
• single layer AR coating:
0= 600 nm; n1=2.0; d1=750 A
•Losses reduced to 10%
Material n
Si 3,45
SiO 1,9
Al2O3 1,9
Si3N4 2,0
TiO2 2,2
Ta2O5 2,2
Double layer AR coatings-better match between high index of Si (3,5) and low index of air (1)
-AR effect over a wide wavelength range
- losses reduced to 3%
Material n
Si 3,45
TiO2 2,2
SiO2 1,5
ZnS 2,3
MgF2 1,4
1st layer: n1=2.2-2.62nd layer: n3=1.3-1.6
2
0231
0231min
22
22
nnnn
nnnnR
Internal Quantum Efficiency and Total Reflectance of cell
0
10
20
30
40
50
60
70
80
90
100
300 400 500 600 700 800 900 1000 1100 1200
Wavelength (nm)
IQE
(%
)
0
10
20
30
40
50
60
70
80
90
100
Ref
lect
ance
(%
)
IQE0.3-4
ARC deposition methods
• vacuum Evaporation
•Sputtering
•Chemical Vapour Deposition
•Plasma Enhanced CVD
- thickness uniformity and reproducibility-Stoichiometry control
Texturing
•pyramidal structures (about 10 microns) on wafer surface
• incident light is trapped (multiple reflections)
-larger exposed area-Oblique incidence (increased collection efficiency at long
Reflectance < 10%
with ARC < 4%
-wet anisotropic etch NaOH or KOH based
-Different etch rates along different crystallographic
directions:
etch rate about 35 faster for <100> direction than for <111>
direction.
100
010
111
001
-for Si <100> oriented, structure is achieved by intersection between the <100> and <111> planes (=54.7°), allowing at least two consecutive reflections
-Inverted pyramids structure reduces reflection to few
percent
-honeycomb: traps light in multi-
crystalline Si cells
Texturing
Crystalline Silicon Cells
• High Efficiency cells: 24.7%
• Industrially Scalable Cells– New Design: 20%– Advanced Screen Printing: 18-19%
• Industrial cells: 14-15%
Thin polysilicon cells: -14%
PERL (Passivated Emitter and Rear Locally diffused) Cell
Voc= 706 mV, Jsc=42.2 mA/cm2 FF=82,8%
=24,7% (UNSW)
• Double AntiReflection Coating (DARC) and inverted pyramids
• Passivating oxide on front (10 nm, Sf<10 cm/s)
• Selective emitter
• High purity material, high resistivity FZ (>1 *cm =>Ld=1 mm)
• Passivating oxide on Back (150-300 nm, Sb<10cm/s)
• Boron overdoping on back contact regions
• 19.8% on multi-crystalline Si
27.5% 100X
Point Contact cells
Back Sided Point Contact Solar Cell (Stanford University)
Buried Contact Solar Cell
• Buried contact grid (laser or mechanical), Selective emitter, Back Surface Field, electroless metal plating
EFF 19-20% (>21% on bifacials)
UNSW
BURIED CONTACT
SOLAR CELLS
• Bi-facial cells: carriers are generated also by light incident on the back side EFF 21% (FhG-ISE) – 19% (Buried contacts)
• “ emitter wrap-through” cells: back-contact solar cells, with emitter contacts on the rear realized through laser –drilled vias. 17% on 225 cm2 mc-Si cells (ECN)
Advanced Screen Printing• High efficiency solutions: -Selective emitter obtained by screen printing of a doped paste - Screen printed contact buried cells-Low temperature (SiN, a-Si) layers deposition on front and back for surface and bulk passivation.
19.8% SiN ( GeorgiaTech)
Future developments
-Short term: lower cost (thinner wafers, further efficiency
enhancement, new structures, etc)
-Long term: spectrum conversion to utilize the solar radiation more completely
Crystalline silicon cells will dominate the market for a very long time
Thank you for your attention