Post on 22-Sep-2020
Luis Angel BathenLuis Angel BathenInformation and Computer Science/ComputerInformation and Computer Science/Computer
Science EngineeringScience Engineering
School of Information and Computer ScienceSchool of Information and Computer Science
University of California, IrvineUniversity of California, Irvine
Research GroupResearch Group
ßß Professor Nader BagherzadehProfessor Nader Bagherzadehßß Department of Electrical Engineering andDepartment of Electrical Engineering and
Computer Science, Henry Computer Science, Henry Samueli Samueli School ofSchool ofEngineering, University of California, IrvineEngineering, University of California, Irvine
ßß Advanced Computer Architecture GroupAdvanced Computer Architecture Group(ACAG)(ACAG)ßß HenryHenry Samueli Samueli School of Engineering,School of Engineering,
University of California, IrvineUniversity of California, Irvine
AbstractAbstract
ß A Fast and Innovative Approach Towardsan Automatic Target Recognition SystemImplementation on a ReconfigurableArchitecture
OutlineOutline
ßß Overview and ObjectivesOverview and Objectives
ßß Introduction to MorphoSys (M2)Introduction to MorphoSys (M2)
ßß Introduction to ATRIntroduction to ATR
ßß Mapping of ATR SLD onto MorphoSysMapping of ATR SLD onto MorphoSys
ßß Results and ConclusionsResults and Conclusions
About ResearchAbout Research
ßß OverviewOverview
ßß GoalsGoalsßß ATR: To save lives of soldiers in the battleATR: To save lives of soldiers in the battle
field.field.
ßß Project: To explore a new approach at theProject: To explore a new approach at theimplementation of an ATR system.implementation of an ATR system.
MorphoSysMorphoSys
ßß Types of computer architecturesTypes of computer architectures
ßß Introduction to reconfigurableIntroduction to reconfigurablearchitecturesarchitectures
ßß MorphoSysMorphoSys
MorphoSys ArchitectureMorphoSys Architecture
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Main Memory
TinyRISC
Context Memory
FrameBuffer
DMA
Automatic Target RecognitionAutomatic Target Recognition
ATR Processing HighATR Processing HighLevel OverviewLevel Overview
Several K
FOA
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Shape Sum Calculation
Template Correlation
Template_0 Template_n
PeakDetector
Target TemplatesTarget Templates
SC: 16 BC: 18
Surround Mask Bright Mask
Second Level Of DetectionSecond Level Of Detection(SLD)(SLD)
ßß Introduction to SLDIntroduction to SLDßß SLD algorithm:SLD algorithm:ßß Calculate Shape Sum SM(i,j)Calculate Shape Sum SM(i,j)ßß Calculate Threshold value TH(i,j)Calculate Threshold value TH(i,j)ßß Calculate Bright Sum BS(i,j)Calculate Bright Sum BS(i,j)ßß Calculate Surround Sum SS(I,j)Calculate Surround Sum SS(I,j)ßß Calculate Hit Quality HQ(i,j)Calculate Hit Quality HQ(i,j)
SLD ProcessSLD Process
Shape SumSM(i,j)
ThresholdTH(i,j)
Hit QualityHQ(i,j)
Bright SumBS(i,j)
Surround SumSS(i,j)
Image(i,j)
Mathematics Behind SLDMathematics Behind SLD
ßß Shape SumShape Sum n-1 n-1n-1 n-1
ßß SM(i,j) = SM(i,j) = ∑∑∑∑B(u,v)MS(i+u,j+v)B(u,v)MS(i+u,j+v) u u00vv00
ßß Threshold CalculationThreshold Calculationßß TH(i,j) = SM(i,j) / BC - BiasTH(i,j) = SM(i,j) / BC - Bias
ßß Bright SumBright Sum
n-1 n-1n-1 n-1
ßß BS(i,j) = BS(i,j) = ∑∑∑∑B(u,v)[MS(i+u,j+v) B(u,v)[MS(i+u,j+v) ≥≥ TH(i,j)] TH(i,j)] uu00vv00
Mathematics Behind SLDMathematics Behind SLD(Cont.)(Cont.)
ßß Surround SumSurround Sum n-1 n-1n-1 n-1
ßß SS(i,j) = SS(i,j) = ∑∑∑∑B(u,v)[MS(i+u,j+v) < TH(i,j)]B(u,v)[MS(i+u,j+v) < TH(i,j)] u u00vv00
ßß Hit Quality CalculationHit Quality Calculationßß HQ(i,j) = 1/2(BS(i,j)/BC + SS(i,j)/SC)HQ(i,j) = 1/2(BS(i,j)/BC + SS(i,j)/SC)
RC ArrayRC ArrayData TransferData Transfer
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Loading the SAR 8x8x8-bitLoading the SAR 8x8x8-bitPixel Image onto RC_ARRAYPixel Image onto RC_ARRAY
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Reg_08-bitvalue
Loading the 8x8x1-bitLoading the 8x8x1-bitTemplates onto RC_ARRAYTemplates onto RC_ARRAY
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Reg_N
MorphoSys ProgrammingMorphoSys ProgrammingSchemeScheme
Tiny RISC Code
ldli $3, 0x7000 ldctxt $3, 1, 0, 25
ldli $4, 200delay3:subi $4, $4, 4Nopbrle $0, $4, Delay3Nop
# LOAD IMAGEldrcex $1, 1, 0, 0, 1, 0rcex 1, 0, 0, 1rcex 1, 0, 0, 2rcex 1, 0, 0, 3rcex 1, 0, 0, 4rcex 1, 0, 0, 5rcex 1, 0, 0, 6rcex 1, 0, 0, 7rcex 1, 0, 0, 8
Column Context
C: FB2RC_RC_REG8{0: BYP FB > R8;1: BYP FB > R8;2: BYP FB > R8;3: BYP FB > R8;4: BYP FB > R8;5: BYP FB > R8;6: BYP FB > R8;7: BYP FB > R8;}C: FB2RC_RC_COL_0{0: BYP R8 V0 > R0;1: BYP R8 V0 > R1;2: BYP R8 V0 > R2;3: BYP R8 V0 > R3;4: BYP R8 V0 > R4;5: BYP R8 V0 > R5;6: BYP R8 V0 > R6;7: BYP R8 V0 > R7;}
RC Array Row OperationsRC Array Row Operations
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R: SHAPESUM-ROW-ADDITION-FIRST-STAGE{0: ADD R11 V1 > R11 | R11;1: KEEP;2: ADD R11 V3 > R11 | R11;3: KEEP;4: ADD R11 V5 > R11 | R11;5: KEEP;6: ADD R11 V7 > R11 | R11;7: KEEP;}R: SHAPESUM-ROW-ADDITION-SECOND-STAGE{0: ADD R11 V2 > R11 | R11;1: KEEP;2: KEEP;3: KEEP;4: ADD R11 V6 > R11 | R11;5: KEEP;6: KEEP;7: KEEP;}R: SHAPESUM-ROW-ADDITION-THIRD-STAGE{0: ADD R11 V4 > R11 | R11;1: KEEP;2: KEEP;3: KEEP;4: KEEP;5: KEEP;6: KEEP;7: KEEP;}
Previous ResultsPrevious Results
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MorphoSys Mojave Splash 2
Simulation ResultsSimulation Results(SIM_ATR and MuLate)(SIM_ATR and MuLate)
ßß SIM_ATRSIM_ATRßß Average Time for SLD on 8x8 SAR image is Average Time for SLD on 8x8 SAR image is ≈≈
0.17 ms0.17 ms
ßß These results are for 8 simultaneous templateThese results are for 8 simultaneous templatecorrelationscorrelations
ßß This simulation was done one a PowerPC G4This simulation was done one a PowerPC G4running at 800MHz and using Java 1.4running at 800MHz and using Java 1.4technology.technology.
Simulation ResultsSimulation ResultsContinuationContinuation
ßß This SLD SIM_ATRThis SLD SIM_ATRimplementation returnsimplementation returnsthe best values for thethe best values for theinitial points for the 8x8initial points for the 8x8blocks of data.blocks of data.
ßß SIM_ATR embeddedSIM_ATR embeddedpeak detector takes SLDpeak detector takes SLDresults and uses them toresults and uses them todetect the target locationdetect the target locationfor the recognitionfor the recognitionprocess.process.
Simulation ResultsSimulation ResultsContinuationContinuation
ßß MuLateMuLate
5.082287SLD process
4.00e-1181Total Processing
4.682106Total Loading
1.33e-26Hit Quality
8.89e-34Threshold
1.53e-169Bright Sum
1.46e-166Surround Sum
8.00e-236Shape Sum
3.53e-1384Data Load
3.831722Context Load
Time µs# CyclesPhase
AcknowledgementsAcknowledgements
ßß GodGod
ßß Mom and FamilyMom and Family
ßß Kika Kika Friend, Summer Scholars,Friend, Summer Scholars,TRIO/McNair - CAMP programsTRIO/McNair - CAMP programs
ßß Professor Nader BagherzadehProfessor Nader Bagherzadeh
ßß Advanced Computer Architecture GroupAdvanced Computer Architecture Group
ReferencesReferencesß [1] H. Singh, Lee, Lu, Bagherzadeh, Kurdahi, “MorphoSys: An integrated Reconfigurable System for Data-
Parallel and Computation –Intensive Applications,” IEEE Transactions on Computers, vol. 49, No. 5, pp. 465-481,May 2000.
ß [2] H. Sigh, M. Lee, G. Lu, F. Kurdahi, N. Bagherzadeh, T. Lang, R. Heaton, E. Filho. “An Integrated Re-configurable Architecture.” NATO Symposium on Concepts and Integration, April 1998.
ßß [3][3] H. Singh, Lee, Lu, Bagherzadeh,H. Singh, Lee, Lu, Bagherzadeh, Kurdahi Kurdahi, , ““Design and Implementation of the MorphoSys ReconfigurableDesign and Implementation of the MorphoSys ReconfigurableComputing Processor,Computing Processor,”” Journal of VLSI Signal Processing Systems for Signal, Image, and Video Technology, Journal of VLSI Signal Processing Systems for Signal, Image, and Video Technology, vol vol..24, No. 2-3,24, No. 2-3, Kluwer Kluwer Academic Publishers, pp. 147-64, Mar 2000. Academic Publishers, pp. 147-64, Mar 2000.
ß [4] J. Villasenor, B. Schoner, K. Chia, C. Zapata, H. J. Kim, C. Jones, S. Lansing, and B. Mangione-Smith, “Configurable Computing Solutions for Automatic Target Recognition,” Proceedings of IEEE Conference on FieldConfigurable Computing Machines, April 1996.
ß [5] M. Rencher, B. Hutchings, " Automated Target Recognition on SPLASH 2," Proc. of IEEE Symp. onFCCM, April 1997.
ß [6] SANDIA National Laboratory - ATR www.sandia.gov/www.sandia.gov/atratrß [7] R. Sivilotti, Y. Cho, W. Su, and D. Cohen, “Scalable, Network-Connected, Reconfigurable Hardware
Accelerators for an Automatic-Target Recognition Application,” Myricom Technical Report, May 1998.ß [8] Pan, Kamalizad, Koohi, Bagherzadeh, “Design and Analysis of a Programmable Single-Chip Architecture
for DVB-T Base-Band Reciever,” To Appear in DATE 2003.ß [9] Kamalizad, Pan, Bagherzadeh, “A Reconfigurable Computation Platform and Case Study of Fast FFT
Implementation,” To Appear in DATE 2003.ß [10] Kamalizad, “Several DBV-T Cores Mapping into MorphoSys Architecture,” Masters Of Science Thesis
2003.
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