Post on 08-Apr-2018
8/6/2019 L5 Generate Block
1/17
Generate Statement A generate statement provides a mechanism for
iterative or conditional elaboration of a portion of
description. The iterative elaboration of a description is a
convenient mechanism to instantiate and replicateconcurrent statements.
The replication index is either a constant or ageneric.
This is often used to instantiate and connectcomponents.
8/6/2019 L5 Generate Block
2/17
8/6/2019 L5 Generate Block
3/17
Generate It is equivalent to the sequential statement
LOOP.
It allows a section of code to be repeated a
number of times, thus creating several
instances of the same assignments.
8/6/2019 L5 Generate Block
4/17
There are two forms of the generate
statement.
1. Using the for-generate scheme, concurrent
statements can be replicated apredetermined number of times.
2. With the if-generation scheme, concurrentstatements can be conditionally selectedfor execution.
8/6/2019 L5 Generate Block
5/17
generate-label: forgenerale-identifierin
discrete-range
generate
concurrent-statements
end generate [generate-label];
8/6/2019 L5 Generate Block
6/17
Consider the following representation of a 4-bit full-adder, shown in Fig. 1, using thegenerate statement.
entityFULL_ADD4 is
port(A, B: in BIT_VECTOR(3 downto0); CIN: in BIT;
SUM: outBIT_VECTOR(3 downto0); COUT: outBIT);
end FULL_ADD4:
architecture FOR_GENERATE ofFULL_ADD4 is
componentFULL_ADDER
port(A, B, C: in BIT; COUT, SUM: outBIT);
end component;
signalCAR: BIT_VECTOR(4 downto0);
begin
CAR(0)
8/6/2019 L5 Generate Block
7/17
After elaboration, the generate statement is expanded to
FA(3): FULL_ADDERportmap (CAR(3), A(3), B(3), CAR(4),
SUM(3));
FA(2): FULL_ADDERportmap (CAR(2), A(2), B(2), CAR(3),
SUM(2));FA(1): FULL_ADDERportmap (CAR(1), A(1), B(1), CAR(2),
SUM(1));
FA(0): FULL_ADDERportmap (CAR(0), A(0), B(0), CAR(1),
SUM(0));
8/6/2019 L5 Generate Block
8/17
the if-generation scheme.genarate-label: if expression generate
concurrent-statements
end generate [generete-label] ;
8/6/2019 L5 Generate Block
9/17
entityCOUNTER4 is
port(COUNT, CLOCK: in BIT; Q: bufferBIT_VECTOR(0 to3));
end COUNTER4;
architecture IF_GENERATE ofCOUNTER4 is
componentD_FLIP_FLOP
port(D, CLK: in BIT; Q: outBIT);
end component;
begin
GK: forKin 0 to3 generate GKO:
ifK = 0 generateDFF: D_FLIP_FLOP portmap (COUNT, CLOCK, Q(K));
end generate GK0;
GK1_3: ifK > 0 generate
DFF: D_FLIP_FLOP portmap (Q(K-1), CLOCK, Q(K));
end generate GK1_3;
end generate GK;
end IF_GENERATE;
8/6/2019 L5 Generate Block
10/17
4 bit counter
8/6/2019 L5 Generate Block
11/17
Block Statement A block is representative of a portion of the hierarchy of
the design.
One of the major purpose of a block is to disable signals(I.e. the signal drivers) by using a guard expression.
A guard expression is a Boolean-valued expression
associated with a block statement that controls assignments
to guarded signals within a block.
A guard expression defines an implicit signal GUARD that
may be used to control the operation of certain statements
within the block.
8/6/2019 L5 Generate Block
12/17
BLOCK Two types Block
Simple and Guarded
Simple Block
The Block statement, in its simple form represents
only a way of locally partitioning the code.
It allows a set of concurrent statements to be
clustered into a Block.
A Block can be nested inside another BLOCK.
8/6/2019 L5 Generate Block
13/17
Block Syntax (Simple)Label : BLOCK
[Declartive part]
Begin
(Concurrent statements)
End BLOCK label;
8/6/2019 L5 Generate Block
14/17
Guarded Block A Guarded Block is a special kind of Block, which
includes an additional expression, called guard
expression. A guarded statement in a guarded BLOCK is
executed only when the guard expression is
TRUE.
Even though only concurrent statements can be
written within a block, with a guarded block
sequential circuit can be constructed.
8/6/2019 L5 Generate Block
15/17
Guarded Block syntaxLabel : BLOCK (guard expression)
[Declarative part]
Begin
(Concurrent guarded and unguarded
statements)
End BLOCK label;
8/6/2019 L5 Generate Block
16/17
Advantages of Blocks1. Faster synthesis compilation time: Synopsys
provides a group hdl_block directive that
groups design partition and creates new level ofhierarchies. This approach can significantly
reduce the compilation time.
2. Information Hiding: Within a block, local type
and signal declaration can be defined. Thesignals within the block are local to the block,
and are not visible by the architecture.
8/6/2019 L5 Generate Block
17/17
Advt. Of blocks (cont..)3. Declaration of partition interfaces: The block
header enables the definition of local generics,ports and port maps. All synthesizer vendors do
not necessarily support block headers.4. Visibility into architecture: Since a block is a
concurrent statement of an architecture, a blockhas visibility into ports and signals of the
architecture and into the declaration of thecomponent within the architecture.
A block also has visibility into packages, constantsand types declared in the entity and architecture.