Post on 21-Sep-2020
JSS MAHAVIDYAPEETHA
JSS ACADEMY OF TECHNICAL EDUCATION JSSATEB Campus, Dr. Vishnuvardhan Road, Srinivasapura, Bengaluru-560060 Karnataka India
Affiliated to Visvesvaraya Technological University, Belagavi, Karnataka, INDIA
Approved by All India Council for Technical Education, New Delhi
UG programs accredited by NBA: ECE, CSE, ISE, CIVIL, MECHANICAL, IEM, E & IE
Innovative teaching-Learning and its mapping of, Dept ECE,
From 2019 - 2020 Odd
Sl.
No.
Name of the Faculty Subject Topic Innovative type CO PO PSO Mapping is
done
Yes/no
1 Sunita Shirahatti
& Dr Tejaswini P
Verilog
HDL/17EC53
Simulation: Simulation of
Digial Circuits and
applications
Collaborative
learning: to
simulate and
synthesize various
digital arithmetic
circuits using
modern tool
C303.5 PO1,
PO2,
PO3,
PO4,P
O5,
PO8,
PO9,
PO10,
PO12
PSO
2,
PSO
3
yes
2 Dr. Usha S.M
Satellite
Communication/
15EC755
Flip-Mode Topic
Presentation and
Report Writing
CO405
.1,
CO405
.2,
CO405
.3
CO405
.4
CO405
.5
PO1
PO2
PO10
PSO
1
yes
3 Spandana
Shashikumar and
Suguna G C
Object Oriented
Programming
using
C++/17EC562
Simulation: Simulation and
demonstration of various
topics like pointers,
inheritance, files and
constructors from C++
Collaborative
learning: to
simulate and
demonstrate
Various topics
from C++
C3062.
5
PO1,
PO2,
PO3,
PO4,
PO5,
PO9,
PO10,
PO11
PSO
1,
PSO
2
No
4 Ashwini Dasare Management
and
Entrepreneurshi
p /17ES51
Collaborative learning: to
Have their own start up
Activity based
Learning
C3062.
5
PO9,P
O10,P
O11
- NO
5 Gunasagari G S
Dr.
VeerammaYatnalli
Information
Theory and
Coding
1. Simulation of ITC
Algorithm using
MATLAB
2. Animation:Convoluti
onal coding
1.Simulation
2.Activity Based
Learning(Collabor
ative Learning)
3.Teaching
Concepts Through
Animation
C304 PO1,
PO2,
PO3
PO5,
PO9,
PO10
PSO
1,
PSO
2
Yes
6 P M Shivakumara
swamy
DIP (15EC72) 1)Morphological operation
2) Simulation of Basic Image
Processing Techniques
Video
Matlab Simulation
CO4
PO5,P
O9
PSO2
yes
7 Dr.
Mallikarjunaswa
my S
COMPUTER
ORGANIZATION
AND
ARCHITECTURE
/18EC35
Collaborative learning: to
simulate memory mapping
Technics
Teaching
concepts through
Animation
C205.1
C205.2
C205.3
C205.4
PO2,
PO3,
PO5
PSO
1,
PSO
3
L4
Innovative Teaching
Faculty Name : Dr Thejaswini P Sem/Sec : 5B
Subject : Verilog HDL Subject Code : 17EC53
Sem Duration: Aug 2019-Jan 2019 Academic Year: 2019-2020 Total strength : 67 number of students feedback: 67
Innovative Teaching methods
Method Activity Indicate with Tick mark
M1 SIMULATION ✓
M2 Activity based Learning (Collaborative learning &
implementation of given problem statement)
✓
M3 Flip-Mode (Circulate Video & Audio material in
advance & discuss the related topics in the class)
M4 Case Studies
M5 Teaching concepts through Animation
Inference:
Through collaborative learning students could work in team and individual level to
implement, Simulate and Synthesize the problem statement mentioned in activity, submit a
report and present the topic in the class.
DEPARTMENT OF ELECTRONICS AND COMMUNICATION ENGINEERING JSS ACADEMY OF TECHNICAL EDUCATION
JSS Campus, Uttarahalli-Kengeri Main Road, Bangalore - 560060.
SL.NO Topic for
teaching
Activity to
students
COs POs PSOs Bloom’s
level
CO
attain
ment
Level
1 Simulation:
Simulation
of Digial
Circuits and
applications
Collaborative
learning: to
simulate and
synthesize
various digital
arithmetic
circuits using
modern tool
C303.5 PO1, PO2, PO3,
PO4,PO5, PO8,
PO9, PO10, PO12
PSO2,
PSO3
L3 1
CO Covered: C303.5
C303.5 Analyze and implement digital systems using HDL. L4
Objectives: Students should be able to
• Analyze, design and implement given digital arithmetic circuits using verilog HDL.
• Work in team and improve the oral / written communication skills.
No. of
Students
Attended
Marks scored/Grade
Attainment PO’s Mapped
PSO’s
Mapped
No. of
students
who
scored
5M
No. Of
students
who
scored
4M
No. Of
students
who
scored
3M
No. Of
students
who
scored
<=2 M
63 57 6 - - PO1,PO2,PO3,PO4,PO5,PO8,PO9,PO10,PO12 PSO1,
PSO2
DEPARTMENT OF ELECTRONICS AND COMMUNICATION ENGINEERING JSS ACADEMY OF TECHNICAL EDUCATION
JSS Campus, Uttarahalli-Kengeri Main Road, Bangalore - 560060.
GROUP USN NAME TOPIC
1
1JS17EC074 POOJA C A
Implement Triple DES algorithm to encrypt N bit data
1JS17EC093 SAUDAMINI V
1JS17EC096 SHASHANK PRAKASH
1JS17EC105 SHRINIDHI J N
1JS17EC113 TANAYA MEHTA
2
1JS17EC073 SAI SPARSHA PRASAD
Implement RSA algorithm to encrypt N bit data
1JS17EC075 POORVI PAI
1JS17EC103 SHRUTHI K
1JS17EC104 SNEHA DATTA
1JS17EC107 SUKRUTHI A
1JS17EC119 VAISHNAVI SRIKANTH
3
1JS17EC071 PAVAN G R
Implement Blowfish algorithm to encrypt N bit data
1JS17EC080 PRIYA R
1JS17EC082 PUNITH P
1JS17EC085 RASHMI C
1JS17EC090 SAMPADA D D
1JS17EC098 SHOBITHA T R
4
1JS17EC079 PRATHIKSHA R V
Implement Twofish algorithm to encrypt N bit data
1JS17EC101 SHRILAXMI DIXIT
1JS17EC108 SUMEDHA C
1JS17EC110 SUPRADA H S
5
1JS17EC064 N S ABHISHEK
Implement AES algorithm to encrypt N bit data
1JS17EC065
MOHAMMAD
EKRAMAH
1JS17EC089 SAHIL AGARWAL
1JS17EC091 SAMYAK JAIN
1JS17EC109 SUMITH KUMAR
1JS17EC114 TATHYA GROVER
6
1JS17EC069 NISCHAY M
Implement LZW data compression algorithm
1JS17EC087 RISHABH RANJAN
1JS17EC120 VARUN MORE
1JS17EC411 KARTHIK
1JS18EC420 SRIRAMULU
7
1JS17EC076 PRAJWAL GATGE Implement Huffman data compression algorithm
1JS17EC078 PRAJYOTH KULKARNI
1JS17EC112 SYED UZAIR
1JS17EC417 NIRANJAN
1JS17EC430 YASIN
1JS18EC425 ZAHEER PASHA
8
1JS17EC095 SHASHANK M
Implement DEFLATE data compression algorithm
1JS17EC102 SHRINIDHI KALLAPUR
1JS17EC111 SYED ASIF
1JS17EC122 VENU M
1JS16EC425 VINOD
9
1JS17EC072 PAVAN S M
Implement MTF data compression algorithm
1JS17EC081 PRUTHVI RAJ N
1JS17EC092 SANTOSH BATI
1JS17EC106 SUHAS GOWDA C R
1JS17EC118 V ARAVINDH KUMAR
1JS17EC121 VARUN S PUTHRAN
10
1JS17EC115 TEJAS B
Implement BWT data compression algorithm
1JS17EC117 THIRUMALESH B
1JS17EC123
VIVEK SANJEEV
POOJARI
1JS17EC124 VIVEKANANDA G
1JS17EC125 YASHAS K
1JS15EC042 KIRAN KUMAR L
11
1JS17EC067 NEHA K G
Design and implement traffic light controller
1JS17EC068 NIHARIKA
1JS17EC070 NISHA M
1JS17EC077 PRAJWA OM PRAKASH
1JS17EC407 CHINNMAI
1JS16EC052 NAMRATHA
12
1JS17EC066 NAVYA R
Design and implement Car parking system
1JS17EC086 RESHMA
1JS17EC097 SHEETAL C
1JS18EC413 MEENAKSHI B C
1JS18EC419 SHWETHA M
1JS18EC424 YASHASWINI H N
JSS MAHAVIDYAPEETHA
JSS ACADEMY OF TECHNICAL EDUCATION DEPARTMENT OF ELECTRONICS AND COMMUNICATION
ENGINEERING JSSATE Campus, Dr. Vishnuvardhan Main Road, Bangalore – 560 060
Innovative Teaching
Subject Name/Code: COMPUTER ORGANIZATION AND ARCHITECTURE /18EC35
Semester/Section: 3th/A
Semester Duration: Aug 2019-Jan 2020
AY: 2019-2020
Faculty Name: Dr. Mallikarjunaswamy S
Innovative Teaching methods
Method Activity Indicate with Tick mark
M1 SIMULATION ✓
M2 Activity based Learning (Circuit Ideas & its
implementation)
M3 Flip-Mode (Circulate Video & Audio material in
advance & discuss the related topics in the class)
M4 Case Studies ✓
M5 Teaching concepts through Animation ✓
SL.NO Topic for
teaching
Activity to
students
COs POs PSOs Bloom’s
level
CO
attainment
Level
1 Memory
storage
analysis using
android app
Collaborative
learning: to
simulate
memory
mapping
Technics
C205.1 PO5 PSO2,
PSO3
L3 1
2 Case Studies:
- C205.2 PO3 PSO1 L4 -
3 Animation:
Videos to
demonstrate
the clock
cycles
Voltage
- C205.3
C205.4
PO2,
PO3,
PO5
PSO1,
PSO3
L4 -
Inference:
Through collaborative learning students could work in team and individual level to
solve the problem mentioned in activity, submit a report and present the topic in the
class.
0
5
10
15
20
25
30
35
40
45
50
Excellent Very Good Good Satisfactory Poor
Stu
den
ts
Grade
Feedback Analysis
JSS MAHAVIDYAPEETHA JSS ACADEMY OF TECHNICAL EDUCATION
DEPARTMENT OF ELECTRONICS AND COMMUNICATION ENGINEERING JSSATE Campus, Dr. Vishnuvardhan Main Road, Bangalore – 560 060
Innovative Teaching
Subject Name/Code: Verilog HDL/17EC53
Semester/Section: 5th/A
Semester Duration: Aug 2019-Jan 2019
Academic Year: 2019-2020
Faculty Name: Sunita Shirahatti
Innovative Teaching methods
Method Activity Indicate with Tick mark
M1 SIMULATION ✓
M2 Activity based Learning (Collaborative learning &
implementation of given problem statement)
✓
M3 Flip-Mode (Circulate Video & Audio material in
advance & discuss the related topics in the class)
M4 Case Studies
M5 Teaching concepts through Animation
Inference:
Through collaborative learning students could work in team and individual level to
implement, Simulate and Synthesize the problem statement mentioned in activity,
submit a report and present the topic in the class.
SL.NO Topic for
teaching
Activity to
students
COs POs PSOs Bloom’s
level
CO
attain
ment
Level
1 Simulation:
Simulation
of Digial
Circuits
and
applications
Collaborativ
e learning: to
simulate and
synthesize
various
digital
arithmetic
circuits
using
modern tool
C303.5 PO1, PO2, PO3,
PO4,PO5, PO8,
PO9, PO10,
PO12
PSO2,
PSO3
L3 1
Collaborative learning topics
Sr.No USN Name Topic
Marks
1 1JS17EC002 ABHIJNA YAJI
32 bit carry look ahead
adder
5
2 1JS17EC004 ACHUTH M
5
3 1JS17EC013 ANANYA S ACHAR
5
4 1JS17EC057 MAHAAN KN
5
5 1JS17EC016 ANISHA MARIA D SILVA
5
6 1JS17EC003 ABHIRAM M S
32 bit floating point
divider
5
7 1JS17EC021 ASHIK J SHETTY
5
8 1JS17EC026 CHANDAN B NOOLI
5
9 1JS17EC035 GANESH GOWTAM
5
10 1JS17EC042 HRISHIKESH MASHALKAR
5
11 1JS17EC051 KRUTHIK N
5
12 1JS17EC008 AKASH C
32 bit floating point
adder
5
13 1JS17EC022 ASHWIN SHARMA P
5
14 1JS17EC029 CHIDANANDA L P
5
15 1JS17EC038 HARSHA N
5
16 1JS17EC005 ACHYUT S KULKARNI
5
17 1JS17EC006 ADITHYA .S. JOSHI
5
18 1JS16EC066 SANDEEP P V
32 bit parallel multiplier
5
19 1JS17EC402 AJAYKUMAR V
5
20 1JS17EC403 AMIT M
5
21 1JS16EC025 GAGAN K
5
22 1JS17EC018 ANKIT PANDA
32 bit carry skip adder
4
23 1JS17EC023 BADAL
4
24 1JS17EC062 MEHRAJ UD DIN BHAT
4
25 1JS17EC063 MISHAN KUMAR 4
26 1JS17EC015 ANISH PRAKASH
4
27 1JS17EC017 ANKIT CHAND
4
28 1JS17EC032 DIVYA SRI R
32 bit carry save adder
5
29 1JS17EC041 HITHASHREE J
5
30 1JS17EC060 MARIA NUZHATH SUBHANI
5
31 1JS17EC011 ANANYA LN SIMHA
5
32 1JS17EC033 EERA BALCHANDANI
32 bit parallel prefix
adder
5
33 1JS17EC055 M MADHURI
5
34 1JS17EC012 ANANYA R
5
35 1JS17EC019 ANKITHA S BANGAR
5
36 1JS17EC028 CHETHANA S R
5
37 1JS17EC039 HAVISH MANIKYA VAKKALANKA
32 bit Multiply and Add
unit
5
38 1JS17EC046 JEEVAN K
5
39 1JS17EC009 AMAN SIDDAPPA RAMAGONATTI
5
40 1JS17EC025 BHARGAV KODALI
5
41 1JS17EC054 LINGARAJ
5
42 1JS17EC050 KRISHNA PRASAD B S
32 bit Booth multiplier
5
43 1JS17EC056 MADHAN KUMAR Y K
5
44 1JS17EC024 BHARATH N S
5
45 1JS17EC030 DILIPKUMAR MV
5
46 1JS17EC031 DIVITH SIDDU
5
47 1JS17EC043 HRUSHIKESH K N
5
48 1JS17EC061 MEGHANA M
32 bit serial multiplier
5
49 1JS17EC020 ANUPRASAD R
5
50 1JS17EC027 CHANDANA L V
5
51 1JS17EC045 JAYASHREE P
5
52 1JS17EC052 L ASHWINI
5
53 1JS17EC058 MANASI S
5
54 1JS17EC034 EKTA SINGH
Design and implement
traffic light controller
5
55 1JS17EC037 HARIKRISHNA V SHETTY
5
56 1JS17EC059 MANISH KUMAR SINGH
5
57 1JS18EC400 ABHISHEKANAND N KASHYAP
5
58 1JS17EC040 HIMANSHU K JAISWAL
5
59 1JS18EC410 DEEPAK S
Design and implement
Car parking system
5
60 1JS18EC404 ASHWINI K
5
61 1JS18EC407 CHANDANA K
5
62 1JS18EC401 ABHISHEK M
5
63
NAVYAKANTH B C
5
JSS MAHAVIDYAPEETHA JSS ACADEMY OF TECHNICAL EDUCATION
DEPARTMENT OF ELECTRONICS AND COMMUNICATION ENGINEERING JSSATE Campus, Dr. Vishnuvardhan Main Road, Bangalore – 560 060
IMPACT ANALYSIS
Activity: Collaborative Learning Date: 20TH & 21ST Nov, 2019
Semester: V ‘A’ Sec Branch: EC
Subject Name: Verilog HDL Subject Code: 17EC53
Subject Faculty: SUNITA SHIRAHATTI
CO Covered: C303.5
C303.5 Analyze and implement digital systems using HDL. L4
Objectives: Students should be able to
• Analyze, design and implement given digital arithmetic circuits using verilog
HDL.
• Work in team and improve the oral / written communication skills.
No. of
Students
Attended
Marks scored/Grade
Attainment PO’s Mapped
PSO’s
Mapped
No. of
students
who
scored
5M
No. Of
students
who
scored
4M
No. Of
students
who
scored
3M
No. Of
students
who
scored
<=2 M
63 57 6 - - PO1,PO2,PO3,PO4,PO5,PO8,PO9,PO10,PO12 PSO1,
PSO2
Faculty In-charge
No. ofstudents who
scored 5M
No. Ofstudents who
scored 4M
No. Ofstudents who
scored 3M
No. Ofstudents who
scored <=2
Series1 57 6
0
10
20
30
40
50
60
NU
MB
ER O
F ST
UD
ENTS
COLLABORATIVE LEARNING
JSS MAHAVIDYAPEETHA JSS ACADEMY OF TECHNICAL EDUCATION
DEPARTMENT OF ELECTRONICS AND COMMUNICATION ENGINEERING JSSATE Campus, Dr. Vishnuvardhan Main Road, Bangalore – 560 060
WEAK STUDENT IMPACT ANALYSIS
Semester: V ‘A’ Sec Branch: EC
Subject Name: Verilog HDL Subject Code: 17EC53
Subject Faculty: SUNITA SHIRAHATTI
Program level weak students list(before It IA)
SL no
USN Name IA 1 IA 2 IA 3 AVERAGE
1 1JS16EC025 Gagan K 24 4 19 26
2 1JS17EC005 Achyut S Kulkarni 22 12 22 29
3 1JS17EC019 Ankitha S Bangar 20 22 25 33
4 1JS17EC023 Badal 11 5 19 21
5 1JS17EC034 Ekta Singh 25 23 25 35
6 1JS17EC035 Ganesh Gowtam 21 26 22 33
7 1JS17EC040 Himanshu K Jaiswal 23 15 19 29
8 1JS17EC046 Jeevan K 22 5 17 25
9 1JS17EC054 Lingaraj 21 16 23 30
10 1JS17EC059 Manish Kumar Singh 20 23 21 32
11 1JS17EC063 Mishan Kumar 14 8 6 19
12 1JS18EC400 Abhishekanand N Kashyap 21 15 8 25
13 1JS18EC404 Ashwini K 29 19 13 31
14 1JS18EC410 Deepak S 22 11 9 24
IMPACT ANALYSIS 02/14 09/14 5/14 0/14
Faculty In-charge
weak students list after 1st IA
SL no
USN Name IA 1 IA 2 IA 3 AVERAGE
1 1JS17EC023 Badal 11 5 19 21
2 1JS17EC063 Mishan Kumar 14 8 6 19
3 1JS16EC006 Aditya Joshi 7 25 20 28
4 1JS16EC009 Aman Siddappa Ramagond 16 15 19 27
5 1JS16EC018 Ankit Panda 17 13 12 23
6 1JS16EC026 Chandan Nooli 11 14 17 24
7 1JS16EC029 Chidananda L P 17 17 20 28
8 1JS16EC038 Harsha N AB AB 22 19
9 1JS17EC403 Ameeta kumar 11 7 12 17
weak students list after 2nd IA
SL no
USN Name IA 1 IA 2 IA 3 AVERAGE
1JS16EC025 Gagan K 24 4 19 26
1JS17EC005 Achyut S Kulkarni 22 12 22 29
1 1JS16EC009 Aman Siddappa Ramagond 16 15 19 27
2 1JS16EC013 Ananya Achar 19 10 14 25
4 1JS16EC018 Ankit Panda 17 13 12 23
1JS16EC021 Ashik Shetty 24 16 20 30
5 1JS17EC023 Badal 11 5 19 21
1JS16EC026 Chandan Nooli 11 14 17 24
6 1JS16EC029 Chidananda L P 17 17 20 28
8 1JS16EC038 Harsha N AB AB 22 19
1JS17EC063 Mishan Kumar 14 8 6 19
9 1JS17EC403 Ameeta kumar 11 7 12 17
Innovative Teaching
Faculty Name : Dr Thejaswini P Sem/Sec : 5B
Subject : Verilog HDL Subject Code : 17EC53
Sem Duration: Aug 2019-Jan 2019 Academic Year: 2019-2020 Total strength : 67 number of students feedback: 67
Innovative Teaching methods
Method Activity Indicate with Tick mark
M1 SIMULATION ✓
M2 Activity based Learning (Collaborative learning &
implementation of given problem statement)
✓
M3 Flip-Mode (Circulate Video & Audio material in
advance & discuss the related topics in the class)
M4 Case Studies
M5 Teaching concepts through Animation
Inference:
Through collaborative learning students could work in team and individual level to
implement, Simulate and Synthesize the problem statement mentioned in activity, submit a
report and present the topic in the class.
DEPARTMENT OF ELECTRONICS AND COMMUNICATION ENGINEERING JSS ACADEMY OF TECHNICAL EDUCATION
JSS Campus, Uttarahalli-Kengeri Main Road, Bangalore - 560060.
SL.NO Topic for
teaching
Activity to
students
COs POs PSOs Bloom’s
level
CO
attain
ment
Level
1 Simulation:
Simulation
of Digial
Circuits and
applications
Collaborative
learning: to
simulate and
synthesize
various digital
arithmetic
circuits using
modern tool
C303.5 PO1, PO2, PO3,
PO4,PO5, PO8,
PO9, PO10, PO12
PSO2,
PSO3
L3 1
CO Covered: C303.5
C303.5 Analyze and implement digital systems using HDL. L4
Objectives: Students should be able to
• Analyze, design and implement given digital arithmetic circuits using verilog HDL.
• Work in team and improve the oral / written communication skills.
No. of
Students
Attended
Marks scored/Grade
Attainment PO’s Mapped
PSO’s
Mapped
No. of
students
who
scored
5M
No. Of
students
who
scored
4M
No. Of
students
who
scored
3M
No. Of
students
who
scored
<=2 M
63 57 6 - - PO1,PO2,PO3,PO4,PO5,PO8,PO9,PO10,PO12 PSO1,
PSO2
DEPARTMENT OF ELECTRONICS AND COMMUNICATION ENGINEERING JSS ACADEMY OF TECHNICAL EDUCATION
JSS Campus, Uttarahalli-Kengeri Main Road, Bangalore - 560060.
GROUP USN NAME TOPIC
1
1JS17EC074 POOJA C A
Implement Triple DES algorithm to encrypt N bit data
1JS17EC093 SAUDAMINI V
1JS17EC096 SHASHANK PRAKASH
1JS17EC105 SHRINIDHI J N
1JS17EC113 TANAYA MEHTA
2
1JS17EC073 SAI SPARSHA PRASAD
Implement RSA algorithm to encrypt N bit data
1JS17EC075 POORVI PAI
1JS17EC103 SHRUTHI K
1JS17EC104 SNEHA DATTA
1JS17EC107 SUKRUTHI A
1JS17EC119 VAISHNAVI SRIKANTH
3
1JS17EC071 PAVAN G R
Implement Blowfish algorithm to encrypt N bit data
1JS17EC080 PRIYA R
1JS17EC082 PUNITH P
1JS17EC085 RASHMI C
1JS17EC090 SAMPADA D D
1JS17EC098 SHOBITHA T R
4
1JS17EC079 PRATHIKSHA R V
Implement Twofish algorithm to encrypt N bit data
1JS17EC101 SHRILAXMI DIXIT
1JS17EC108 SUMEDHA C
1JS17EC110 SUPRADA H S
5
1JS17EC064 N S ABHISHEK
Implement AES algorithm to encrypt N bit data
1JS17EC065
MOHAMMAD
EKRAMAH
1JS17EC089 SAHIL AGARWAL
1JS17EC091 SAMYAK JAIN
1JS17EC109 SUMITH KUMAR
1JS17EC114 TATHYA GROVER
6
1JS17EC069 NISCHAY M
Implement LZW data compression algorithm
1JS17EC087 RISHABH RANJAN
1JS17EC120 VARUN MORE
1JS17EC411 KARTHIK
1JS18EC420 SRIRAMULU
7
1JS17EC076 PRAJWAL GATGE Implement Huffman data compression algorithm
1JS17EC078 PRAJYOTH KULKARNI
1JS17EC112 SYED UZAIR
1JS17EC417 NIRANJAN
1JS17EC430 YASIN
1JS18EC425 ZAHEER PASHA
8
1JS17EC095 SHASHANK M
Implement DEFLATE data compression algorithm
1JS17EC102 SHRINIDHI KALLAPUR
1JS17EC111 SYED ASIF
1JS17EC122 VENU M
1JS16EC425 VINOD
9
1JS17EC072 PAVAN S M
Implement MTF data compression algorithm
1JS17EC081 PRUTHVI RAJ N
1JS17EC092 SANTOSH BATI
1JS17EC106 SUHAS GOWDA C R
1JS17EC118 V ARAVINDH KUMAR
1JS17EC121 VARUN S PUTHRAN
10
1JS17EC115 TEJAS B
Implement BWT data compression algorithm
1JS17EC117 THIRUMALESH B
1JS17EC123
VIVEK SANJEEV
POOJARI
1JS17EC124 VIVEKANANDA G
1JS17EC125 YASHAS K
1JS15EC042 KIRAN KUMAR L
11
1JS17EC067 NEHA K G
Design and implement traffic light controller
1JS17EC068 NIHARIKA
1JS17EC070 NISHA M
1JS17EC077 PRAJWA OM PRAKASH
1JS17EC407 CHINNMAI
1JS16EC052 NAMRATHA
12
1JS17EC066 NAVYA R
Design and implement Car parking system
1JS17EC086 RESHMA
1JS17EC097 SHEETAL C
1JS18EC413 MEENAKSHI B C
1JS18EC419 SHWETHA M
1JS18EC424 YASHASWINI H N
JSS MAHAVIDYAPEETHA
JSS ACADEMY OF TECHNICAL EDUCATION DEPARTMENT OF ELECTRONICS AND COMMUNICATION
ENGINEERING JSSATE Campus, Dr. Vishnuvardhan Main Road, Bangalore – 560 060
Innovative Teaching
Subject Name/Code: Digital Image Processing/15EC72
Semester/Section: 7th/B
Semester Duration: Aug 2019-Jan 2020
AY: 2019-2020
Faculty Name: Dr. P.M.Shivakumara swamy
Innovative Teaching methods
Method Activity Indicate with Tick mark
M1 SIMULATION ✓
M2 Activity based Learning (Circuit Ideas & its
implementation)
M3 Flip-Mode (Circulate Video & Audio material in
advance & discuss the related topics in the class)
M4 Case Studies
M5 Teaching concepts through Animation ✓
Inference:
Through collaborative learning students could work in team and individual level to
solve the problem mentioned in activity, submit a report and present the topic in the
class.
SL.NO Topic for
teaching
Activity to
students
COs Pos PSOs Bloom’s
level
CO
attainment
Level
1 Simulation:
Simulation of
Image
processing
algorithms
Collaborative
learning: to
simulate
Various Image
processing
algorithms
using modern
tool
CO4 PO5 PSO2,
PSO3
L3 1
2 Animation:
Wavelet
transform
- CO3 PO1,
PO2,
PO3
PSO1,
PSO3
L3 -
Feed Back
0
10
20
30
40
50
60
Excellent Very Good Good Satisfactory Poor
Students
Students