SKKUISDL 1

Cadence Environment Setup

Integrated Systems Design Lab.Semiconductor Bldg. 400425

Bai-Sun Kong(bskong@skku.edu)

SKKUISDL 2

Connect to server

1. Move to “http://sgd.semi.skku.edu” and Login

2. ID & Password are the same as of Semi Web (semi.skku.edu)

If you have a problem with login, please contact to “ 시스템관리실”3. Click Terminal(Solaris)

”

SKKUISDL 3

Initial setup

1. In your terminal, execute “gedit .cshrc”

2. Modify your file following the example and save.

SKKUISDL 4

Initial setup

1. Execute “source .cshrc”

2. Execute “cp –rf /semihome/homedir/101/10122/gpdk180 ./” ( “./” means the current directory)

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Run simulation tool

1. Execute “cd gpdk180” and “virtuoso &” * “&” makes the command run in the background

Must run simulation tool in “gpdk180” folder!!!

2. Go to library manager. “ Tools Library Manager ”

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Make new library

Make library. “ File New Library ”

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Make new library

1. Write name “ test ”

2. Click “OK”

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Make new library

1. Select “Attach to an existing technology library” and click “OK”

2. Select “gpdk180” and click “OK”

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Make new cell

1. Check “test” library

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Make new cell

Write cell name “test” and click “OK”.

SKKUISDL 11

Make new cell

Schematic Editor

SKKUISDL 12

“I” key “Browse” “gpdk180” choice device symbol

NMOS nmos

PMOS pmos

Add instance

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“I” key “Browse” “analogLib” choice device symbol

Voltage source vdc

Current source idc

Supply voltage vddGround gnd

Resistor res

Add instance

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Set properties

1. Click NMOS

2. “q” key Properties

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Set properties

1. Click voltage source

2. “q” key Properties

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Draw circuit

1. Draw circuit

2. Set properties

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Add wire name

1. “l” key (label)

2. Write wire names

3. Click “Hide”

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Add wire name

1. Click wires

2. Wire names added

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Add wire name

1. “l” key (label)

2. Write wire names

3. Click “Hide”

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Add wire name

1. Click wires

2. Wire names added

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Add wire name

label make connection between wires in netlist

SKKUISDL 22

Check and save

SKKUISDL 23

Launch analog environment

“Launch ADE L”

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Setup model library

1. Check model library “Setup Model Libraries …”

2. Select stat “NN” and click “OK”

* Process corners : [NMOS][PMOS], N : normal, S : slow, F: fast)

SKKUISDL 25

Setup variables

“Variables Copy From Cellview”

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Setup design variables

1. Click variable and “Variables Edit”

2. Write value and click “OK”

SKKUISDL 27

Setup outputs

“Outputs To Be Plotted Select On Schematic”

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Setup outputs

1. Move mouse to output wire

2. Click the wire

3. “Esc” key

4. Check output in analog environment

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Setup outputs (additional)

1. Move mouse to output node

2. Click the node

3. “Esc” key

4. Check output (current) in analog environment

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Setup DC analyses

Click the button

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Setup DC analyses

1. Select “dc”

2. Check “Save DC Operating Point”

3. Check “Design Variable”

4. Click “Select Design Variable” and select input

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Setup DC analyses

1. Write “Start” value and “Stop” value

2. Select Sweep Type “Linear”

3. write “Step Size” value

4. Click “OK”

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Simulate DC analyses

“Netlist and Run”

SKKUISDL 34

Simulate DC analyses

Input-output characteristic graph

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Result of DC Operating Points

1. “Result Print DC Operating Points”

2. Click device on schematic

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Simulate AC analyses

1. Setup dc input voltage for saturation

2. Disable DC analyses

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Simulate AC analyses

1. Write “AC magnitude”

and “AC phase”

2. Check and save

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Simulate AC analyses

1. Go to analyses and select “ac”

2. Write “Start” frequency and “Stop” frequency

3. Select Sweep Type “Logarithmic”

4. Write “Points Per Decade” value

5. Click “OK”

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Simulate AC analyses

Netlist and Run

SKKUISDL 40

Simulate AC analyses

Frequency-gain graph

SKKUISDL 41

Simulate time analyses

1. Return to schematic

2. Click the voltage source and remove it with “delete” key

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Simulate time analyses

1. Add instance “vsin” by “i” key

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Simulate time analyses

1. Click instance and “q” key

2. Write

DC voltageAmplitudeFrequency

3. Click “OK”

4. Don’t forget check and save

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Simulate time analyses

1. Disable ac analyses and click choose analyses button

2. Select “tran”

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Simulate time analyses

1. Write “Stop Time”

2. Select Accuracy Defaults “moderate”

3. Click “OK”

SKKUISDL 46

Simulate time analyses

Netlist and Run

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Simulate time analyses

Time-output graph