Paulo Moreira Introduction 1

Outline

• Introduction• Transistors

– DC behaviour– MOSFET capacitances– MOSFET model

• The CMOS inverter• Technology• Scaling• Gates• Sequential circuits• Storage elements• Phase-Locked Loops• Example

Paulo Moreira Introduction 2

“Making Logic”

• Logic circuit “ingredients”:– Power source– Switches– Inversion– Power gain

• Power always comes from some form of external EMF generator.

• NMOS and PMOS transistors:– Can perform the last three

functions– They are the building blocks

of CMOS technologies!

Paulo Moreira Introduction 3

Silicon switches: the NMOS

Channel doping:• 0.13 µm technology• ~1017 atoms/cm3

BoronArsenic

&Phosphorous

Paulo Moreira Introduction 4

Silicon switches: the NMOS

Above silicon:• Thin oxide (SiO2) under the gate areas;• Thick oxide everywhere else;

Paulo Moreira Introduction 5

Silicon switches: the PMOS

Paulo Moreira Introduction 6

MOSFET equations• Cut-off region:

• Linear region:

• Saturation:

• Oxide capacitance

• Process “transconductance”

Ids Vgs VT= − <0 0 for

( ) ( )Ids CoxW

LVgs VT Vds

Vds Vds Vds Vgs VT= ⋅ ⋅ ⋅ − ⋅ − ⋅ + ⋅ < < −

µ λ2

21 0 for

( ) ( )IdsCox W

LVgs VT Vds Vds Vgs VT=

⋅⋅ ⋅ − ⋅ + ⋅ > −

µλ

22

1 for

( )Coxox

tox=ε

F / m2

( )µµ ε

⋅ =⋅

Coxox

tox A / V2

0.24µm process

tox = 5 nm (~10 atomic layers)

Cox = 5.6 fF/µm2

(1)

(2)

(3)

Paulo Moreira Introduction 7

MOS output characteristics

• Linear region:Vds<Vgs-VT

– Voltage controlled resistor

• Saturation region:Vds>Vgs-VT

– Voltage controlled current source

• Curves deviate from the ideal current source behavior due to:– Channel modulation

effects

Paulo Moreira Introduction 8

MOS output characteristicsL = 240nm, W = 480nm

0

50

100

150

200

250

0 0.5 1 1.5 2 2.5Vds [V]

Ids

[uA

]

Vgs = 0.7V (< Vt)Vgs = 1.3VVgs = 1.9VVgs = 2.5V

Paulo Moreira Introduction 9

MOS output characteristicsL = 24um, W = 48um

0

50

100

150

200

250

300

350

400

0 0.5 1 1.5 2 2.5

Vds [V]

Ids

[uA

]

Vgs = 0.7V (<Vt)Vgs = 1.3VVgs = 1.9VVgs = 2.5V

Paulo Moreira Introduction 10

Is the quadratic law valid?Ids - Vgs (Vds = 2.5V, Vbs = 0V)

0

100

200

300

400

500

600

0 0.5 1 1.5 2 2.5Vgs [V]

Ids

[uA

]

L = 24um, W = 48um

L = 2.4um, W = 4.8um

L = 240nm, W = 480nm

Quadratic law “valid” for long channel devices only!

Paulo Moreira Introduction 11

Bulk effect• The threshold depends on:

– Gate oxide thickness– Doping levels– Source-to-bulk voltage

• When the semiconductor surface inverts to n-type the channel is in “strong inversion”

• Vsb = 0 ⇒ strong inversion for:– surface potential > -2φF

• Vsb > 0 ⇒ strong inversion for:– surface potential > -2φF + Vsb

n+ n+p+

V>0 V>VT0

n+ n+p+

V=0 V=VT0

Paulo Moreira Introduction 12

Bulk effect

0

100

200

300

400

500

600

0 0.5 1 1.5 2 2.5

Vgs [V]

Ids

[uA

]

L = 24um, W = 48um, Vbs = 1

L = 24um, W = 48um, Vbs = -1V

W = 24µm

L = 48µm

Vsb = 0V

Vsb = 1 V

Paulo Moreira Introduction 13

Weak inversion• Is Id=0 when Vgs<VT?• For Vgs<VT the drain current

depends exponentially on Vgs

• In weak inversion and saturation (Vds > ~150mV):

where

• Used in very low power designs• Slow operation

I WL

I ed do

q Vn k T

gs

≅ ⋅ ⋅⋅

⋅ ⋅

TknVq

do

T

eI ⋅⋅⋅

−=

Paulo Moreira Introduction 14

Gain & Inversion• Gain:

– Signal regeneration at every logic operation

– “Static” flip-flops– “Static” RW memory cells

• Inversion:– Intrinsic to the common-

source configuration• The gain cell load can be:

– Resistor– Current source– Another gain device (PMOS)

Paulo Moreira Introduction 15

Outline

• Introduction• Transistors

– DC behaviour– MOSFET capacitances– MOSFET model

• The CMOS Inverter• Technology Scaling• Gates• Sequential circuits• Storage elements• Phase-Locked Loops• Example

Paulo Moreira Introduction 16

What causes delay?

VIN

0

Vdd

t

VOUT

0

Vdd

t

50% leveldelay

CVINVGS

I (VGS-VT)2

Ideal MOS• In MOS circuits capacitive loading is the main cause. (RC delay in the interconnects will be addressed latter)

• Capacitance loading is due to:– Device capacitance– Interconnect capacitance

WL

VCC

IVCt

ddox⋅

⋅⋅≈

∆⋅=∆

µ

Assuming VT = 0

Paulo Moreira Introduction 17

MOSFET capacitances

• MOS capacitances have three origins:– The basic MOS structure– The channel charge– The pn-junctions depletion regions

Source Drain

Gate

CSB CDB

CGB

Bulk

CGS CGD

Paulo Moreira Introduction 18

MOS structure capacitances

• Source/drain diffusion extend below the gate oxide by:xd - the lateral diffusion

• This gives origin to the source/drain overlap capacitances:

• Gate-bulk overlap capacitance:

C C C WC

gso gdo o

o

= = × (F / m)

C C L Cgbo o o= ×' ', (F / m)

L

Source Source

Gate-bulkoverlap

Gate

W

xd xd

Leff

tox

Cgso Cgdo

G/S overlap G/D overlap

Source/Drain

Overlap OverlapCgbo/2

Weff

Paulo Moreira Introduction 19

MOS structure capacitances

0.24 µm process

NMOSL(drawn) = 0.24 µmL(effective) = 0.18 µmW(drawn) = 2 µmCo (s, d, b) = 0.36 fF/µmCox = 5.6 fF/µm2

Cgso = Cgdo = 0.72 fFCgbo = 0.086 fF

Cg = 2.02 fF

Paulo Moreira Introduction 20

Channel capacitance

Operation region Cgb Cgs Cgd

Cutoff Cox W L 0 0

Linear 0 (1/2) Cox W L (1/2) Cox W L

Saturation 0 (2/3) Cox W L 0

• The channel capacitance is nonlinear• Its value depends on the operation region• Its formed of three components:

Cgb - gate-to-bulk capacitanceCgs - gate-to-source capacitanceCgd - gate-to-drain capacitance

Paulo Moreira Introduction 21

Channel capacitance

Cg = Weff × Leff × Cox

Cg + Cgbo

2/3 Cg + Cgso

Gate-to-bulk

1/2 Cg + Cgbo

Cgdo , Cgso

Cgbo

Gate-to-source

Gate-to-drain

Off Saturated Linear

Paulo Moreira Introduction 22

Junction capacitances

• Csb and Cdb are diffusion capacitances composed of:– Bottom-plate capacitance:

– Side-wall capacitance:C C W Lbottom j s= ⋅ ⋅

( )C C L Wsw jsw s= ⋅ +2

Side wall Bottom plate

Xj

W

Channel

Channel-stopimplant

Ls

Paulo Moreira Introduction 23

Junction capacitances

0.24 µm process

NMOSL(drawn) = 0.24 µmL(effective) = 0.18 µmW(drawn) = 2 µmLs = 0.8 µmCj (s, d) = 1.05 fF/µm2

Cjsw = 0.09 fF/µm

Cbottom = 1.68 fFCsw = 0.32 fF

Cg = 2.02 fF

Paulo Moreira Introduction 24

Source/drain resistance

• Scaled down devices ⇒ higher source/drain resistance:

• In sub-µ processes silicidation is used to reduce the source, drain and gate parasitic resistance

RLW

R Rs ds d

sq c,,= ⋅ +

Sourcecontact

Draincontact

Ld Ls

0.24 µm process

R (P+) = 4 Ω/sqR (N-) = 4 Ω/sq

Paulo Moreira Introduction 25

Outline

• Introduction• Transistors

– DC behaviour– MOSFET capacitances– MOSFET model

• The CMOS inverter• Technology Scaling• Gates• Sequential circuits• Storage elements• Example

Paulo Moreira Introduction 26

Ultra simplified MOSFET model• Here it is an almost “simplistic” model of the MOSFET that will help you to

easily follow the remaining material.• The MOS transistor “is” a capacitor whose voltage controls the passage of

current between two nodes called the source and the drain.• One of the electrodes of this capacitor is called the gate, the other the

source.• The “way” the current flows between the source and the drain depends on

the gate-to-source voltage (Vgs) and on the drain-to-source voltage (Vds).

VdsVgs

Ids

Vgs VdsIdsCgsG

D

S S S S

DG

Paulo Moreira Introduction 27

Ultra simplified MOSFET model• If the gate-to-source voltage (Vgs) is less than a certain voltage, called the

threshold voltage (Vth), no current flows in the drain circuit no matter what the drain-to-source voltage (Vds) is!

• This is the actual definition of threshold voltage Vth.• That is, Ids = 0 for Vgs < Vth

• This is the same as saying that the drain circuit is an infinite impedance (an open circuit)!

VdsVgs

Ids

Vgs VdsZ=∞CgsG

D

S S S S

DG

Paulo Moreira Introduction 28

Ultra simplified MOSFET model• If the gate-to-source voltage (Vgs) is bigger than the threshold voltage (Vth)

and the drain-to-source voltage (Vds) is bigger than Vgs – Vth then the drain current only depends on the gate overdrive voltage (Vgs – Vth)

• That is, the drain circuit behaves as an “ideal” voltage controlled current source:

( )22 TVgsVL

WoxCdsI −⋅⋅

⋅=µ

VdsVgs

Ids

Vgs VdsICgsG

D

S S S S

DG Ids

Paulo Moreira Introduction 29

Ultra simplified MOSFET model• If the gate-to-source voltage (Vgs) is bigger than the threshold voltage (Vth)

and the drain-to-source voltage (Vds) is smaller than Vgs – Vth then the drain current depends both on the gate overdrive voltage (Vgs – Vth) and the drain- to- source voltage (Vds)

• That is, the drain circuit behaves as a voltage controlled resistor:

( ) dsVTVgsVL

WoxCdsI ⋅−⋅⋅⋅= µ

VdsVgs

Ids

Vgs Vds

Ids

CgsG

D DG

R

Paulo Moreira Introduction 30

Ultra simplified MOSFET model

• For PMOS transistors the same concepts are valid except that:– All voltages are negative (including Vth)– Were we used bigger than you should use smaller than– The drain current actually flows out of the transistor

instead of into the transistor.• REMEMBER!

– This is an almost ‘simplistic’ model of the device!• However, it will allow us to understand

qualitatively the behaviour of CMOS logic circuits!– Even some conclusions will be based on such a simple

model.