Asawari 2012

By Asawari Dudwadkar By Asawari Dudwadkar Dept. of Electronics Dept. of Electronics

VESITVESIT

IC 8253 is popularly known as “Programmable Interval Timers IC (PITs).”

Why it is referred as “PITs”?

IC 8253 / 8254 is used as a:

1. COUNTER.2. TIMER.

Why to use 8253? conventional method of doing the same thing?

Advantages of using 8253?

Earlier Applications.

Asawari 2012

• FEATURES OF PITs:

1. There are 3 independent 16 bit down counter.2. Programmable counter modes.3. Counting facility in both Binary & BCD.4. Compatible with 8085.5. 24 pin DIP.6. Single +5v supply.7. For 8253 2MHz frequency range & for 8254 10MHz.

IC 8253 IC 8254

1. DC to 2.6 MHZ 1. DC to 10MHz

2. Uses N=MOS technology. 2. Uses H-MOS technology

3. Read back command not available

3. Read Back command available

4. Read and Write of same counter cannot be interleaved

4. Read and Write of same counter can be interleaved

Asawari 2012

Asawari 2012

1. Do-D7: Data bus ___2. CS : Chip Select. ____3. RD : Read ____4. WR : Write

5. A0-A1: Address lines

A1 A0 Selected Part

0 0 Counter 0

0 1 Counter 1

1 0 Counter 2

1 0 Control Register

6. CLK: Clock Input7. GATE:: Gate Control8. OUT: Output

Asawari 2012

Asawari 2012

Asawari 2012

Asawari 2012

The programmable timer IC provides following modes of operation selected by control word M2 M1 M0 :

Mode 0 Interrupt on terminal count

Mode 1 Programmable one-shot

Mode 2 Rate Generator

Mode 3 Square wave rate generator

Mode 4 Software triggered strobe

Mode 5 Hardware trigger strobe

Asawari 2012

Asawari 2012

Asawari 2012

Asawari 2012

Asawari 2012

Asawari 2012

Asawari 2012

GATE PIN SUMMARY:

Asawari 2012

The programming procedure for the 8253 is very flexible. Only two conventions needs to be remembered:

1.For each Counter the control word must be written before the initial count is written.

2.The initial count must follow the count format specified in CWR. (LSB only, MSB only, LSB first then MSB)

Since the CWR and the three counters have separate address(selected by A1 –A0 inputs) and each Control word specifies thecounter it applies to (SC1 – SC0 bits), no special instruction isSequence is required.

The two generally used formats for initialising control register andloading count values are as follows:

Asawari 2012

A1 A0 Details

1 1 Control word register for counter 0

1 1 Control word register for counter 1

1 1 Control word register for counter 2

0 0 LSB count register value for counter 0

0 0 MSB count register value for counter 0

0 1 LSB count register value for counter 1

0 1 MSB count register value for counter 1

1 0 LSB count register value for counter 2

1 0 MSB count register value for counter 2

FORMAT 1:

Asawari 2012

A1 A0 Details

1 1 Control word register for counter 0

0 0 LSB count register value for counter 0

0 0 MSB count register value for counter 0

1 1 Control word register for counter 1

0 1 LSB count register value for counter 1

0 1 MSB count register value for counter 1

1 1 Control word register for counter 2

1 0 LSB count register value for counter 2

1 0 MSB count register value for counter 2

FORMAT 2:

Asawari 2012

There are 2 methods in 8253 and 3 methods in 8254 available for reading the content of counters without disturbing the actual count in progress:

1)Method 1:i.) Simple I/O read operation.ii.) A0-A1 select countersiii.) Read signal is then issuediv.) Counter should be inhibited (latched) by using

GATE i/pv.) RL0-RL1 bits should be taken care off.vi.) Chances of missing some of the pulses.

2)Method 2:i.) A special internal logic is accessed by issuing

WRITE signal to the control register.ii.) A special code is loaded in the control register

which ultimately latches the count value at that instant.iii.) Then Read command is issued.

SC1 SC0 0 0 X X X X

Asawari 2012

3) Method 3 (only available in 8254):i.) Counter is latched with a read back command.

1 1 ______COUNT

______STATUS

CNT2 CNT1 CNT0 0

Asawari 2012

The status word available when the status is latched is as follows:

The advantage of using method 3 for read operation is that You can latch one, two or all three counters by putting 1 in appropriate select counter bits

Asawari 2012