George Mason University FPGA Memories ECE 448 Lecture 13.

George Mason University

FPGA Memories

ECE 448Lecture 13

Recommended reading

• XST User Guide for Virtex-6, Spartan-6, and 7 Series Devices Chapter 7, HDL Coding Techniques Sections:

• RAM HDL Coding Techniques

• ROM HDL Coding Techniques

•ISE In-Depth Tutorial, Section: Creating a CORE Generator Tool Module

Memory Types

Memory

RAM ROM

Single port Dual port

With asynchronous

With synchronous

Memory

Memory Types specific to Xilinx FPGAs

Memory

Distributed (MLUT-based)

Block RAM-based(BRAM-based)

Inferred Instantiated

Memory

Manually Using CORE Generator

FPGA Distributed

Memory

Location of Distributed RAMRAM blocks

Multipliers

Logic blocks

Graphics based on The Design Warrior’s Guide to FPGAsDevices, Tools, and Flows. ISBN 0750676043

DSP units

RAM blocks

Logic resources

Logic resources(CLB slices)

Three Different Types of Slices

50% 25% 25%

16-bit SR

16 x 1 RAM

4-input LUT

The Design Warrior’s Guide to FPGAsDevices, Tools, and Flows. ISBN 0750676043

Spartan-6 Multipurpose LUT (MLUT)

64 x 1 ROM

(logic)

64 x 1 RAM

32-bit SR

Single-port 64 x 1-bit RAM

Memories Built of Neighboring MLUTs

• Single-port 128 x 1-bit RAM: RAM128x1S• Dual-port 64 x 1-bit RAM : RAM64x1D

Memories built of 2 MLUTs:

Memories built of 4 MLUTs:

• Single-port 256 x 1-bit RAM: RAM256x1S• Dual-port 128 x 1-bit RAM: RAM128x1D• Quad-port 64 x 1-bit RAM: RAM64x1Q• Simple-dual-port 64 x 3-bit RAM: RAM64x3SDP

(one address for read, one address for write)

Dual-port 64 x 1 RAM

• Dual-port 64 x 1-bit RAM : 64x1D• Single-port 128 x 1-bit RAM: 128x1S

Total Size of Distributed RAM

FPGA Block RAM

Location of Block RAMsRAM blocks

Multipliers

Logic blocks

Graphics based on The Design Warrior’s Guide to FPGAsDevices, Tools, and Flows. ISBN 0750676043

DSP units

RAM blocks

Logic resources

Logic resources(CLB slices)

Spartan-6 Block RAM Amounts

Block RAM can have various configurations (port aspect ratios)

16,383

16k x 1

8k x 2 4k x 4

2k x (8+1)

1024 x (16+2)

Block RAM Port Aspect Ratios

Block RAM Interface

Block RAM Ports

Block RAM Waveforms – READ_FIRST mode

Block RAM Waveforms – WRITE_FIRST mode

Block RAM Waveforms – NO_CHANGE mode

Features of Block RAMs in Spartan-6 FPGAs

Inference vs.

Instantiation

Generator

CORE Generator

Generic

Inferred

Distributed ROM with asynchronous read

LIBRARY ieee;USE ieee.std_logic_1164.all;USE ieee.std_logic_arith.all; Entity ROM is generic ( w : integer := 12; -- number of bits per ROM word r : integer := 3); -- 2^r = number of words in ROM port (addr : in std_logic_vector(r-1 downto 0); dout : out std_logic_vector(w-1 downto 0)); end ROM;

architecture behavioral of rominfr is type rom_type is array (2**r-1 downto 0) of std_logic_vector (w-1 downto 0); constant ROM_array : rom_type := ("000011000100", "010011010010", "010011011011", "011011000010", "000011110001", "011111010110", "010011010000", "111110011111"); begin dout <= ROM_array(conv_integer(unsigned(addr))); end behavioral;

architecture behavioral of rominfr is type rom_type is array (2**r-1 downto 0) of std_logic_vector (w-1 downto 0); constant ROM_array : rom_type := ("0C4", "4D2", "4DB", "6C2", "0F1", "7D6", "4D0", "F9F"); begin dout <= ROM_array(conv_integer(unsigned(addr))); end behavioral;

Generic

Inferred

Distributed versus Block RAM Inference

Examples:1. Distributed single-port RAM with asynchronous read

2. Distributed dual-port RAM with asynchronous read

1. Block RAM with synchronous read (no version with asynchronous read!)

More excellent RAM examples from XST Coding Guidelines.

Distributed single-port RAM with asynchronous read

LIBRARY ieee;USE ieee.std_logic_1164.all;USE ieee.std_logic_arith.all; entity raminfr is generic ( w : integer := 32; -- number of bits per RAM word r : integer := 6); -- 2^r = number of words in RAM port (clk : in std_logic; we : in std_logic; a : in std_logic_vector(r-1 downto 0); di : in std_logic_vector(w-1 downto 0); do : out std_logic_vector(w-1 downto 0)); end raminfr;

Distributed single-port RAM with asynchronous read

architecture behavioral of raminfr is type ram_type is array (2**r-1 downto 0) of std_logic_vector (w-1 downto 0); signal RAM : ram_type; begin process (clk) begin if (clk'event and clk = '1') then if (we = '1') then RAM(conv_integer(unsigned(a))) <= di; end if; end if; end process; do <= RAM(conv_integer(unsigned(a))); end behavioral;

Distributed dual-port RAM with asynchronous read

library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; use ieee.std_logic_arith.all; entity raminfr is generic ( w : integer := 32; -- number of bits per RAM word r : integer := 6); -- 2^r = number of words in RAM port (clk : in std_logic; we : in std_logic; a : in std_logic_vector(r-1 downto 0); dpra : in std_logic_vector(r-1 downto 0); di : in std_logic_vector(w-1 downto 0); spo : out std_logic_vector(w-1 downto 0); dpo : out std_logic_vector(w-1 downto 0)); end raminfr;

Distributed dual-port RAM with asynchronous read

architecture syn of raminfr is type ram_type is array (2**r-1 downto 0) of std_logic_vector

(w-1 downto 0); signal RAM : ram_type; begin process (clk) begin if (clk'event and clk = '1') then if (we = '1') then RAM(conv_integer(unsigned(a))) <= di; end if; end if; end process; spo <= RAM(conv_integer(unsigned(a))); dpo <= RAM(conv_integer(unsigned(dpra))); end syn;

Block RAM Waveforms – READ_FIRST mode

Block RAM with synchronous read

LIBRARY ieee;USE ieee.std_logic_1164.all;USE ieee.std_logic_arith.all; entity raminfr is generic ( w : integer := 32; -- number of bits per RAM word r : integer := 9); -- 2^r = number of words in RAM port (clk : in std_logic; we : in std_logic; en : in std_logic; addr : in std_logic_vector(r-1 downto 0); di : in std_logic_vector(w-1 downto 0); do : out std_logic_vector(w-1 downto 0)); end raminfr;

Block RAM with synchronous read Read-First Mode - cont'darchitecture behavioral of raminfr is type ram_type is array (2**r-1 downto 0) of std_logic_vector (w-1 downto 0); signal RAM : ram_type;

begin process (clk) begin if (clk'event and clk = '1') then if (en = '1') then do <= RAM(conv_integer(unsigned(addr))); if (we = '1') then RAM(conv_integer(unsigned(addr))) <= di; end if; end if; end if; end process; end behavioral;

Block RAM Waveforms – WRITE_FIRST mode

Block RAM with synchronous read Write-First Mode - cont'darchitecture behavioral of raminfr is type ram_type is array (2**r-1 downto 0) of std_logic_vector (w-1 downto 0); signal RAM : ram_type;

begin process (clk) begin if (clk'event and clk = '1') then if (en = '1') then if (we = '1') then RAM(conv_integer(unsigned(addr))) <= di;

do <= di; else do <= RAM(conv_integer(unsigned(addr))); end if; end if; end if; end process; end behavioral;

Block RAM Waveforms – NO_CHANGE mode

Block RAM with synchronous read No-Change Mode - cont'darchitecture behavioral of raminfr is type ram_type is array (2**r-1 downto 0) of std_logic_vector (w-1 downto 0); signal RAM : ram_type;

begin process (clk) begin if (clk'event and clk = '1') then if (en = '1') then if (we = '1') then RAM(conv_integer(unsigned(addr))) <= di; else do <= RAM(conv_integer(unsigned(addr))); end if; end if; end if; end process; end behavioral;

Criteria for Implementing Inferred RAM in BRAMs

George Mason University FPGA Memories ECE 448 Lecture 13.

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