Post on 06-May-2015
description
1
EET 3350 Digital Systems Design
Textbook: John Wakerly Chapter 9: 9.6
FPGAs
FPGA
• FPGA Basics• FPGA Architecture
– CLBs– I/O Blocks– Switch Matrix
• Xilinx FPGAs• System Development Boards
2
Advantages of FPGA • The FPGA is one of the most popular logic circuit components
and has revolutionized the way digital systems are designed. Some FPGA advantages include:– Low-cost
– Fast-turnaround prototype implementation
– Supported by CAD/EDA tools
– High density
– High speed
– Programmable and versatile
– Flexible
– Reusable
– Large amounts of logic gates, registers, RAM and routing resources
– Quick time-to-market
– SRAM FPGA provide the benefits of custom CMOS
3
FPGA• There are two primary FPGA architectures:
– fine-grained– coarse-grained
• Another difference in architectures is the underlying
technology used to manufacture the device. The common technologies are:– PROM/EPROM/EEPROM/FLASH based – Anti-fuse based– SRAM based
4
Programmable Switch Technology
• SRAM• Antifuse• EPROM
5
SRAMCell
SRAMCell
0 1
MUX0 or 1
Control Pass Gate
Multiplexer
Programmable Switch Technology
• SRAM• Antifuse• EPROM
6
Disadvantages
Advantages
Volatile
External Permanent Memory Required
Large Area Required
Reprogrammable, easily and quickly
Requires only standard integrated circuit process technology (as opposed to Antifuse)
7
Programmable Switch Technology
• SRAM• Antifuse• EPROM 0
1
AntiFuse Technology
(a) Before programming
Substrate
Metal
Oxide
Metal
Amorphous silicon column
(b) After programming
Polysilicon via
• Growing an antifuse
Programmable Switch Technology
• SRAM• Antifuse• EPROM
9
Disadvantages
Advantages
Not reprogrammable; links made are permanent
Requires extra circuitry to deliverthe high programming voltage
Small size
Relatively low series resistance
Low parasitic capacitance
Programmable Switch Technology
• SRAM• Antifuse• EPROM
10
Control Gate
Floating Gate
Bit
Line
Word Line
Drain Source
Oxide Layer
Control Gate
Floating Gate
Bit
Line
Word Line
Drain Source
Oxide Layer
1
0
- -
- - - - - - -
11
Programmable Switch Technology
• SRAM• Antifuse• EPROM
Disadvantages
Advantages
High resistance of EPROM transistors
High static power consumption
UV light exposure needed to reprogram
No external memory required; retains memory even without power
Reprogrammable
Technology SymbolPredominantly
associated with ...
Fusible-link SPLDs
Antifuse FPGAs
EPROM SPLDs and CPLDs
E2PROM/FLASH
SPLDs and CPLDs(some FPGAs)
SRAM FPGAs (some CPLDs)SRAM
Programmable Switch Technology
• A summary of programmable switches
12
FPGA Architectures
• Fine-grained Architecture– Fine-grained made up of a sea of gates or
transistors or small macro cells – With programmable interconnect between them
13
Almost the opposite of a CPLDAlmost the opposite of a CPLD
FPGA Architectures
• Coarse-grained Architecture– Coarse-grained FPGAs include bigger macrocells– The macrocells usually include Flip-Flops and Look
Up Tables (LUTs) which are used to implement combinatorial logic functions
– In a majority of these architectures, four-input look-up table (think of it as a 16x1 ROM) implement the actual logic
– The larger logic block usually results in improved performance when compared to fine-grained architectures
14
FPGA Process Technology
• PROM/EPROM/EEPROM/FLASH based– These implementations are typically programmed
out of circuit and can or cannot be reprogrammed • PROM is one time programmable (OTP) device can only be
programmed once
– EPROM cells are electrically programmed in a device programmer
– Some EPROM-based devices are erasable using ultra-violet (UV) lights if they are in a windowed package
– EEPROMs are in low-cost plastic packaging for production • Plastic packages cannot be UV erased, they are electrically
erased
15
FPGA Process Technology
• PROM/EPROM/EEPROM/FLASH based– An Electrically-Erasable-Programmable-Read-Only-
Memory (EEPROM) memory cell is physically larger than an EPROM cell but offers the advantage of being erased electrically with no special UV erasers require. • EEPROM devices can be erased, even in low-cost plastic
packaging.
– FLASH-erased (or bulk erased) electrically erasable programmable read-only memory. • FLASH has the electrically erasable benefits of EEPROM
but the small, economical cell size of EPROM technology.
16
FPGA Process Technology
• Anti-fuse based– Anti-fuse is a one-time programmable (OTP)– Fuses are permanently put in place – The anti-part of anti-fuse comes from its
programming method • Instead of breaking a metal connection by passing current
through it, a link is grown to make a connection
– Anti-fuses are either amorphous silicon or metal-to-metal connections
17
FPGA Process Technology
• Anti-fuse based– The advantages of anti-fuse FPGAs include:
• They are usually physically quite small• They have low resistance interconnect
– Disadvantages include• They require large programming transistors on the device • They cannot be reused (they are OTP)
18
FPGA Process Technology
• SRAM based– SRAM cells are implemented as function generators to
simulate combinatorial logic and also are used to control multiplexors and routing resources
– This is by far the most popular process technology– This method is similar to the technology used in static
RAM devices but with a few modifications • The RAM cells in a memory device are designed for fastest
possible read/write performance • The RAM cells in a programmable device are usually designed
for stability instead of read/write performance • Consequently, RAM cells in a programmable device have a
low-impedance connect to VCC and ground to provide maximum stability over voltage fluctuations
19
FPGA Process Technology
• SRAM based (cont.)– Because static memory is volatile (the contents
disappear when the power is turned off), SRAM-based devices are "booted" after power-on
– This makes them in-system programmable and re-programmable, even in real-time
– As a result, SRAM-based FPGAs are common in reconfigure computing applications where the device's function is dynamically changed
20
FPGA Process Technology
• SRAM based (cont.)– The configuration process typically requires only a
few hundred milliseconds at most – Most SRAM-based devices can boot themselves
automatically at power-on much like a microprocessor
– Most SRAM-based devices are designed to work with either standard byte-wide PROMs or with sequential-access serial PROMs
21
22
FPGAs
• Historically, FPGA architectures and companies began around the same time as CPLDs
• FPGAs are closer to “programmable ASICs”– Large emphasis on interconnection routing– Timing is difficult to predict -- multiple hops vs. the
fixed delay of a CPLD’s switch matrix– But more “scalable” to large sizes
• FPGA programmable logic blocks have only a few inputs and 1 or 2 flip-flops, but there are a lot more of them compared to the number of macrocells in a CPLD
FPGAs
• General FPGA chip architecture, coarse-grained
23
a.k.a. CLB: “configurable logic block”a.k.a. CLB: “configurable logic block”
LogicBlock
I/O Block
InterconnectionSwitches
FPGAs
• FPGAs do not contain AND or OR planes• Three major elements:
– Logic blocks– I/O blocks– Interconnection wires
and switches
24
all elements are all elements are programmableprogrammable
Other FPGA Building Blocks
• Clock distribution• Embedded memory blocks• Special purpose blocks:
– DSP blocks: • Hardware multipliers, adders and registers
– Embedded microprocessors/microcontrollers– High-speed serial transceivers
FPGA – Basic Logic Element• LUT to implement combinatorial logic• Register for sequential circuits• Additional logic (not shown):
– Carry logic for arithmetic functions– Expansion logic for functions requiring more than 4 inputs
LUTLUT
Out
Select
D Q
A
B
C
D
Clock
Look-Up Tables (LUT)• Look-up table with N-inputs can be used to implement
any combinatorial function of N inputs• LUT is programmed with the truth-table
LUTLUTABCD
Z
A
B
C
D
Z
Truth-tableTruth-table Gate implementationGate implementation
LUT implementationLUT implementation
LUT Implementation
• Example: 3-input LUT• Based on multiplexers
(pass transistors)• LUT entries stored in
configuration memory cells
0/10/1
0/10/1
0/10/1
0/10/1
0/10/1
0/10/1
0/10/1
0/10/1
X1X2
X3
F
configuration memory cellsconfiguration memory cells
Other FPGA Building Blocks
• Clock distribution• Embedded memory blocks• Special purpose blocks:
– DSP blocks:• Hardware multipliers, adders and registers
– Embedded microprocessors/microcontrollers– High-speed serial transceivers
Special Features
• Clock management– PLL,DLL– Eliminate clock skew between external clock input
and on-chip clock– Low-skew global clock distribution network
• Support for various interface standards• High-speed serial I/Os• Embedded processor cores• DSP blocks
Configuration Storage Elements
• Static Random Access Memory (SRAM)– Logical configuration is controlled by the state of
SRAM bits– FPGA needs to be configured at power-on by
another separated ROM
• Flash Erasable Programmable ROM (Flash)– Logical configuration is implemented by floating-
gate transistors that can be turned off by injecting charge onto its gate.
– FPGA itself holds the program– reprogrammable, even in-circuit
FPGA• Xilinx refers to the “interconnection switches” as the
switch matrix
32
CLB CLB
CLB CLB
SM SM
SM SM
CLB CLB
CLB CLB
SM
SM
CLB CLB
CLB CLB
SM SM
CLB CLB
CLB CLB
SM
IOB IOB IOB IOB
IOB IOB IOB IOB
IOB
IOB
IOB
IOB
IOB
IOB
IOB
IOB
Programmable Programmable Switch MatrixSwitch Matrix
FPGAs
• Programmable Switch Matrix
33
turning the corner, etc.turning the corner, etc.
programmable switch elementprogrammable switch element
FPGA Logic Block• The storage cells in the LUTs in an FPGA are volatile
– losing stored contents whenever the power is off
• Using PROM to hold data permanently• The storage cells are loaded automatically from
PROM when the chip is initialized
0/10/10/10/1
x1
x2
fLUT
34
DQ
Clock
Select
Out
LUT
In1In2In3
Logic Block
In4
FPGAs
• An example of programming an FPGA
0001
x1
x2
f1
0100
x2
x3
f2
0111
f1
f2
f3
x1
x2
x3 f
3221
322
211
xxxxf
xxf
xxf
35
0/10/10/10/1
x1
x2
fLUT
FPGAs
• An example of programming an FPGA
0001
x1
x2
f1
0100
x2
x3
f2
0111
f1
f2
f3
x1
x2
x3 f
36
3221
322
211
xxxxf
xxf
xxf
0/10/10/10/1
x1
x2
fLUT
Xilinx 4000-Series FPGAs• Characteristics of the Xilinx 4000-series FPGAs
37
38
Configurable Logic Block (CLB)
Logic Function Generators
• Look-Up Tables (LUT)– Memory to store truth tables
• F, G– 16 x 1 SRAMs
• H– 8 x 1 SRAM
• Can be configured as memory
39
40
CLB function generators (F, G, H)
• Use RAM to store a truth table– F, G: 4 inputs, 16 bits of RAM each– H: 3 inputs, 8 bits of RAM– RAM is loaded from an external PROM at system
initialization.
• Broad capability using F, G, and H:– Any 2 funcs of 4 vars, plus a func of 3 vars– Any func of 5 vars– Any func of 4 vars, plus some funcs of 6 vars– Some funcs of 9 vars, including parity and 4-bit
cascadable equality checking
FPGAs• CLB input and output connections – buried in the sea
of interconnect
41
CLB
CLB
42
Detail
connectionsconnectionscontrolled bycontrolled by
RAM bitsRAM bits
43
The Fitter’s Job
• Partition logic functions into CLBs• Arrange the CLBs• Interconnect the CLBs• Minimize the number of CLBs used• Minimize the size and delay of interconnect
used• Work with constraints
– “Locked” I/O pins– Critical-path delays– Setup and hold times of storage elements
44
I/O Blocks
Spartan-II FPGA
45
Logic Fabric
• Logic Cell– Lookup table (LUT)– Flip-Flop– Carry logic– Muxes (not shown)
• Slice– Two Logic Cells
• Spartan-3E FPGAs– 2K to 33K logic cells
I3
I1
I2
I0
O
D Q
SET
RST
CE
D Q
SET
RST
CE0 1
I3
I1
I2
I0
O 0 1
46
Memory
• Block RAM– RAM or ROM– True dual port
• Separate read and write ports
– Independent port size• Data width translation
– Excellent for FIFOs
Configuration Depth Data bits Parity bits16K x 1 16Kb 1 08K x 2 8Kb 2 04K x 4 4Kb 4 02K x 9 2Kb 8 1
1K x 18 1Kb 16 2512 x 36 512 32 4
Block RAM Configurations
CLKA
DIPA
ADDRA
DOPA
CLKB
ADDRB
DIA DOA
DIPB DOPBDIB DOB
47
Multipliers
• 18 x 18 Multipliers– Signed or unsigned– Optional pipeline stage– Cascadable
18 bit
18 bit
36 bit
48
Clock Management
• Digital Clock Managers (DCMs)– Clock de-skew– Phase shifting– Clock multiplication – Clock division– Frequency synthesis
CLKIN CLK0
CLK90
CLKFX
49
CLB Logic Cells (x4)
50
Dual-Port Block Ram (SRAM)
51
• A training resource
BASYS Board Components
52
BASYS Board Components
• 100K FPGA• USB2 Port• Flash ROM• I/O Devices• PS/2 and VGA• Clock• Expansion
Connectors
53
FPGA Selection Guide
• Xilinx Spartan-3 series FPGAs
54
Summary
• Complex Programmable Logic Devices– Function Blocks
• AND Arrays and Macrocells
– Programmable Interconnect– I/O
• Field Programmable Gate Arrays– Configurable Logic Blocks
• Look-up Tables
– Programmable Interconnect– I/O
55