Ensuring Signal and Power Integrity for High-Speed Digital ... 2015 - Schuster - Handout.pdf ·...

Ensuring Signal and Power Integrity

for High-Speed Digital Systems

An EMC Perspective

Christian Schuster

Institut für Theoretische Elektrotechnik

Technische Universität Hamburg-Harburg (TUHH)

Invited Presentation at the IEEE International Conference on Consumer

Electronics (ICCE), Berlin, September 6-9, 2015

C. Schuster, TUHH – 2

Abstract

With increasing data rates and reduced margin for communication

errors both consumer electronic products as well a large-scale

digital systems like data centers have to be designed very carefully

with respect to their “electrical integrity”. In this presentation two

aspects of this integrity, namely signal integrity (SI) and power

integrity (PI), will be explained in some detail. The focus will be put

mostly on packaging and electromagnetic compatibility (EMC)

aspects. Topics that will be addressed include discontinuities,

transmission line effects, crosstalk, bypassing and decoupling, via

and power plane effects, return current issues, and measurement

techniques. The presentation should be suitable for both a

technical and a non-technical audience. For more information on SI

and PI research at TUHH visit: http://www.tet.tuhh.de

(1) Motivation

(2) SI, PI & EMI

(3) High-Speed Digital Systems

(4) Improving SI

(5) Improving PI

(6) Wrapping Up

Outline

Motivation

Digital Link Data Rates

Data Rate [Gb/s]

CPU to CPU Storage Network/ Peripherals

Infiniband

Transport

SA-SCSI

SATA III

6.0 Fibre

Channel

10G Ethernet

USB 2.0

FireWire

up 3.2

Digital Link Frequency Trends

SI, PI & EMI

Power Plane Ground Plane

Driver Via

Receiver

Digital Link Seen From ..

DC Power Supply

.. a Signal Transmission Perspective

Signal Transmission Issues:

Attenuation, Reflection, Dispersion, Interference, Crosstalk

.. a Signal Transmission Perspective

Signal Transmission Issues:

Attenuation, Reflection, Dispersion, Interference, Crosstalk

.. a Power Delivery Perspective

Power Delivery Issues:

Voltage Drop, Switching Noise, Crosstalk

.. a Power Delivery Perspective

Power Delivery Issues:

Voltage Drop, Switching Noise, Crosstalk

.. an EMI Perspective

Electromagnetic Interference Issues:

Near Field Coupling, Radiated Emissions

.. an EMI Perspective

Electromagnetic Interference Issues:

Near Field Coupling, Radiated Emissions

SI + PI + EMI = Comprehensive EMC

Elements of a comprehensive EMC

SI/PI Foundations and Resources

SI / PI

Transmission

Line Theory

Antenna

Theory

Network

Theory System Theory

Coupler &

Filter Design

EM Field

Theory

Communication

Theory

Circuit Design &

Simulation

Numerical

Techniques

Electromagnetic

Compatibility

HF Measurement

Techniques

CAD Tools

Material

Characterizationj

SI/PI Foundations and Resources

Figures © C. Schuster,

TET, TUHH

SI/PI in the IEEE Community

Number of publications

found in IEEE Xplore

containing the index

terms:

“Signal Integrity“

“Power Integrity“

SI/PI in the EMC Community

High-Speed Digital Systems

A High-Speed Digital System

Housing / Chassis

Connector

Package / Module

IC (Transmitter)

IC (Receiver)

Connector

Backplane / Motherboard

Socket

The SI Challenge

Connector

Interconnect

(Link)

The ideal interconnect will simply delay the signal:

Any real interconnect will additionally change timing and amplitude:

Effect of Interconnects

Jitter and Noise

The deviations in timing and amplitude are in general called:

Timing jitter or simply: JITTER

Amplitude noise or simply: NOISE

Receiver

Sampling

In the eye diagram timing jitter and anplitude noise are defined as follows:

JITTER

Jitter and Noise

The PI Challenge

Connector VRM

Effect of Common Power Delivery

IC #1 IC #2

PDN = Power Delivery Network

Effect of Common Power Delivery

R uIC L

iGate1, iGate2, …

uIC = U0 - Du

...)()(...)()()( Gate1Gate1Gate1Gate1 D titidt

dLtitiRtu

"DC-drop or IR-drop" "DI-drop or DI-noise"

Improving SI

Improving Signal Integrity

1. Match terminations

2. Minimize discontinuities

3. Reduce Coupling

4. Limit attenuation

5. Balance deficiencies

High performance digital links are mostly serial: HSS = HIGH SPEED SERIAL.

The technology is typically CMOS with the links being voltage mode,

unidirectional, serial, point-to-point, and source-synchronous. Both single-ended

and differential signaling can be found.

For improved bandwidth equalization is typically used in the Tx, Rx, or both.

Deserializer

Interconnect

Clock & Data Recovery

Data .

Serializer

Equalizer

+ Slicer

Typical Digital Link Design

3. Reduce Coupling

Effect of Terminations

Let‘s use the following interconnect (link) model:

lZ ,,0

u0 u1 u2

Transmitter Receiver Interconnect

Metal Dielectric

Microstrip

Stripline

(symmetric)

(h = height of dielectric,

w = conductor width,

t = conductor thickness)

98.5ln

(h = height of dielectric,

w = conductor width,

t = conductor thickness)

Transmission Lines in Digital Systems

Let‘s use the following interconnect (link) model:

lZ ,,0

u0 u1 u2

!max. and const.0

lZ ,,0

input acceptance TL transfer function

source transmission load transmission

source reflection load reflection

lZ ,,0

2 0LS ZZZ

lZ ,,0

0L ZZ Hau

Matched interconnect:

Mismatched Interconnect:

low source impedance

high source impedance

lossless transmisson line

lossy transmisson line

1 kΩ1,Ω50,Ω10 L0S ZZZ

zero losses

2 Ω100,Ω50,Ω50 L0S ZZZ

zero losses

3 Ω50,Ω50,Ω50 L0S ZZZ

zero losses

4 Ω100,Ω50,Ω100 L0S ZZZ

zero losses

kΩ1,Ω50,Ω10 L0S ZZZ

non-zero losses

6 Ω50,Ω50,Ω50 L0S ZZZ

non-zero losses

(all lines have a delay of 0.1 ns)

3. Reduce coupling

Packaging of Digital Systems

Connector

Interconnect

(Link)

Effect of Lumped Discontinuities

Signal

u1 u2 50

50 2.5

Tx-Output Bond Wire Rx-Input

Source

Voltage

Received

Voltage

Attenuation of high frequency signal components

„Slowing down" of the edges of a digital signal

Frequency [GHz] Time [ps]

Magnitude o

Frequency Response Step Response

f0 ≈ 6.37 GHz t 1/w0 = 25 ps

Signal

In Signal

50 50 1 pF

Tx-Output Via Rx-Input

Source

Voltage

Received

Voltage

Attenuation of high frequency signal components !!

„Slowing down" of the edges of a digital signal !!

Frequency [GHz] Time [ps]

Magnitude o

Frequency Response Step Response

f0 ≈ 6.37 GHz t 1/w0 = 25 ps

Effect of Distributed Discontinuities

lZ ,, 0Z0Z

cf 952.2

1 inch, 45 Ohm mismatched transmission line at c0 /2

Frequency Response

(Scattering Parameters)

Overall Effect of Discontinuities

0 0 0 0

Port1 Port2

2nHZ=48

P=15cm

3. Reduce coupling

Packaging of Digital Systems

Connector

Interconnect

(Link)

(3) Near End (4) Far End

Aggressor Line (Active Line)

Victim Line (Quiet Line)

(1) Input (2) Output

Effect of Coupling

Consider two transmission lines in close proximity:

IC-NE IC-FE

Effect of Coupling

Capacitive Crosstalk

UL-NE UL-FE

Effect of Coupling

Inductive Crosstalk

(3) Near End (4) Far End

(1) Input (2) Output

NEXT =

Near End Crosstalk (sum of ind. and cap. crosstalk)

FEXT =

Far End Crosstalk (difference of ind. and cap. crosstalk)

Effect of Coupling

3. Reduce Coupling

Attenuation usually increases with frequency. The exact calculation can be

difficult but for weakly lossy lines:

a convenient approximations exists:

with ac = attenuation due to conductor losses and ad = attenuation due to

dielectric losses. The following dependencies are often found:

with k = electrical conductivity and tan d = loss tangent.

CGLR ww and

dw tan~ CGkw /~R

Contributors to Line Losses

Time Domain Effect of Losses

When taking into account DC losses the effect in the time domain is twofold:

edge degradation

DC drop

Voltage

step response

without losses

step response

with losses

For the frequency dependence follows with these assumptions:

In other words, a typical semi-

logarithmic plot of the magnitude

of the transfer function will be

dominated by a square root

behavior at lower and a linear

behavior at higher frequencies.

fflllleeeeeeH

dcdc constconst

ffH dc constconst~ln

linear

square root

Frequency Dependence of Losses

Dielectric Packaging Materials

Dielectric materials are typically classified with respect to their

relatice dielectric constant r and their loss tangent tan d:

Quartz (SiO2) Alumina (Al2O3)

"FR-4"

Silicon Teflon (PTFE)

3. Reduce coupling

Overview of Equalization Techniques

Deserializer

Interconnect

Clock & Data Recovery

Data .

Serializer

Equalizer

+ Slicer

Most high speed serial links nowadays use some EQUALIZATION, i.e. some

kind of signal processing technique to correct for the degradations in the

interconnect, and thereby improve the quality of signals. When the corrections

are applied at the transmitter equalization is sometimes also called DE-

EMPHASIS or PRE-EMPHASIS. Apart from continuous time equalization (CTE)

signal processing takes place in the discrete time domain / digital filters.

In frequency domain the effect of equalization can be to some extent be

visualized as the flattening of the transfer function of the interconnect.

An interconncet with a completely flat transfer function would transmit a signal

undisturbed apart from a potential amplitude scaling.

Interconnect

Equalization

Equalized Response

Two big classes of (digital, discrete) equalization exist:

Equalization

Linear Feedforward

Equalization (LFE/FFE) Distributed Feedback

Equalization (DFE)

- Uses only information from the

current and previously received

- Can be interpreted as a non-

recursive digital filter (finite

impulse response filter)

- Uses a feedback loop after the

signal has been decoded by an

LFE/FFE

- The output of the LFE/FFE is

added to the feedback loop

resulting in the equalized signal

Improving PI

Improving Power Integrity

1. Decrease PDN impedance

2. Add decoupling

3. Add more decoupling

4. Use several power supplies

5. Use on-chip VRMs

Discrete

Decoupling

Capacitors

(various sizes)

IC incl.

Power/Ground Grid

& Integrated Decaps

Printed Circuit Board incl.

Power/Ground Planes

High Power

DC Supply

Voltage

Regulator

Module

Package incl.

Power/Ground

Planes

PDN Elements

2. Add decoupling

5. Use on-chip VRMs

A typical maximum ripple for ditigal systems is:

With a 10% value the following numbers can be obtained for

applications … of the early 1990'ies: … of 2000 and on:

PDN Impedance

Ω0.5/

Target

%10to%5ripple maximum0

Ω001.0

Ω01.0/

Target

= 1 m !

2. Add decoupling

5. Use on-chip VRMs

Low Frequency Equivalent PDN Circuit

U0 ~ ZIC ( f )

… including a "decoupling" or "bypass" capacitor:

Low Frequency Equivalent PDN Circuit

U0 ~ ZIC ( f ) C

… some nF to some mF

Heuristic explanation:

Frequency domain: Beyond the resonance frequency the capacitor

decouples the part of the PDN that lies "left" of him, i.e. the IC sees

only the impedance of the capacitor.

Time domain: The capacitor stores charges close to the IC that can

become currents needed for fast switching. It is like a "small battery".

Decoupling Effect

U0 ~ ZIC ( f ) C

Unfortunately, there is no ideal capacitor available in the real world!

Ideal world: … and real world:

R is also is called the EQUIVALENT SERIES RESISTANCE

(ESR) and L the EQUIVALENT SERIES INDUCTANCE (ESL).

As a consequence any real world capacitor behaves approximately

like an inductor beyond its resonance frequency:

Real Word Decoupling Capacitors

C R L C

LC/10 w

2. Add decoupling

5. Use on-chip VRMs

More Decoupling

Speed of charge

delivery,

effective

frequency

board-level package-level chip-level

Amount of

charge, size

of decoupling

capacitance

More Decoupling P

pedance

Target

Impedance

Inductance

Capacitance

of Bulk

Decaps

ESL of

Decaps, Pads

and Vias

Capacitance of

P/G Planes &

Small Decaps

ESL of Planes

and Inductance

of Package

Remaining

On.Chip

Inductance

500 MHz 10 GHz 1 GHz 1 MHz

Capacitance of

Decaps on

Package and IC

board-level package-level chip-level

...),2,1,0,(22

Resonance frequencies of power/ground plane pairs:

Examples of standing wave patterns on a rectangular power/ground plane pair.

Power/Ground Plane Resoances

Wrapping Up

Comprehenisve EMC of Digital Systems

The basic goals of SI, PI, and EMI control for a digital system are

complementary to each other.

SIGNAL INTEGRITY: insure

acceptable quality of signals within

POWER INTEGRITY: insure

acceptable quality of power

delivery within

EMI: insure acceptable level of

interference with the outside

Frequency

Target

System

Frequency

Impedance

Target

System

Frequency

Target System

Ensuring Signal and Power Integrity for High-Speed Digital ... 2015 - Schuster - Handout.pdf ·...

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