Post on 03-Jul-2020
Introduction to Computer Engineering – EECS 203http://ziyang.eecs.northwestern.edu/∼dickrp/eecs203/
Instructor: Robert Dick
Office: L477 Tech
Email: dickrp@northwestern.edu
Phone: 847–467–2298
TA: Neal Oza
Office: Tech. Inst. L375
Phone: 847-467-0033
Email: nealoza@u.northwestern.edu
TT: David Bild
Office: Tech. Inst. L470
Phone: 847-491-2083
Email: d-bild@northwestern.edu
EncodersDecoders
MultiplexersHomework
Encoders
Assume you have n one-bit signals
Only one signal can be 1 at a time
How many states can you be in?
How many signals are required to encode all those states?
3 R. Dick Introduction to Computer Engineering – EECS 203
EncodersDecoders
MultiplexersHomework
Encoder example
Pressed (i2, i1, i0) Code (o1, o0)
000 00001 01010 10011 XX100 11101 XX110 XX111 XX
Implementation?
4 R. Dick Introduction to Computer Engineering – EECS 203
EncodersDecoders
MultiplexersHomework
Priority encoder
What if we want the highest-order high signal to dominate?
Pressed (i3, i2, i1) Code (o1, o0)
000 00001 01010 10011 10100 11101 11110 11111 11
What impact on implementation efficiency?
5 R. Dick Introduction to Computer Engineering – EECS 203
EncodersDecoders
MultiplexersHomework
Decoders
Need to map back from encoded signal to state
Pressed (i1, i0) Code (o3, o2, o1, o0)
00 000101 001010 010011 1000
o0 isn’t always used. Why?Most straightforward implementation?
7 R. Dick Introduction to Computer Engineering – EECS 203
EncodersDecoders
MultiplexersHomework
Straight-forward decoder implementation
n NOTs n inputs
2n ANDs
i1 i1 i0 i0
o0
o1
o2
o3
8 R. Dick Introduction to Computer Engineering – EECS 203
EncodersDecoders
MultiplexersHomework
Decoder implementation efficiency
n NOTs
n2 n-input ANDS
O(
n2)
Can’t do this for large number of inputs!
Instead, decompose into multi-level implementation
9 R. Dick Introduction to Computer Engineering – EECS 203
EncodersDecoders
MultiplexersHomework
Multilevel decoder implementation
Starting point
o0 = i2 i1 i0
o1 = i2 i1 i0
o2 = i2 i1i0
o3 = i2 i1i0
o4 = i2i1 i0
o5 = i2i1 i0
o6 = i2i1i0
o7 = i2i1i0
10 R. Dick Introduction to Computer Engineering – EECS 203
EncodersDecoders
MultiplexersHomework
Multilevel decoder implementation
o0 = i2 (i1 i0 )
o1 = i2 (i1 i0)
o2 = i2 (i1i0 )
o3 = i2 (i1i0)
o4 = i2(i1 i0 )
o5 = i2(i1 i0)
o6 = i2(i1i0 )
o7 = i2(i1i0)
Reuse terms! Schematic?
11 R. Dick Introduction to Computer Engineering – EECS 203
EncodersDecoders
MultiplexersHomework
Multiplexers or selectors
Routes one of 2n inputs to one output
n control lines
Can implement with logic gates
13 R. Dick Introduction to Computer Engineering – EECS 203
EncodersDecoders
MultiplexersHomework
Logic gate MUX
Decoder
i0
i1
i2
i3
s0
s1
o
However, there is another way. . .
14 R. Dick Introduction to Computer Engineering – EECS 203
EncodersDecoders
MultiplexersHomework
MUX functional table
C Z
0 I01 I1
15 R. Dick Introduction to Computer Engineering – EECS 203
EncodersDecoders
MultiplexersHomework
MUX truth table
I1 I0 C Z
0 0 0 00 0 1 00 1 0 10 1 1 01 0 0 01 0 1 11 1 0 11 1 1 1
16 R. Dick Introduction to Computer Engineering – EECS 203
EncodersDecoders
MultiplexersHomework
Review: CMOS transmission gate (TG)
C
A
C
B
C = 1
C = 0
17 R. Dick Introduction to Computer Engineering – EECS 203
EncodersDecoders
MultiplexersHomework
Review: Other TG diagram
18 R. Dick Introduction to Computer Engineering – EECS 203
EncodersDecoders
MultiplexersHomework
MUX
C
C
C
C
A
B
D
19 R. Dick Introduction to Computer Engineering – EECS 203
EncodersDecoders
MultiplexersHomework
MUX using TGs
I3
I0
I2
I1
AA BB
ZZ
20 R. Dick Introduction to Computer Engineering – EECS 203
EncodersDecoders
MultiplexersHomework
Hierarchical MUX implementation
4 :1
mux
4 :1
mux
8 :1
mux
2 :1
mux
0
1
2
3
0
1
2
3
S
S1
S0
S1
S0
Z
ACB
I0
I1
I2
I3
I4
I 5
I6
I7
0
1
21 R. Dick Introduction to Computer Engineering – EECS 203
EncodersDecoders
MultiplexersHomework
Alternative hierarchical MUX implementation
00
11SS
00
11SS
00
11 SS
00
11SS
00
11
S 1
22
33S 0
AA BB
II00
II11
II22
II33
II44
II55
II66
II77
CC
CC
CC
22 R. Dick Introduction to Computer Engineering – EECS 203
EncodersDecoders
MultiplexersHomework
MUX examples
2:1
m ux
I0
I1
A
Z
Z = A I0 + AI1
23 R. Dick Introduction to Computer Engineering – EECS 203
EncodersDecoders
MultiplexersHomework
MUX examples
I0
A
I1
I2
I3
B
Z4:1
m ux
Z = AB I0 + A BI1 + AB I2 + ABI3
24 R. Dick Introduction to Computer Engineering – EECS 203
EncodersDecoders
MultiplexersHomework
MUX examples
I0
A
I1
I2
I3
B
Z8:1
m ux
C
I4
I5
I6
I7
Z = AB C I0 + AB CI1 + A BC I2 + A BCI3+
AB C I4 + AB CI5 + ABC I6 + ABCI7
25 R. Dick Introduction to Computer Engineering – EECS 203
EncodersDecoders
MultiplexersHomework
MUX properties
A 2n : 1 MUX can implement any function of n variables
A 2n−1 : 1 can also be used
Use remaining variable as an input to the MUX
26 R. Dick Introduction to Computer Engineering – EECS 203
EncodersDecoders
MultiplexersHomework
MUX example
F (A,B,C ) =∑
(0, 2, 6, 7)
= AB C + A BC + ABC + ABC
27 R. Dick Introduction to Computer Engineering – EECS 203
EncodersDecoders
MultiplexersHomework
Truth table
A B C F
0 0 0 10 0 1 00 1 0 10 1 1 01 0 0 01 0 1 01 1 0 11 1 1 1
28 R. Dick Introduction to Computer Engineering – EECS 203
EncodersDecoders
MultiplexersHomework
Lookup table implementation
8:1
MUX
1
0
1
0
0
0
1
11
0
1
2
3
4
5
6
77 S2 S1 S0
AA BB CC
FF
29 R. Dick Introduction to Computer Engineering – EECS 203
EncodersDecoders
MultiplexersHomework
MUX example
F (A,B,C ) =∑
(0, 2, 6, 7)
= AB C + A BC + ABC + ABC
Therefore,
AB → F = C
A B → F = C
AB → F = 0
AB → F = 1
30 R. Dick Introduction to Computer Engineering – EECS 203
EncodersDecoders
MultiplexersHomework
Truth table
A B C F
0 0 0 10 0 1 00 1 0 10 1 1 01 0 0 01 0 1 01 1 0 11 1 1 1
F=C
31 R. Dick Introduction to Computer Engineering – EECS 203
EncodersDecoders
MultiplexersHomework
Lookup table implementation
S1 S0
AA BB
4:1
M UX
0
1
2
33
00
11
FF
C
C
32 R. Dick Introduction to Computer Engineering – EECS 203
EncodersDecoders
MultiplexersHomework
Demultiplexer (DMUX) definitions
Closely related to decoders
n control signals
Single data input can be routed to one of 2n outputs
33 R. Dick Introduction to Computer Engineering – EECS 203
EncodersDecoders
MultiplexersHomework
Recall decoders
n NOTs n inputs
2n ANDs
i1 i1 i0 i0
o0
o1
o2
o3
34 R. Dick Introduction to Computer Engineering – EECS 203
EncodersDecoders
MultiplexersHomework
DMUXs similar to decoders
Use extra input to control output signal35 R. Dick Introduction to Computer Engineering – EECS 203
EncodersDecoders
MultiplexersHomework
Demultiplexer
C
C
C
C
D
A
E
36 R. Dick Introduction to Computer Engineering – EECS 203
EncodersDecoders
MultiplexersHomework
Dangers when implementing with TGs
C
C
C
C
D
A
E
C = 1
37 R. Dick Introduction to Computer Engineering – EECS 203
EncodersDecoders
MultiplexersHomework
Dangers when implementing with TGs
C
C
C
C
D
A
E
C = 1
What if an output is not connected to any input?38 R. Dick Introduction to Computer Engineering – EECS 203
EncodersDecoders
MultiplexersHomework
Review: Consider undriven inverter inputs
VDD
VSS
A B
39 R. Dick Introduction to Computer Engineering – EECS 203
EncodersDecoders
MultiplexersHomework
Set all outputs
C
C
C
C
C
C
A
0
E
0
C
C
D
40 R. Dick Introduction to Computer Engineering – EECS 203
EncodersDecoders
MultiplexersHomework
Demultiplexers as building blocks
3 :8
dec
0
1
2
3
4
5
6
7
A B C
Enb
ABC
ABC
ABC
ABC
ABC
ABC
ABC
ABCS2
S1
S0
Generate midterm based on control signals
41 R. Dick Introduction to Computer Engineering – EECS 203
EncodersDecoders
MultiplexersHomework
Example function
F1 = AB CD + A BC D + ABCD
F2 = ABC D + ABC = ABC D + ABCD + ABCD
F3 = A + B + C + D = ABCD
42 R. Dick Introduction to Computer Engineering – EECS 203
EncodersDecoders
MultiplexersHomework
Demultiplexers as building blocks
A B C D
A B C D
A B C D
A B C D
A B C D
A B C D
A B C D
A B C D
A B C D
A B C D
A B C D
A B C D
A B C D
A B C D
A B C D
A B C D
F1
F3
0
1
2
3
4
5
6
7
8
9
10
1 1
12
13
14
15
A
S3
S2
S1
S0
4:16
dec
Enb
B C D
F2
43 R. Dick Introduction to Computer Engineering – EECS 203
EncodersDecoders
MultiplexersHomework
Status
CMOS
Switch-based and gate-based design
Two-level minimization
Encoders
Decoder
Multiplexers
Demultiplexers
Is anything still unclear? Then let’s do some examples!
44 R. Dick Introduction to Computer Engineering – EECS 203
EncodersDecoders
MultiplexersHomework
Lab three
Requires error detection
Read Section 1.4 in the book
How to build an error injector, i.e., a conditional inverter?
How to build a two-input parity gate?
How to build a three-input parity gate from two-input paritygates?
How to detect even number of ones?
45 R. Dick Introduction to Computer Engineering – EECS 203
EncodersDecoders
MultiplexersHomework
Reading assignment
M. Morris Mano and Charles R. Kime. Logic and Computer
Design Fundamentals. Prentice-Hall, NJ, fourth edition, 2008
Sections 1.2–1.7
47 R. Dick Introduction to Computer Engineering – EECS 203
EncodersDecoders
MultiplexersHomework
Computer geek culture reference
Cliff Stoll. The Cukoo’s Egg. Bantam Doubleday Dell PublishingGroup, 1989
48 R. Dick Introduction to Computer Engineering – EECS 203