1Jose E. Schutt‐Aine ‐ ECE 442

ECE 442Solid‐State Devices & Circuits

Review

Jose E. Schutt-AineElectrical & Computer Engineering

University of Illinoisjschutt@emlab.uiuc.edu

2Jose E. Schutt‐Aine ‐ ECE 442

Diode Circuits - RectificationsininV A tω=

Rectification with ripple reduction. C must be large enough so that RC time constant is much larger than period

3Jose E. Schutt‐Aine ‐ ECE 442

Find the barrier voltage across the depletion region of a silicon diode at T = 300 K with ND=1015/cm3 and NA=1018/cm3.

2ln A Do T

i

N NV Vn

⎛ ⎞= ⎜ ⎟

⎝ ⎠

Example

Use

( )

18 15 13

2 20

10 10 100.026ln 0.026ln2.251.5 10

o oV ψ⎛ ⎞ ⎡ ⎤⋅

= = =⎜ ⎟ ⎢ ⎥⎜ ⎟× ⎣ ⎦⎝ ⎠

10 31.5 10 /cmin = ×0.026 VTV =

@ 300K,

0.026 29.12 0.7571 voltso oV ψ= = × =

0.7571 voltso oV ψ= =

4Jose E. Schutt‐Aine ‐ ECE 442

Two diodes are connected in series as shown in the figure with Is1=10-16 A and Is2 =10-14 A. If the applied voltage is 1 V, calculate the currents ID1 and ID2 and the voltage across each diode VD1 and VD2.

Example

1 /1 1

D TV VD SI I e= 2 /

2 2D TV V

D SI I e=1 2

1 1

2 2

1D D

T

V VVS D

S D

I IeI I

−

= =

11 2

2

ln 0.12SD D T

S

IV V VI

⎛ ⎞− = = −⎜ ⎟

⎝ ⎠1 2 1D DV V+ = 2 0.44 VDV = 1 0.56 VDV =

16 0.56 / 0.0261 210 0.22 A=D DI e Iµ−= =

The diode equations can be written as:

from which

Using KVL, we get from which and

5Jose E. Schutt‐Aine ‐ ECE 442

( )µ ⎡ ⎤= −⎣ ⎦D ox GS T DSWI C V V VL

( )−DS GS TV V VCox: gate oxide capacitanceµ: electron mobilityL: channel lengthW: channel widthVT: threshold voltage

MOS – Triode Region - 1

3.9ε ε= =ox o

oxox ox

Ct t

6Jose E. Schutt‐Aine ‐ ECE 442

( ) 212

µ ⎡ ⎤= − −⎢ ⎥⎣ ⎦D n ox GS T DS DS

WI C V V V VL( )< −DS GS TV V V

>GS TV V

– Charge distribution is nonuniform across channel– Less charge induced in proximity of drain

MOS – Triode Region - 2

7Jose E. Schutt‐Aine ‐ ECE 442

MOS – Active Region

Saturation occurs at pinch off when ( )= − =DS GS T DSPV V V V

( )2

2µ= −D n ox GS T

WI C V VL

( )DS GS TV V V> −

>GS TV V

(saturation)

8Jose E. Schutt‐Aine ‐ ECE 442

PUN conducts when inputs are low and consists of PMOS transistors

PDN consists of NMOS transistors and is active when inputs are high

• PDN and PUN utilize devices– In parallel to form OR functions– In series to form AND functions

• Two Networks– Pull-down network (PDN) with NMOS– Pull-up network (PUN) with PMOS

CMOS Logic Gate Circuits

9Jose E. Schutt‐Aine ‐ ECE 442

Pull-Down Networks

Y A B= + Y AB=

10Jose E. Schutt‐Aine ‐ ECE 442

Pull-Up Networks

Y A B= + Y AB=

11Jose E. Schutt‐Aine ‐ ECE 442

1PMOS

1NMOS

2NMOS-Parallel

2NMOS-Series

2PMOS-Series

2PMOS-Parallel

Symbol

# DevicesPUN

# DevicesPDN

TruthTable

BasicFunction INVERTER NOR NAND

Basic Logic Function

12Jose E. Schutt‐Aine ‐ ECE 442

• Key features– When PDN switch is on, PUN switch is off

and vice versa

– Conditions for being on and off are complementary

Pull-Down and Pull-Up Functions

Pull-up network (PUN)

Pull-down network (PDN)

13Jose E. Schutt‐Aine ‐ ECE 442

Pull-Down and Pull-Up

Truth Tables

PDN-parallelNMOS PUN-series

PMOS

DPY A B= + USY AB=

14Jose E. Schutt‐Aine ‐ ECE 442

2. Emitter Bias

BJT Bias

Provides good stability with respect to changes in β with temperature

15Jose E. Schutt‐Aine ‐ ECE 442

Common Source MOSFET Amplifier

Bias is to keep MOS in saturation region

16Jose E. Schutt‐Aine ‐ ECE 442

Small-Signal Equivalent Circuit for MOS (device only)

Common Source MOSFET Amplifier

( )2'1

2D n GS T

WI k V V

L= −

2

GS GSQ

D Dm

GS effV V

I Ig

V V=

∂= =∂

GS T effwhereV V V− = /mg is proportional to W L=

'2 /m n Dg k W L I=

Which leads to

17Jose E. Schutt‐Aine ‐ ECE 442

To calculate rds, account for λ

[ ]21 1

2GS GSQ

DSds

D DPV Vox GS T

Vr

WI IC V VL

λλµ=

∂= = =∂ −

( )2'1

2DP n GS T

WI k V V

L= −

rds, accounts for channel width modulation resistance.

MOSFET Output Impedance

18Jose E. Schutt‐Aine ‐ ECE 442

Source Follower ConfigurationSince source is not tied to the substrate, we need to model the body effect. Note: substrate is always tied to ground.

19Jose E. Schutt‐Aine ‐ ECE 442

Common Emitter (CE) Amplifier

Bias: Choose R1 & R2 to set VB VE is then set. Choose REto set IE~IC. Quiescent point of Vout will be determined by RC. Emitter is an AC short.

20Jose E. Schutt‐Aine ‐ ECE 442

Hybrid-π Incremental Model for BJTs

rπ: input resistance looking into the baserx: parasitic series resistance looking into base – ohmic base resistancegm: BJT transconductancero=rce: output collector resistance related to the Early effect

21Jose E. Schutt‐Aine ‐ ECE 442

Hybrid-π Parameters

tanC

C Cm

BE TI cons t

i Igv V

=

∂= =∂

:b

vr is defined as riπ

π π =

mb

g vSince i π

β=

m

then rgπβ

=

A Ace o

C B

V Vr r

I Iβ= = =

is associated with the Early effectce or r=

( )1 er rπ β= +

me

grα

=

mg rπβ =

Can show that

1 1m

e

gr rπ

+ =

22Jose E. Schutt‐Aine ‐ ECE 442

m Dg R

DR

1

mg∞

1− m Dg R

∞

DR

CS CG SF

Avo

Rin

Rout

MOS Topologies - Ideal

1

mg

23Jose E. Schutt‐Aine ‐ ECE 442

m Cg R

CR

1rπ

β +

/( 1)ER rπ β +

( )1Er Rπ β+ +

1m Cg R−

rπ

CR

CE CB EF

Avo

Rin

Rout

BJT Topologies - Ideal

24Jose E. Schutt‐Aine ‐ ECE 442

Given VBEON=0.6V, find the gain for the circuit shown

1.5BQV V=

Example

1 2

0.9 0.9 0.91E

E E

I mAR R k

= =+ Ω

1.5 0.6 0.9EQV V V V= − =

25Jose E. Schutt‐Aine ‐ ECE 442

1CMB

E e

RA withR rα α= −+

26 28.80.9

Te

E

VrI

= = = Ω

0.9 12 0.9 10 3C outQI mA V V V⇒ = − × =

AC analysis: RE2 is shorted and RE=RE1=100Ω. Since β is not known, use:

10,000 77.5100 28.8MBA = − = −

+

Example (Cont’)

77.5MBA = −