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ECE 7366 Advanced Process Integration

Set 8: Junctions and Contacts

Dr. Wanda Wosik

Text Book: B. El-Karek, “Silicon Devices and Process Integration”

2 Leakage in sub 32/28nm devices Yuri Erokhin, IWJT, 2012

Arghavani&M’saad, SST

Scaling Issues Related to Source and Drain Regions

Extensions: Ultra shallow junctions (USJ) with low Rs

Doping: Ion Implantation Epi, Plasma DopingMonolayer Doping

Annealing: Flash, Laser (no melt), mwavesCompatibility with high K/Metal gate

Contacts: Silicides with low contact resistance Rco and low resistivity

Si or SiGe consumption and device compatibility: Small avoid leakage currentsDual workfunction for NMOS and PMOS with one silicide only

Annealing: Low T Compatibility with high K/Metal gateLine widths and structures control

Fabrication of junctions and contacts must be optimized to limit defects leakage

Parasitic resistances

Defect Free Junctions/Contacts

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• Flash annealing - ramp to intermediate T (≈ 800 ˚C) then msec flash to high T (≈ 1300 ˚C).

• Recent flash annealing results with boron are much better than RTA. = flash data points

• Annealing must ensure shallow depths but also dopant activation and defects annealing.

Overall, the shallow junction problem seems manageable through process innovation: both doping/deposition/implantation and annealing.

Furnace, T= 550-700°C Solid Phase Epitaxial Regrowth (SPER)

RTA, 1000-1100°C,, t<10s

Spike Anneal, 1000-1100°C, ~1s

Flash, 1100-1300°C, t<1ms

Future Projections - Shallow Junctions

Laser, 1100-1300°C, t<1ms

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Junction-Contact Integration in Scaled Down Devices

The main component of parasitic resistance is due to contact/junction interface limited dopant concentrations at the surface (solubility and activation), high energy barrier. We will see that junction contact integration also important in nonplanar bulk and SOI devices.

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Real Numbers and Real Constrains for Junctions/Contacts from ITRS

6R. Jammy, Sematech

MLD

Cryo II

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3 Main Sources Areas Of Device Leakage • Gate Leakage

– High-k/Metal Gate reduce gate leakage by >1,000x

• Source Drain Leakage– Engineer the location of

EOR damage to reduce junction leakage

• Gate Edge Leakage– Extension/HALO junction

leakage influenced by band to band tunneling, HALO dose, extension abruptness and shallow EOR damage

Borland et al. J.O.B. Technology (Strategic Marketing, Sales & Technology)

Surdeanu et al, Philips/IMEC, SSDM 2004, Sept. 04

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Resistance is Important so is the Leakage (defects)

Borland et al., SST

Preamorphization (Ge, Si) before ion implantation• Alleviates channeling effects• Improves dopant activation after annealing• Typically causes End of Range Defects (EOR)

Optimization of Implantation:• Cryogenic II to prevent in-situ annealing• Molecular implants = clusters of ions• Control the location of EOR with respect to

junction depths

C implant 5keV, 1015cm-2

Y. Erokhin, IWJT 2012

• Crystal degradation and trapping of dopants at EOR

• Recrystallization depends on location for given annealing technology

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Cryogenic Ion Implantation (high dose C or Si) for P-doped layers

Defect Engineering: The goal is to have high activation, shallow P-doped layers w/o crystallographic defects both in Si and strained Si-C layers.

Itokawa et al. IEEE 2012

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Cryo-C co-ImplantsEffects in P & B Doping

Yako et al. IWJT, 2011

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Leakage: Ion Implantation and Annealing

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Resistance: Ion Implantation and Annealing

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J. Appl. Phys. 111, 044508 (2012)

B concentration profiles for in situ doped and additionallyB implanted poly-Si films with various annealing conditions. Solid lines represent simulated profiles

Poly_silicon SourcesB Segregation To Grain Boundaries And

Diffusion In Polycrystalline Si

Elevated (Raised) S/DSimilar concept will be used with silicides

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PMOS device final 2D activated B profile simulation of B beam-line implant with an energy/dose of 2keV/5°—1015/cm2.

NMOS device final 2D activated As profile simulation of As beam-line implant with an energy/dose of 10keV/8°—1015/cm2.

Raised S/D

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Contacts to S/D Regions: Silicides with Low Rco

Rectifying vs Ohmic Contacts

Work function in metals fm

Barrier height

Ohmic contact

Schottky diode

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Ideal and Experimental Barriers of M-S Contacts

4.05eV So the barrier height fb for Al-n-Si should be about 0.2 eV but when measured it is much higher≅0.5 – 0.9 eV

Surface states at the M-Si interface

Very thin interfacial layer (may due to a physical layer)

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Surface Charges Present at the Si Surface

Large charge concentrations due to surface states in Silicon

Zero charges

Negative charges

Positive charges

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Fermi Level Pinning at the Charge Neutrality Distribution Point

Barrier height becomes independent on metal used for contact but instead it depends on silicon charges (density of states=Dit).

or

Ideal Schottky

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Image Force Barrier Lowering

Image charge in the metal of opposite sign is created by an approaching electron - image potential

Barrier at the M-Si interface is lowered by Df

Example: E=105V/cm, xm≅1.75 nm, and Df≅35 mVThe barrier increases with + bias and decreases with – bias.

Built-in voltage

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Current Voltage Characteristics

Forward Bias decreases the barrier at the semiconductor site

A – Richardson constant; use m*For electrons A* ≅120 A/cm2K2

For holes A* ≅32 A/cm2K2

[A/cm2]

[A/cm2K2]

where

Thermionic emission depends on barrier height

Under the applied bias VF

[A/cm2]

Electrons from metalElectrons from Si

Barrier height important!

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Current Voltage Characteristics

•Reverse Bias • increases the barrier at the semiconductor sitejR=-js (like in a p-n junction)

• decreases the barrier height fB by (=2Df Exm)• so the reverse current:

To reduce the field effect use guard rings

To reduce parasitic resistance use n+ buried layer

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Comparison Between Schottky Diode and p-n Junction

SBD is majority-carrier non-injecting diodeHigh switching speed device

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Comparison Between Schottky Diode and p-n Junction

Minority carrier injection and charge storage at high + bias voltages:

Band bending at Si surface – holes>electrons (inversion) may be important at high currents (seen when voltage drops on resistance). Minority carrier current increases

Charge storage of minority carriers reduces the switching speed

s is the surface recombination velocity beneath the contact

Faster speed for the Schottky diodes and smaller forward bias voltage

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Capacitance-Voltage Measurements

As for p-n junctions C depends on depletion thickness. Barrier extracted

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Ohmic ContactsR

Practical realization

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Contacts - Electrical Parametersthermionic emission

Schottky = rectifying

Tunneling

Surface states in Si pin F-level deep in the E-gap no metal gives fB

for n – Si contact resistance & rectifying contact

thermionic emission

Tunneling contact

Thickness of depletion = tunneling layer

2.5 nmresults fromNd=6. 1019 cm-3

contact area

Depends on metal/semiconductor

Rc[Ω]=r[Ωcm]/A[cm2]

c|1019cm-3=5.9•10-2Ωcm2

c|1020cm-3=6.7•10-6Ωcm2

c≈10-9Ωcm2 will be needed

Role of concentration

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Specific Interface Contact Resistance

For thermionic emission dominating contact

For tunneling mechanism dominating contact

Where E00 is an energy characteristic of the tunneling probability i.e. dominates when E00>kT N≅3e19cm-3

Ex. fB≈0.57eV rc≈ 10Wcm2

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Influence of the Dopant Concentration on Specific Contact

Resistance

ITRS specifies rc at about 10-9 Wcm2

http://www.itrs.net/links/2012ITRS/Home2012.htm

For rc ≈ 10-8Wcm2 ND≥1021cm-3

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Specific Contact Resistivity Decreases with Doping Levels and Barrier Heights

P-type SiN-type Si

S. Swirhun, 1987

Barrier heights larger for n- vs p-type

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Contact Resistance

Current crowding

Example: Rc=10-8 Wcm-2 and 0.25x0.25 µm2 results in 16 .W

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Electrical Measurements of Contacts

gives overestimation( RC ) of thecontact properties

Low resistance

KELVIN BRIDGE

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Historical Development and Basic Concepts

Contacts

• Early structures were simple Al/Si contacts.• Highly doped silicon regions are necessary to insure ohmic, low resistance contacts.

(2)

• Tunneling current through a Schottky barrier depends on the width of the barrier and hence ND. • In practice, ND, NA > 1020 cm-3 are required.

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Scaling: Contacts and Interconnects

rεGlobal

Global

Self - aligned

Self - aligned

Self - aligned

50% delay from interconnectsEarlier:15-20%, then 30-40% (delay increases with scaling)

Contacts between metal/junction using silicides

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Aluminum Metallization

high compressive stress in Al during annealing

large

All silicides give self-aligned contacts contact area R

passive

Al contact: SiO2 native reduced good ohmic! Al2O3 forms, very stable adhesion to Si O2

Qit

duringannealing@ 450 0C H formation

High SS of Si in Al 0.5% 4500CHigh Si diff in Al SPIKES!in local spots

Al - 2-3 µm junctions only!

Ti as asacrificedBarrier TiSi2 &TiN (=diffusionbarrier)

Better solution

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Equilibrium phase diagram of the Si-Al System Spikes Generated In Al Contacts

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Silicides and Polycides

gate

contacts

local interconnects (require a-Si deposition)

SALICIDE PROCESS

sputtering

T (~ 600 0C )C 49 Ti Si2 - high resistive

T ( > 800 0C )C 54 Ti Si2 - low resistive Larger grains

Ti also against electromigration

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Silicides

Good adhesion

Problems :adhesion stability

stress

large

SILICON CONSUMPTION

striped

CoSi2 does not cause problems with resistivity for very narrow lines

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For 1 nm of metal (Ti, Co, Ni):TiSi2 - 2.27 nm Si usedCoSi2 - 3.64 nm SiNiSi -1.83 nm Si

Bulk Device

Critical: Sharp profiles, Small depths

Silicide

Junction/contact integration: small Rs of the contact causes Si consumption thus junction degradation (leakage)

Ex. xTiSi2 = 360 - 800 Å Rs = 4.5 - 1.7 Ω/sq. , Si consumption ≈ xTiSi2, > xCoSi2 , < , xNiSi

20-30 nm minimum

•Short Extension lengths for high transconductance (10 - 20 nm)

•Shallow Deep junctions for small Drain Induced Barrier Loweringxjdeep ≈70 -50 nm)

Surface roughness - due to excess silicidation, phase & structure differences – must be avoided to limit

leakage currents and SB height nonuniformity (ex. small contact sizes).

Flat interfaces for CoSi2 and NiSi possible

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Evolution of Silicides in CMOS

Main Problems:TiSi2: • Sheet resistance

• oxidation (high T)• narrow lines – phase transition,

stress, knock on oxygen, surface damage (RIE)

• leakage (metal diffusion)• bridging b/w S/D and G• thermal stability – agglomeration• TDDB – metal diffusion to G oxide

CoSi2: • Large Si consumptionNiSi• Instability at elevated T ~700°C –

NiSi2= larger Si consumption and higher resistance

NiSi is currently used with modifications by: dopant segregation, complementary implantation to adjust Schottky barriers for e- and h+.

Iwai, 2002

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TEM images of 0.1 mm TiSi , NiSi, and CoSi lines.Relationship between crystal structure and TiSi line width.

TiSi2 and its Successors

Iwai, 2002

CoSi2 and NiSi scale with line widths

42TEM images of cross-section of TiSi , NiSi, and CoSi lines.

Mechanisms of Silicide Formation and Devices (gates)

Iwai, 2002

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TiSi2 Salicide Formation

Si is the diffuserfor CoSi2 TiSi2

Creep - up

short G - S

Less lateral encroachment

Consumption of Silicon Large :

Ti Si2 = 138 nm from Ti = 55 nmSi consumed = 125 nm

fast diffusion

Linear coefficient = fast reaction

conductive

Growth as in the oxidation process: parabolic and linear

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• Some front-end models have also been applied to back-end processing.

• Silicide formation is often modeling using the Deal-Grove linear-parabolic model.

(7)

• Simulation of TiSi2 formation using FLOOPS [11.32] on a 0.35 m wide gate structure. Left: before formation anneal step. Right: after formation anneal step: 30 sec at 650˚C in a nitrogen atmosphere

TiSi2 Salicide Formation

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Silicide Formation and Scaling of Devices

650 0C/ 30” Ar

@ the top of the oxide spacer

TiN growth:20% of TiSi2 parameters

32.5 nm Ti 44 nm Si

50 nm TiSi2 + 27 nm TiN

Not all Ti consumed

See Deal & Grove

Linear / Parabolic growth

Anneal now in N2

2µm wide channel

0.35µm wide channel

48 nm TiSi2 from 43 nm Si

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47Iwai, 2011

Kittl et al., 2008

PMOS – challenge - P+ (100) Si, 310°C RTP

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NiSi2 technology suppresses leakage current:• Flat interface and no Si consumption• No defects in the Si substrate

Iwai, 2011

Flat NiSi interface - from a NiSi2 Source

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Chang Y. Kang, Sematech Symp., Korea 2011

50Chang Y. Kang, Sematech Symp., Korea 2011

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Contacts Optimization

• Interface Engineering to reduce Schottky Barrier Height• Co-implantation (dopants Sb, As, B or other elements

ex.for S DfB~0.5 eV, Al ~0.4eV, and Nitrogen)

• Dipole Engineering• Ni-Alloys (for Si – silicides and for SiGe/Ge – germanides)• Raised (diffused) S/D show superior properties

Ioff/Ion than Schottky S/D – in FinFETs (discussed later).

Chang Y. Kang, Sematech Symp., Korea 2011Hobbs; Jammy, Sematech Symp., Taiwan,2010

Sb

NiPtSi + charged Sb at the interface

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Implantation was done prior to silicidation

Yuri Erokhin, IWJT, 2012

SBH modification by PAI and Selected co-Implantation Steps

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THE FUTURE OF BACKEND TECHNOLOGY

• Contacts will be now connected to interconnects – more challenges!

• Reduce metal resistivity - use Cu instead of Al.• Aspect ratio - advanced deposition, etching and planarization methods.• Reduce dielectric constant - use low-K materials.