Post on 14-Dec-2015
ECE 448 – FPGA and ASIC Design with VHDL George Mason University
Lab 1
Introduction to Aldec Active HDL
Implementing Combinational Logic in VHDL
Example 1: MLU
Introduction to Aldec Active-HDL
MLU Block Diagram
B
A
NEG_A
NEG_B
IN0
IN1
IN2
IN3 OUTPUT
SEL1
SEL0
MUX_4_1
L0L1
NEG_Y
Y
Y1
A1
B1
MUX_0
MUX_1
MUX_2
MUX_3
Experiment 1
Problem 1
ALU of PIC Microcontroller
Pertinent Components of PIC
Working Register7 0W
000000000100010
11111
777
7
000
0
Register File(32 Registers)
Address
00011 7 000100 7 0
STATUS
00101 7 000110 7 0
00111 7 0
8 Special FunctionRegisters
01000 7 0
24 General PurposeRegisters
Addressing Modes
Immediate mode
ANDLW H’6C’
Direct mode
ANDWF H’12’, 0
W & 0x6C W
W & (0x12) W
Assembly language vs. Machine Code
Assembly language
mnemonic [operands]
ANDLW H’6C’
Machine code
‘000101’ ‘010010’
opcode [operands]
ANDWF H’12’, 0
‘1110’ ‘01101100’
Status Register
STATUS 07
Z DC C
Carry/BorrowDigit Carry (3rd4th bit)ZeroPower-downTime-out
Program Page Preselect
Reserved
Definition of the Status Register Flags (1)
Z = 1 if result = 0 0 otherwise
Zero flag - Z zero result
C = 1 if result > MAX_UNSIGNED or result < 0 0 otherwise
where MAX_UNSIGNED = 28-1 for 8-bit results
Carry flag - C out-of-range for unsigned numbers
Definition of the Status Register Flags (2)
DC = 1 if carry from bit 3 to bit 4 (ADDWF) orno borrow from bit 4 to 3 (SUBWF)
0 otherwise
Digit Carry flag – DC Carry / Borrow between MSB of first hex digit and LSB of second
111 1 0010 0110+ 0001 1100 0100 0010
0010 1110 - 0001 1100 0001 0010
DC = 1
Logic Instructions
1. AND ANDWF W & RF W or RF
ANDLW W & L W
2. Inclusive OR
IORWF W | RF W or RF
IORLW W | L W
3. Exclusive ORXORWF W RF W or RFXORLW W L W
4. Ones ComplementCOMF RF RF
DIR
Z C DC
DIR
IMM
DIR
– –
– –
– –
– –
DIR
IMM
IMM
Arithmetic Instructions
1. AdditionADDWF W + RF W or RF
2. Subtraction SUBWF RF – W W or RF
DIR
3. IncrementINCF RF + 1 RF
4. DecrementDECF RF - 1 RF
DIR
Z C DC
DIR
DIR
– –
– –
Shifts and Rotation Instructions
1. Rotate Left Through Carry RLF
2. Rotate Right Through Carry RRF
3. Swap Nibbles SWAPF RF [7:4] W [3:0] or RF [3:0]
RF [4:0] W [7:4] or RF [7:4]
DIR
DIR
Z C DC
DIR
– –x
– –x
– – –
07
. . .C
07 C. . .
Instruction Summary
Example 2
Mini ALU
opcode
A
B
M
RMini ALU
4
4
4
4
4
Mnemonic Operation Opcode
ADDAB R= A + B 0000
ADDAM R = A + M 0001
SUBAB R = A - B 0010
SUBAM R = A - M 0011
NOTA R = NOT A 0100
NOTB R = NOT B 0101
NOTM R = NOT M 0110
ANDAB R = A AND B 0111
ANDAM R = A AND M 1000
ORAB R = A OR B 1001
ORAM R = A OR M 1010
XORAB R = A XOR B 1011
XORAM R = A XOR M 1100
Block diagram
Example 3
Variable Rotator
Function
C = A <<< B
A – 4-bit data inputB – 2-bit rotation amount
Interface
4
4
2
A
B
C
Block diagram
C
Fixed Shifts in VHDL
A(3)A(2) A(1) A(0)
A(3) A(2) A(1)
A>>1
A_shiftR <= ‘0’ & A(3 downto 1);
‘0’
‘0’
Arithmetic Functions in VHDL (1)
To use arithmetic operations involving
std_logic_vectors you need to include the
following library packages:
library ieee;use ieee.std_logic_1164.all;use ieee.STD_LOGIC_UNSIGNED.ALL;
Arithmetic Functions in VHDL (2)
You can use standard +, - operators
to perform addition and subtraction:
signal A : STD_LOGIC_VECTOR(3 downto 0); signal B : STD_LOGIC_VECTOR(3 downto 0); signal C : STD_LOGIC_VECTOR(3 downto 0);
……
C<= A + B;