Post on 25-Jul-2020
ECE 154A Introduction to Computer ArchitectureComputer Architecture
Fall 2012
Dmitri Strukov
Lecture 4: Arithmetic and Data Transfer Instructions
AgendaAgenda
• Review of last lectureReview of last lecture
• Logic and shift instructions
d/ i i• Load/store instructions
Last LectureLast Lecture
CPU Overview
… with muxes
Assembly LanguageAssembly Language
• Basic job of a CPU: execute lots of instructionsBasic job of a CPU: execute lots of instructions• Instructions are the primitive operations that the CPU may
execute
• Different CPUs implement different sets of instructions• Instruction Set Architecture (ISA) is a set of instructions a
particular CPU implements
• Examples: Intel 80x86 (Pentium 4), IBM/Motorola Power PC (Macintosh), MIPS, Intel IA64, ARM
Below the Programtemp = v[k];
$ ($ )
High Level Language Program (e.g., C)
Compiler
temp = v[k];
v[k] = v[k+1];
v[k+1] = temp;
lw $t0, 0($2)lw $t1, 4($2)sw $t1, 0($2)sw $t0, 4($2)
Assembly Language Program (e.g.,MIPS)
Compiler
AssemblerMachine Language
Program (MIPS)
Assembler
Machine
0000 1001 1100 0110 1010 1111 0101 10001010 1111 0101 1000 0000 1001 1100 0110 1100 0110 1010 1111 0101 1000 0000 1001 0101 1000 0000 1001 1100 0110 1010 1111
Hardware Architecture Description (e.g., block diagrams)
Machine Interpretation
0101 1000 0000 1001 1100 0110 1010 1111
g )
Architecture Implementation
Logic Circuit Description(Circuit Schematic Diagrams)
MIPS SyntaxMIPS Syntax• Instruction Syntax:[Label:] Op‐code [oper. 1], [oper. 2], [oper.3], [#comment][ ] p [ p ], [ p ], [ p ], [ ]
(0) (1) (2) (3) (4) (5)– Where
1) operation name2,3,4) operands5) comments0) label field is optional, will discuss later
– For arithmetic and logic instruction2) operand getting result (“destination”)3) 1st operand for operation (“source 1”)4) 2nd d f i ( 2”4) 2nd operand for operation (source 2”
• Syntax is rigid– 1 operator, 3 operands– Why? Keep hardware simple via regularity
Assembly Variables: RegistersAssembly Variables: Registers
• Unlike HLL like C or Java assembly cannot useUnlike HLL like C or Java, assembly cannot use variables– Why not? Keep hardware simple– Why not? Keep hardware simple
• Assembly Operands are registersLi i d b f i l l i b il di l– Limited number of special locations built directly into the hardware
O ti l b f d th– Operations can only be performed on these
– Benefit: Since registers file is small, it is very fast
Assembly Variables: RegistersAssembly Variables: Registers
• By convention, each register also has a name to make it easier to code
• For now:$16 ‐ $23 $s0 ‐ $s7$16 $23 $s0 $s7(correspond to C variables)$8 ‐ $15 $t0 ‐ $t7( )(correspond to temporary variables)
Will explain other 16 register names later
• In general, use names to make your code more readable
Procedure results
Reserved for assembler use $0 $1 $2
0
$zero $at $v0
3 2 1
A 4-byte word sits in consecutive memory addresses
di t thRegister
ConventionsSaved Procedure arguments
Procedure results $3 $4 $5 $6 $7
$8 $t0
$a0
$a2
$v1
$a1
$a3
10
according to the big-endian order (most significant byte has the lowest address)
Temporary values
$8 $9 $10 $11 $12 $13
$t0
$t2
$t4
$t1
$t3
$t5
When loading a byte into a register, it goes in the low end B t
Byte numbering: 0 1 2 3
Saved
$13 $14 $15 $16 $17 $18
$t6
$t5
$t7
$s0
$s2
$s1
in the low end Byte
Word
Doublew ord
Operands
across procedure
calls
$18 $19 $20 $21 $22 $23
$s2
$s4
$s6
$s3
$s5
$s7 A doublewordMore
temporaries
Global pointer
Reserved for OS (kernel)
$24 $25 $26 $27 $28
$t8
$t9
$gp
$k0
$k1
A doubleword sits in consecutive registers or memory locations according to the big-endian order (most significantStack pointer
Frame pointer Return address
Saved $29 $30 $31
$sp
$fp
$ra
(most significantword comes first)
Instruction formats
R‐format:
op rs rt rd shamt funct6 bits 6 bits5 bits 5 bits 5 bits 5 bits
op rs rt constant or address
6 bit 5 bit 5 bit 16 bit
I‐format:
6 bits 5 bits 5 bits 16 bits
J‐format:
op address
6 bits 26 bits
ECE 15B Spring 2011
Instruction formats
Why stick to fixed formats?
rigid and just few formats + fixed instruction size simple decoding faster clock cyclesize simple decoding faster clock cycle ( hopefully faster execution)
note that it is always a tradeoff: too rigid and simple instruction set could be result in thesimple instruction set could be result in the large number of instructions
several visual example later…
Arithmetic InstructionsArithmetic Instructions
Addition and Subtraction of IntegersAddition and Subtraction of Integers• Addition in assembly
l– Example:add $s0, $s1, $s2 (in MIPS)• Equivalent to: a = b + c (in C)q ( )• Where MIPS registers $s0, $s1, $s2 are associated with C variables a, b, c
• Subtraction in Assembly• Subtraction in Assembly– Example
Sub $s3, $s4, S5 (in MIPS)Sub $s3, $s4, S5 (in MIPS)• Equivalent to: d = e ‐ f (in C)• Where MIPS registers $s3, $s4, $s5 are associated with C variables d e fvariables d, e, f
Addition and Subtraction of IntegersAddition and Subtraction of Integers
• How do we do this?How do we do this?f = (g + h) – (i + j)
Use intermediate temporary registersUse intermediate temporary registers
add $t0, $s1, $s2 #temp = g + h
dd $t1 $ 3 $ 4 #t I + jadd $t1, $s3, $s4 #temp = I + j
sub $s0, $t0, $t1 #f = (g+h)‐(i+j)
ImmediatesImmediates
• Immediates are numerical constantsImmediates are numerical constants• They appear often in code, so there are special instructions for themspecial instructions for them
• Add immediate:addi $s0 $s1 10 # f= g + 10 (in C)addi $s0, $s1, 10 # f= g + 10 (in C)
– Where MIPS registers $s0 and $s1 are associated with C variables f and g
– Syntax similar to add instruction, except that last argument is a number instead of register
R‐format Example
op rs rt rd shamt funct
6 bi 6 bi5 bi 5 bi 5 bi 5 bi
add $t0, $s1, $s2
6 bits 6 bits5 bits 5 bits 5 bits 5 bits
note the order!$ , $ , $(green card)
special $s1 $s2 $t0 0 add
0 17 18 8 0 320 17 18 8 0 32
000000 10001 10010 01000 00000 100000
000000100011001001000000001000002 = 0232402016
L i d ShifLogic and Shift Instructions
Bitwise operationsBitwise operations
• Up until now, instructions have been:Up until now, instructions have been:– Arithmetic (e.g. add, sub, addi)
• All these instructions view contents of registers as a single quantity (such as signed or unsigned integer)
• New Perspective – View contents of register as 32 individual bits rather than as a single 32 bit number Introduce two new classes of instructions:– Introduce two new classes of instructions:
• Logical operations• Shift Instructions
Logical OperationsLogical Operations• Instructions for bitwise manipulation
Operation C Java MIPSShift left << << sll
Shift right >> >>> srl
Bitwise AND & & and, andi
iBitwise OR | | or, ori
Bitwise NOT ~ ~ nor
Useful for extracting and inserting groups of bits in a wordof bits in a word
AND OperationsAND Operations• Useful to mask bits in a word
Select some bits clear others to 0– Select some bits, clear others to 0
and $t0, $t1, $t2
0000 0000 0000 0000 0000 1101 1100 0000$t2
0000 0000 0000 0000 0011 1100 0000 0000$t1
0000 0000 0000 0000 0000 1100 0000 0000$t0 0000 0000 0000 0000 0000 00 0000 0000$t0
OR OperationsOR Operations• Useful to include bits in a word
Set some bits to 1 leave others unchanged– Set some bits to 1, leave others unchanged
or $t0, $t1, $t2
0000 0000 0000 0000 0000 1101 1100 0000$t2
0000 0000 0000 0000 0011 1100 0000 0000$t1
0000 0000 0000 0000 0011 1101 1100 0000$t0 0000 0000 0000 0000 00 0 00 0000$t0
NOT OperationsNOT Operations• Useful to invert bits in a word
Change 0 to 1 and 1 to 0– Change 0 to 1, and 1 to 0
• MIPS has NOR 3‐operand instructionb ( b )– a NOR b == NOT ( a OR b )
nor $t0, $t1, $zero Register 0: always
0000 0000 0000 0000 0011 1100 0000 0000$t1
read as zero
$
1111 1111 1111 1111 1100 0011 1111 1111$t0
Shift OperationsShift Operations
op rs rt rd shamt funct
• shamt: how many positions to shift • Shift left logical (SLL)
6 bits 6 bits5 bits 5 bits 5 bits 5 bits
• Shift left logical (SLL)– Shift left and fill with 0 bits– sll by i bits multiplies by 2i
h f h l l ( )• Shift right logical (SRL)– Shift right and fill with 0 bits– srl by i bits divides by 2i (unsigned only)s by i bits divides by (unsigned only)
• Shift right arithmetic (SRA)– Shift right and fill emptied bits by sign extending
• Note that shamt (immediate value) is only 5 bits• Note that shamt (immediate value) is only 5 bits
Uses for Shift InstructionsUses for Shift Instructions
• Very convenient operation to extract group ofVery convenient operation to extract group of bits (e.g. one byte) within a word (e.g. think of operations on 8‐bit pixels or 8‐bit characters)operations on 8 bit pixels or 8 bit characters)
• For example, suppose we want to get bits 8 to 15 from $t0 The code below will do the job15 from $t0. The code below will do the job
sll $t0, $t0, 16
srl $t0, $t0, 24 $ , $ ,
Uses for Shift InstructionsUses for Shift Instructions
• Since shifting is faster than multiplication, a good S ce s t g s aste t a u t p cat o , a goodcompiler (or a good programmer for that matter) usually notices when C code multiplies by a
f d l h fpower of 2 and compiles it to a shift instruction
For example:a = a*8; (in C)
would compile to: sll $s0, $s0, 3 (in MIPS)
Load and Store Instructions
Memory OperandsMemory Operands
• Main memory used for composite data– Arrays, structures, dynamic data
• To apply arithmetic operations– Load values from memory into registersy g– Store result from register to memory
• Memory is byte addressed– Each address identifies an 8‐bit byteEach address identifies an 8 bit byte
• Words are aligned in memory– Address must be a multiple of 4
• MIPS is Big Endian• MIPS is Big Endian– Most‐significant byte at least address of a word– c.f. Little Endian: least‐significant byte at least address
Data Transfer: Memory to RegisterData Transfer: Memory to Register
• MIPS load Instruction Syntaxlw register#, offset(register#) (1) (2) (3) (4)
Where1) operation name2) register that will receive value3) numerical offset in bytes4) register containing pointer to memory
lw – meaning Load Word32 bits or one word are loaded at a time
Data Transfer: Register to MemoryData Transfer: Register to Memory
• MIPS store Instruction Syntaxsw register#, offset(register#) (1) (2) (3) (4)
Where1) operation name2) register that will be written in memory3) numerical offset in bytes4) register containing pointer to memory
sw – meaning Store Word32 bits or one word are stored at a time
Memory Operand Example 1Memory Operand Example 1
• C code:C code:g = h + A[8];
g in $s1 h in $s2 base address of A in $s3– g in $s1, h in $s2, base address of A in $s3
• Compiled MIPS code:– Index 8 requires offset of 32
• 4 bytes per word
l $t0 32($ 3) # l d dlw $t0, 32($s3) # load wordadd $s1, $s2, $t0
offset base register
Memory Operand Example 2Memory Operand Example 2
• C code:C code:A[12] = h + A[8];
h in $s2 base address of A in $s3– h in $s2, base address of A in $s3
• Compiled MIPS code:– Index 8 requires offset of 32
lw $t0, 32($s3) # load worddd $t0 $ 2 $t0add $t0, $s2, $t0sw $t0, 48($s3) # store word
Registers vs. MemoryRegisters vs. Memory
• Registers are faster to access than memoryRegisters are faster to access than memory• Operating on memory data requires loads and storesstores– More instructions to be executed
• Compiler must use registers for variables asCompiler must use registers for variables as much as possible– Only spill to memory for less frequently used y p y q yvariables
– Register optimization is important!
Byte/Halfword OperationsByte/Halfword Operations
• MIPS byte/halfword load/store– String processing is a common case
lb rt, offset(rs) lh rt, offset(rs)
– Sign extend to 32 bits in rtlbu rt, offset(rs) lhu rt, offset(rs)
– Zero extend to 32 bits in rtsb rt, offset(rs) sh rt, offset(rs)
– Store just rightmost byte/halfword
Why do we need them? characters and multimedia data are expressed by less than 32
bits; having dedicated 8 and 16 bits load and store instructions results in faster operation
Two’s Compliment Representation
Unsigned Binary IntegersUnsigned Binary Integers• Given an n‐bit number
0121 00
11
2n2n
1n1n 2x2x2x2xx
Range: 0 to +2n – 1 Range: 0 to +2 1
Example0000 0000 0000 0000 0000 0000 0000 1011 0000 0000 0000 0000 0000 0000 0000 10112= 0 + … + 1×23 + 0×22 +1×21 +1×20
= 0 + … + 8 + 0 + 2 + 1 = 1110
Using 32 bits 0 to +4,294,967,295, , ,
Unsigned Binary Integers0000
0001 1111
0010 1110 0
1 15
Turn x notches counterclockwise
to add x
0011 1101 2
3
14
13 0
1 2
3
15 14
13 0100 1100
01011011
4
5 11
12 Inside: Natural numberOutside: 4-bit encoding
3
4 5
6 789
11
13 12
10 01011011
0110 1010 6
7 8
9 10
789
Turn y notches clockwise
t bt t
Schematic representation of 4‐bit code for integers in [0, 15].
1000 01111001 to subtract y
2s‐Complement Signed Integers
• Given an n‐bit number0121 0
01
12n
2n1n
1n 2x2x2x2xx
Range: –2n – 1 to +2n – 1 – 1 Range: 2 to +2 1
Example1111 1111 1111 1111 1111 1111 1111 1100 1111 1111 1111 1111 1111 1111 1111 11002= –1×231 + 1×230 + … + 1×22 +0×21 +0×20
= –2,147,483,648 + 2,147,483,644 = –410
Using 32 bits –2,147,483,648 to +2,147,483,647, , , , , ,
2s‐Complement Signed Integers
• Bit 31 is sign bitg– 1 for negative numbers– 0 for non‐negative numbers
• ( 2n – 1) can’t be represented• –(–2n 1) can t be represented• Non‐negative numbers have the same unsigned and 2s‐complement representation
• Some specific numbers– 0: 0000 0000 … 0000
1: 1111 1111 1111– –1: 1111 1111 … 1111– Most‐negative: 1000 0000 … 0000– Most‐positive: 0111 1111 … 1111
Two’s‐Complement Representation
0000 00011111 Turn x notches
With k bits, numbers in the range [–2k–1, 2k–1 – 1] represented.Negation is performed by inverting all bits and adding 1.
00011111
0010 1110
00111101
+0 +1
+2
–1
–2
Turn x notches counterclockwise
to add x
0100 1100
+3
+4
–3
–4 + _ 0
1 2
3
–1
4 5–5
–2 –3
–4
0101 1011
0110 1010
+5
+6 +7
–5
–8 –7
–6
6 7
–8
–7
Turn 16 – y notches counterclockwise to
–6
Schematic representation of 4‐bit 2’s‐complement code for integers in [ 8 +7]
1000 0111 1001 counterclockwise toadd –y (subtract y)
[–8, +7].
Signed NegationSigned Negation• Complement and add 1
Complement means 1→ 0 0→ 1– Complement means 1 → 0, 0 → 1
11111...111xx 2
x1x
2
Example: negate +2 +2 = 0000 0000 … 001022 –2 = 1111 1111 … 11012 + 1
= 1111 1111 … 111022
Sign ExtensionSign Extension
• Representing a number using more bitsp g g– Preserve the numeric value
• In MIPS instruction setaddi: extend immediate value– addi: extend immediate value
– lb, lh: extend loaded byte/halfword– beq, bne: extend the displacement
• Replicate the sign bit to the left– c.f. unsigned values: extend with 0s
• Examples: 8 bit to 16 bit• Examples: 8‐bit to 16‐bit– +2: 0000 0010 => 0000 0000 0000 0010– –2: 1111 1110 => 1111 1111 1111 1110