Digital Logic & Design Vishal Jethva Lecture 13

Digital Logic & Design

Vishal Jethva

Lecture 13

SVBITEC.WORDPRESS.COMSVBITEC.WORDPRESS.COM

Functions having multiple outputs Comparator Quine-McCluskey Method (two variations) Odd-Prime Number checker circuit

Odd Prime Number (table1)Minterm A B C D E

1 0 0 0 0 1

3 0 0 0 1 1

5 0 0 1 0 1

7 0 0 1 1 1

11 0 1 0 1 1

13 0 1 1 0 1

17 1 0 0 0 1

19 1 0 0 1 1

23 1 0 1 1 1

29 1 1 1 0 1

31 1 1 1 1 1SVBITEC.WORDPRESS.COMSVBITEC.WORDPRESS.COM

Odd Prime Number (table2)Minterm A B C D E used

1 0 0 0 0 1 3 0 0 0 1 1 5 0 0 1 0 1 17 1 0 0 0 1 7 0 0 1 1 1 11 0 1 0 1 1 13 0 1 1 0 1 19 1 0 0 1 1 23 1 0 1 1 1 29 1 1 1 0 1 31 1 1 1 1 1 SVBITEC.WORDPRESS.COMSVBITEC.WORDPRESS.COM

Minterms Variable removed used

1,3 2 1,5 4 1,17 16 3,7 4 3,11 8

3,19 16 5,7 2 5,13 8

Odd Prime Number (table3)

17,19 2 7,23 16 13,29 16

19, 23 4 23,31 8

29,31 2

1,3,5,7 2,4

1,3,17,19 2,16

3,7,19,23 4,16

1 3 5 7 11 13 17 19 23 29 31

x x x x

Combinational Logic

Implementation of SOP using AND-OR Implementation of POS using OR-AND

SOP Implementation

NOTGatelevel

ANDGatelevel

OR Gatelevel

POS Implementation

NOTGatelevel

OR Gatelevel

ANDGatelevel

Design and Implementation of Digital Circuits

Function Table Simplification of Expression Implementation

Adjacent 1s Detector Circuit

SOP Implementation Directly from function table

Simplified implementation Implementation using NAND gates

Adjacent 1s Detector Function

Input Output Input Output

A B C D F A B C D F

0 0 0 0 0 1 0 0 0 0

0 0 0 1 0 1 0 0 1 0

0 0 1 0 0 1 0 1 0 0

0 0 1 1 1 1 0 1 1 1

0 1 0 0 0 1 1 0 0 1

0 1 0 1 0 1 1 0 1 1

0 1 1 0 1 1 1 1 0 1

0 1 1 1 1 1 1 1 1 1

SOP ImplementationA

SOP Expression Simplification

AB\CD 00 01 11 10

00 0 0 1 0

01 0 0 1 1

11 1 1 1 1

10 0 0 1 0

SOP based Simplified Circuit

NAND based ImplementationA

POS Implementation Directly from function table

Simplified Implementation Implementation using NOR Gates

Adjacent 1s Detector Circuit

POS ImplementationA

POS Expression Simplification

AB\CD 00 01 11 10

00 0 0 1 0

01 0 0 1 1

11 1 1 1 1

10 0 0 1 0

POS based Simplified Circuit

NOR based Implementation

Operation of Circuit

Represented through a timing diagram Timing diagram of 8 time intervals Each interval representing a new input

POS based Simplified Circuit

t0 t1 t2 t3 t4 t5 t6 t7 t8

Active low/high inputs/outputs

Active output state represented by 1 or 0 Active input state represented by 1 or 0 A bubble at output represents active low

output A bubble at input represents active low

Active low/high inputs/outputs

AND Gate OR Gate

NAND Gate NOR Gate

Active-high inputs & outputs

t0 t1 t2 t3 t4 t5 t6 t7 t8

Odd-Parity Generator Circuit

Circuit checks the 4-bit data Generates a parity bit (odd) Data + parity bit add up to odd number of

Digital Logic & Design Vishal Jethva Lecture 13

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