Post on 21-Jan-2016
description
Work Group – Basics of Systems Engineering
Mark Schaefer, Walter Vogler, Dominic Wist and Ralf Wollowski
DesiJ: A Tool for Decomposing STGs
Work Group – Basics of Systems Engineering
2
Outline
■ Motivation
□ Decomposition-based SI Logic Synthesis
□ Idea of Decomposition
■ DesiJ
□ Functionality
□ User Interface
□ Installation requirements
■ Live Demo
■ Integration into the Balsa Design Flow
Work Group – Basics of Systems Engineering
3
Outline
■ Motivation
□ Decomposition-based SI Logic Synthesis
□ Idea of Decomposition
■ DesiJ
□ Functionality
□ User Interface
□ Installation requirements
■ Live Demo
■ Integration into the Balsa Design Flow
Work Group – Basics of Systems Engineering
4
From SI Logic Synthesis to …
dtack-
ldtack-
dsr+ lds+
ldtack+lds-d-
dsr- dtack+ d+
Specification:Signal Transition Graph (STG)
State Graph
State Graph with CSC (Complete State Coding)
Next-State Functions
Gate netlist
Reachabilityanalysis
Decomposed Functions
State encoding
Boolean minimization
Logic decomposition
Technologymapping
00/000 10/00000/010
01/010 01/000 11/000
11/10001/10001/110
01/111 11/111 11/101
11/100
10/100
(dsr ldtack / lds dtack d)
dtack- dsr+
dtack- dsr+
dtack- dsr+
lds-
ldtack-
lds-
ldtack-
lds-
ldtack-
lds+
ldtack+
d+
dtack+dsr-
d-
00/0000 10/000000/0100
01/0100 01/0000 11/0000
11/100001/100001/1100
01/1111 11/1111 11/1011
11/1001
10/1001
(dsr ldtack / lds dtack d csc)
dtack- dsr+
dtack- dsr+
dtack- dsr+
lds-
ldtack-
lds-
ldtack-
lds-
ldtack- lds+
ldtack+
d+
dtack+dsr-
d-
10/0001
01/1110
csc+
csc-
lds = d + cscdtack = d
d = ldtack · csccsc = dsr · (csc + ldtack)
Work Group – Basics of Systems Engineering
5
Decomposition-based Logic Synthesis
Specification:STG
State Graph
State Graph with CSC (Complete State Coding)
Next-State Functions
Gate netlist
Reachabilityanalysis
Decomposed Functions
State encoding
Boolean minimization
Logic decomposition
Technologymapping
Specification:STG
State Graphs
State Graphs with CSC (Complete State Coding)
Next-State Functions
Gate netlist
STG decomposition
Decomposed Functions
State encoding
Boolean minimization
Logic decomposition
Technologymapping
Component STGs
Reachabilityanalysis
Petrify
DesiJ
“State Space Explosion“
Work Group – Basics of Systems Engineering
6
Idea of STG-Decomposition
VME Bus Controller
DataTransceiver
Dev
ice
BU
S
dsr
dtack
lds
ldtack
dVME BusController
DataTransceiver
Dev
ice
BU
S
dsr
dtack
lds
ldtack
d
comp 2
comp1
Work Group – Basics of Systems Engineering
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STG-Decomposition Technique
dtack-
ldtack-
dsr+ lds+
ldtack+lds-d-
dsr- dtack+ d+
(out) = { {lds, d} , {dtack} }
ldtack-
dsr+ lds+
ldtack+lds-d-
dsr- d+
dtack-
d- dtack+
d+
VME Bus Controller
DataTransceiver
Dev
ice
BU
S
dsr
dtack
lds
ldtack
d
VME BusController
DataTransceiver
Dev
ice
BU
S
dsr
dtack
lds
ldtack
d
comp 2
comp1
Elimination of irrelevant signals
(transition contraction)
Work Group – Basics of Systems Engineering
8
Results – Success Stories
Avoidance of state explosion
Effectivity and efficiency in logic synthesis
Benchmark Specification Components
FIFO 832 26 + 12 + 12 + 8 + 4 + 4 = 66
locked2 166 34+20+20 = 74
mread-8932 8932 36 + 36 + 18 + 18 + 12 + 10 = 130
Benchmark Petrify DesiJ + Petrify
2pp.arb.nch.09.csc.g 116 s 4 s
2pp-wk.12.csc.g impossible 18 s
SeqParTree-3.g 59 s 1 s
SeqParTree-5.g impossible 10 s
Work Group – Basics of Systems Engineering
9
Outline
■ Motivation
□ Decomposition-based SI Logic Synthesis
□ Idea of Decomposition
■ DesiJ
□ Functionality
□ User Interface
□ Installation requirements
■ Live Demo
■ Integration into the Balsa Design Flow
Work Group – Basics of Systems Engineering
10
Primary Function: Decomposition
Complex Specification
STG
Synthesizer
Asynchronous System Netlist
instead
Complex Specification
STG
Decomposer
(smaller)STG
Components
Synthesizer
Asynchronous Circuit Netlist
Decomposition
SI Logic
SynthesisPetrify Petrify
DesiJ
Punf & Mpsat
R
Configuration of the Decomposition
■ Decomposition strategy (basic, lazyBack, tree etc.)
■ Specification of the output partition
■ Insertion of internal communication signals to enable SI logic synthesis
■ Deletion of redundant places
□ simple versions (loop-only, duplicate …)
□ shortcut places
□ implicit places (with unfoldings)
Work Group – Basics of Systems Engineering
11
Secondary Functions
■ Functions for STG manipulation
□ deletion of redundant places
□ contraction of dummy transitions
□ creation of particular benchmark STGs (e.g. SeqParTree)
■ STG conversion to a postscript document (requires graphviz package and a working postscript installation to display the result)
■ Reachability graph generation (simple version)
■ Verification of the decomposition implementation (test for STG-bisimulation)
Work Group – Basics of Systems Engineering
12
User Interface
■ Primary UI: Command Line Interface
□ most powerful UI (all functions and options are accessible)
□ easy accessible by other tools (see later)
■ Secondary UI: a rudimentary GUI
□ for research purposes
□ works in an old DesiJ version only
Work Group – Basics of Systems Engineering
13
Installation requirements
■ DesiJ comes as a Jar-Archive (JRE 1.6 or higher is required)
■ Third party tools are required
□ For synthesis: Petrify, Punf, Mpsat
□ For visualization: Graphviz, Ghostview
■ Full functionality is only provided for Linux so far
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Work Group – Basics of Systems Engineering
15
Outline
■ Motivation
□ Decomposition-based SI Logic Synthesis
□ Idea of Decomposition
■ DesiJ
□ Functionality
□ User Interface
□ Installation requirements
■ Live Demo
■ Integration into the Balsa Design Flow
SeqParTree-3
Work Group – Basics of Systems Engineering
16
Outline
■ Motivation
□ Decomposition-based SI Logic Synthesis
□ Idea of Decomposition
■ DesiJ
□ Functionality
□ User Interface
□ Installation requirements
■ Live Demo
■ Integration into the Balsa Design Flow
Control Circuit
Cluster 1
Decomposition-Based Logic Synthesis
Balsa Specification
Balsa Compiler(balsa-c)
Handshake Circuit
Data Path HCs
STG composer
STG 1 STG n
Decomposer(improved DesiJ)
Decomposer(improved DesiJ)
C-STG 1.1 C-STG 1.i C-STG n.1 C-STG n.j
PetrifyPunf &Mpsat
PetrifyPunf &Mpsat
SI Circuit SI Circuit SI Circuit SI Circuit
Merging Agent
Technolgy-Mapper(balsa-netlist)
Verilog Netlist
ControlHC
ControlHC
STG Extractor
HC-STG
STG composer
STG Extractor
HC-STG
Control HC Mixed HC Data HC
Clustering Agent
Cluster n
ControlHC
Data PathExtractor
MixedHC
Verilognetlist
Failure
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already available
partially available
not available (have to be developed)
Proposed CAD Framework for
Decomposition-based HDL Synthesis
of Asynchronous Circuits
Cluster-STG 1 Cluster-STG n
More Information
■ Website (with download version): http://www.informatik.uni-augsburg.de/en/chairs/swt/ti/research/tools/desij/
■ Mark Schaefer. DesiJ - a tool for STG decomposition. Technical Report 2007-11, Institute of Computer Science, University of Augsburg, 2007, (available at http://www.informatik.uni-augsburg.de/en/chairs/swt/ti/research/tr/2007_desij/)
■ Mark Schaefer, Dominic Wist and Ralf Wollowski. DesiJ – Enabling Decomposition-Based Synthesis of Complex Asynchronous Controllers. To appear in the Proceedings of ACSD’09.
■ DesiJ help: via the command line call desij --help
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