Design of large area, pixelated ASICs for picosecond...

Design of large area, pixelated ASICs for picosecond timing

applications

E. Charbon EPFL

edoardo.charbon@epfl.ch

Outline

•  Why large area TOA ASICs? •  TDC Basics & Architectures •  Case Studies •  ASIC vs. FPGA •  3D Integration •  Quantum computing •  Conclusions

Why large area TOA ASICs?

Large Area TOA Applications

•  Optical rangefinder on-pixel (3D camera) •  Fluorescence lifetime imaging microscopy (FLIM) •  Fluorescence Correlation Spectroscopy (FCS) •  Detection of a scintillation shower upon gamma

photon detection in PET •  High energy physics (HEP)

•  Extremely harsh conditions –  Large ionizing doses, Gamma –  Protons, Neutrons

•  Very demanding specs –  TOA resolutions in ns to ps –  Ranges of µs to ms

•  Very low dead times –  Events spaced ns –  Gevents/s

•  Large number of points-of-measurement –  Thousands to million points –  Large surfaces

Example (Courtesy: Artur Apresyan)

Another Example

•  In time-of-flight PET one needs –  A large number of point-of-measurement –  A high timing resolution

•  Synchronization is extremely important to enable coincidence computation and rejection of singles

TDC Basics

TDC Objective

But, in most cases:

Time scale

TDC Symbol

Basic Definitions •  Bin size or LSB – τ (sec)

–  Minimum distance between time events that can be resolved •  Accuracy & precision (sec)

–  Time-invariant offset –  Time-varying drift

•  Range (sec) –  Maximum time difference that can be measured

•  Conversion rate (MS/sec) •  Latency (sec) •  Non-linearities

–  Differential non-linearity (DNL) –  Integral non-linearity (INL)

Input Non-Idealities

•  Signals are non-Dirac –  Non-zero rise time –  Non-zero width

•  START-STOP sequence is not regular •  Signals have jitter in

–  Time –  Amplitude

•  Temperature •  Supply variations

TDC Non-Idealities

Time difference between START and STOPO

ital c

Ideal response

Actual response

8DNLi = LSB

ti - LSB

INLi = ∑ DNLji

Digital code [LSB]

(a) (b)

Standard deviation, FWHM => single-shot precision

Ideally only one digital code

DNL, INL

•  Integral non-ideality (INL) is the integral of DNL •  Depending upon definition, starts and ends at 0

How to Measure: Density Test

•  Poisson distributed uniform START generator •  Measure statistics of TDC measurements per bin •  Normalize to average counts, differences are DNL

points

counts

avg. counts

Single-Shot Accuracy (SSA)

•  Repeat measurement of single time-of-arrival and construct histogram

•  Derive statistics by Gaussian fitting and calculation of FWHM or σ or 3σ.

TOA centroid

Optical Tests

•  Density test: free running SPAD •  Single-shot experiment:

–  Histogram Δti, i=[1…N] (time-correlated single-photon counting – TCSPC)

GAPD or SPAD

DATA START

Figures of Merit

•  Power, LSB, DNL/INL, SSA, area •  Temperature stability •  Cross-talk

65 90 130 180 350Tech. (nm)

[18]Conventional TDC array

[2][5]

[16][17][9]

[7][6]

Architectures

The Simplest: A Counter

•  Resolution: τ = 1/fclock

•  Conversion rate = 1/latencySTART STOP

CLOCK DATA

DATA VALID BUSY IDLE 20

Counter – Register

•  Advantage: fast counter can be shared among many HIT lines

•  Fast registers easier to build RESET

DATA REGISTER

COUNTER

Delay Chain

•  Non-Inverting Gates

Register

START(Φ0)

DATA VALID BUSY IDLE

1 1 1 1 1 0 0 0

Delay Chain

•  Resolution: τ = delay element •  Conversion rate = 1/latency •  Latency = N×τ•  Need a thermometer decoder: Nèlog2(N) •  Issues: metastability, bubbles

1 1 1 0 1 0 0 0

Phase Interpolator

•  Non-inverting gates

Register

CLOCK(Φ0)

DATA VALID BUSY IDLE

1 1 1 1 1 0 0 0

Phase Interpolator

•  Resolution: τ = delay element •  Conversion rate = 1/latency •  Latency = N×τ•  Need a thermometer decoder: Nèlog2(N) •  Issues: metastability, no bubbles

Vernier Lines

•  Resolution: τ = τslow - τfast •  Conversion rate = 1/latency •  Latency = N×τslow

•  Need a thermometer decoder: Nèlog2(N) •  Issues: metastability, matching

D D D D D D D D

τslow

τfast

Pulse Shrinking

•  Resolution: τ = τrise - τfall •  Conversion rate = 1/latency •  Latency = N×τslow

•  Need a thermometer decoder: Nèlog2(N) •  Issues: matching

START N 1 STOP

START STOP

Asymmetric rise, fall time

Ring Oscillators

•  Resolution: τ = delay element •  Conversion rate = 1/latency •  Latency = N×τ•  Need a thermometer decoder: Nèlog2(N) •  Issues: metastability, matching, asymmetric load

COUNTER To extend range

N 1 STOP

START STOP R/O signal

Uncertainty region

Actual Implementation

•  Fully differential •  Partial propagation readout

–  lower oscillation frequency or higher resolution –  Rise times and fall times doubles resolution

•  Invariant load to improve linearity

Mandai and C

harbon, ES

Delay Element Implementation

•  Uniform rise/fall time •  Bias control used for feedback •  Positive feedback for speed VDD

In+ In-

Out+ Out-

Asymmetric Rise/Fall Time

•  E.g. inverter starved cell •  Rise time =VDD� Cload/I

•  Fall time: inverter delay

In Out

Semi-Digital TDCs

•  Determine time difference based on propagation through an RC line

RC delay chain

t1 t2 t3 t4

Time Difference Amplifier (TDA)

•  Time differences are multiplied as in successive approximation ADCs

•  Issues: gain stability, jitter

Mandai and Charbon , ESSCIRC11

TDA Base Cell

Bias Circuit

TDA Base Cell

Bias Circuit Fast Behavior

TDA Base Cell

Bias Circuit Fast Behavior Slow Behavior

TDA in a TDC

Upper bitTDC

Upper bitADC

DACLower bit

VoltageamplifierVin

DelayLower bit

Time Differenceamplifier

Tstart

Two-stage ADC

Two-stage TDC

Vin-LSB < V < Vin

Amplified time

residue

Amplified voltageresidue

Tdiff-LSB < T < Tdiff

(Tdiff=Tstart-Tstop)

TDA in a TDC

Upper bitTDC

Upper bitADC

DACLower bit

VoltageamplifierVin

DelayLower bit

Time Differenceamplifier

Tstart

Two-stage ADC

Two-stage TDC

Vin-LSB < V < Vin

Amplified time

residue

Amplified voltageresidue

Tdiff-LSB < T < Tdiff

(Tdiff=Tstart-Tstop)

Other Composite TDCs

•  Counter + Phase Interpolator + Vernier Niclass et al., JSSC08

•  Ring Oscillators + Counters Veerappan et al., ISSCC11

•  Ring Oscillators + TDA Mandai and Charbon , ESSCIRC11

… and many more

Stabilization Techniques

•  Process, Voltage supply, Temperature (PVT) variations eliminated using a delay locked-loop (DLL) in clock phase generation

Register HIT1

Register HIT2

CP LF PFD

PVT Stabilization in Phase Interpolators

•  DLL running in parallel as a replica of delay chain •  Distribute bias to all delay chains

CP LF PFD

START1

START2

REPLICA DELAY CHAIN

Nested Stabilization Loops Clock

Resolution: T2 – T1 = Δ

Metastability in Ring Oscillators

CLK_B CLK_B En_b

Metastability of Latch

Case 1: Monolithic Fully Parallel TDC

An Array of 20,480 TDCs

•  Massive array of pixels comprising –  single-photon avalanche diode (SPAD) –  TDC (ring oscillator type) –  Memory

•  Readout –  Frame rate: 1us –  Fully digital

TDC Implementation

Single-gate delay means less power, faster transitions

Analog techniques allow greater architecture flexibility

C. Veerappan, J. Richardson, R. Walker, D.-U. Li, M. W. Fishburn, Y. Maruyama, D. Stoppa, F. Borghetti, M. Gersbach, R.K. Henderson, E. Charbon, ISSCC2011 46

The MEGAFRAME Pixel

The MEGAFRAME Chip •  Format: 160x128 pixels •  Timing resolution: 55ps •  Impulse resp. fun.: 140ps •  DCR (median): 50Hz •  R/O speed: 250kfps •  Size: 11.0 x 12.3 mm2

TDC Ring oscillator (3 bits) + counter (7 bits) = 10 bits 48

The Megaframe-128 Chip

C. Veerappan, J. Richardson, R. Walker, D.-U. Li, M. W. Fishburn, Y. Maruyama, D. Stoppa, F. Borghetti, M. Gersbach, R.K. Henderson, E. Charbon, ISSCC2011

12.3mm

Imager Block Diagram

Pixel Architecture

Photon Counting

Photon Time-of-Arrival

TDC Characterization

55ps resolution, 55ns range

INL DNL

System-level Timing Blue laser Red laser

INL Uniformity

% Resolution Variation

Optical Burst Detection

IR Drop in MEGAFRAME

•  If a large number of TDCs are operating at once, then IR drop occurs

•  As a result the LSB of TDCs changes in space

Pitfalls of MEGAFRAME

•  LSB changes as a function of position of the pixel •  There is a dependency to brightness that will change

the current absorbed •  If a VCO is disrupted, the disruption will propagate

through the array in unpredictable ways

You Can Compensate, but…

e.g. A replica of the pixel VCO can be placed in a PLL but mismatch will dominate the error

Case 2: Column-Parallel TDC

Column-parallel TDC Idea

S. Mandai and E. Charbon, IEEE Nuc. Sci Symp. (NSS) 2012 62

Column-parallel TDC Idea

•  A single VCO distributing the oscillation to all TDCs in a line

•  Pros –  Picosecond skew among TDCs –  No LSB variability –  Good PVT control

•  Cons –  Power & buffers create skews

Column-parallel TDC Solutions

192 TDCs

16x26 SPAD

Mandai, C

harbon, IEE

uc. Sci. S

ymp. (N

) 2012

atto, Mandai, C

harbon, IEE

C 2015

Digitally controlled charge pump

9 x 18 MD-SiPM array

432 TDC array

signal processing

7.6 mm

4.654 mm

192 Column-parallel TDC

mask and energy registers

Pixel with 2-bit counter

Pixel with 1.5-bit counter

4 x 4 SiPMs26 x 16pixels

4.22 mm

44%(D4)

47%(D5)

47%(D6)

51%(D7)

50%(D12)

53%(D13)

54%(D14)

57%(D15)

41%(D9)

39%(D8)

43%(D0)

41%(D1)

46%(D2)

50%(D3)

53%(D10)

56%(D11)

16x26 SPAD

atto, Mandai, C

harbon, IEE

C 2015

Column-parallel TDC Solutions

192 TDCs

16x26 SPAD

Mandai, C

harbon, IEE

uc. Sci. S

ymp. (N

) 2012

Digitally controlled charge pump

9 x 18 MD-SiPM array

432 TDC array

signal processing

7.6 mm

4.654 mm

Pixel with 1.5-bit counter

4 x 4 SiPMs26 x 16pixels

4.22 mm

44%(D4)

47%(D5)

47%(D6)

51%(D7)

50%(D12)

53%(D13)

54%(D14)

57%(D15)

41%(D9)

39%(D8)

43%(D0)

41%(D1)

46%(D2)

50%(D3)

53%(D10)

56%(D11)

16x26 SPAD

SiPMs: The position of the photon detection is lost!

Column-parallel TDC Uniformity

192 TDC array

20 40 80 100 120TDC address

60 140 160 1800

150TDC address

100 400200 300150 250 350

ital c

1st group 2nd group 3rd group

432 TDC array

START0

Band gap

voltage referece

Bias voltage

START1

START2

START143

TDC0TDC1

TDC143

TDC431

TDC144

TDC287

TDC288

Phase repeater

START144

START287

START288

START431

τ+Δτ

φ3 V+

LSB16 phases

φ2 φ3

phase detector

VCO phases

Δτ = LSB

12b CNT

TDCDUM

Bias voltage

STARTDUM

Reftdc

16 + 16 = 32 phases

phase detector

Digital circuit

7.2 mm0.4 mm(c)

(a) (b)

0 200Digital code

400 1000

600 800

0 200Digital code

400 1000

600 800

(a) (b)

0 200Digital code

400 1000

600 800

0 200Digital code

400 1000

600 800

Column-parallel TDC with Memory Features of ‘Piccolo’:

–  32x32 pixels •  FF: 28% •  Pitch: 28µm •  PDP: 50% (max); 11% (800nm) •  DCR: 60cps/pixel

–  128 TDCs •  LSB: 49ps •  Range: 400ns •  Output: 5.12 Gbps (244 Mphotons/s) •  DNL/INL: +/- 0.15 LSB •  SPTR: better than 90ps (SPAD dom.)

S. Lindner et al., IIS

W 2017

ASIC vs. FPGA

FPGA vs. discrete ASIC

•  An application-specific integrated circuit (ASIC) is a chip with static circuitry optimized for one task

•  A field-programmable gate array (FPGA) is a

chip whose configuration, specified by a hardware description language, can be changed many times

General Comparison

FPGA •  Fast Development

Time •  Reconfigurable

–  Lower fault risk –  Iterate design

•  Low non-recurring costs –  Development –  Testing

ASIC •  Lower power •  Faster operation •  Smaller footprint •  Better integration •  More flexibility •  Low unit costs

–  High-volume applications

How to Build a Delay Chain From multiple adder’s carry units

FPGA Caveats: Clock Regions

Bad location for a TDC

Example FPGA Architecture Only digital techniques available with existing cells

Virtex-6 FPGA TDC

Temperature Dependence

Location, Location, Location

Chip-to-chip Variation

TDC Comparison

FPGA •  Best time

uncertainty: 20ps •  Usage examples

–  High-energy physics –  OpenPET

ASIC •  Best time

uncertainty: <1ps •  Examples

–  Time-correlated imaging

–  Frequency synthesizers for RF

FPGA- or ASIC-based TDC?

•  Consider an FPGA-based TDC if your application: –  Is low-volume –  Doesn’t require <20ps time uncertainty –  Is sensitive to development time, or is being created in

iterations –  Is open source (FPGA-based TDCs are code-based)

3D Integration

3D ICs – Hybrid Bonding

J. Mata Pavia, M. Wolf, E. Charbon, JSSC 2015

3D ICs – Hybrid Bonding

•  Sony Corp. (?/?) •  STMicroelectronics (65/45nm) •  TSMC (45/65nm) •  Tezzaron (anything/anything)

TSMC BSI + 3D-Stacking

•  Tier 1: SPADs + microlenses •  Tier 2: quenching, recharge, TDCs, multi-core,

memories, communication unit, I/O A7A1 A2 A3 A4 A5 A6 A8

ADDR_WRITE

MEM_WRITE

DATA_WRITEMEM_READ

Σ16 10b

8 10bDEC

SHAREDTDC

DIGITALPROCESSING

DATA_ROUT

DATA_NEW

ADDR_ROUT

MeM64x21b

31.3%FF

EN_READ

DTOFSAFF* DFF**

masking

100n/390n 60n/390n

60n/520nPassivequenching

1.2VTier2Tier1

RST:GlobalResetMODE:Pulse/State

‘1’

SYMMETRICOR

ADDRESSSR-LATCH

PhotonsMultiple3Dconnections

perSPAD

DTOF6b ADDR_READ01

DECISIONMAKER

ADDR_READ[0] ADDR_READ[1] ADDR_READ[2]

MEM_READ[0] MEM_READ[1] MEM_READ[2]

ADDR_WRITE[0] ADDR_WRITE[1]

DATA_WRITE[0] DATA_WRITE[1]

X MEM_WRITE[0] MEM_WRITE[1]

Combinedevents(8x8pixels) Ignoredevent Ignoredevent

in1 in2A

QUENCHING

READOUT

ACCESS&CONTROL

SERIALIZER

DECISIONTREE6levelsofDECISIONMAKERS6levelsofMUXforADDRESS

QUENCHINGARRAYPassivequenchingMasking&multi-modeoutput

QUENCHING ARRAY (8 x 8)

*SAFF(Sense-AmplifierFlip-Flop)usedforROphasesampling**DFF(Standard-cellD-typeFlip-Flop)usedforcountersampling

M.J. Lee, A.R. Ximenes, P. Padmanabhan, Y. Yamashita, D.N. Yaung, E. Charbon, IEDM 2017

TDC Sharing

•  Virtually zero skew •  Preservation of origin of pulse

A7A1 A2 A3 A4 A5 A6 A8

ADDR_WRITE

MEM_WRITE

DATA_WRITEMEM_READ

Σ16 10b

8 10bDEC

SHAREDTDC

DIGITALPROCESSING

DATA_ROUT

DATA_NEW

ADDR_ROUT

MeM64x21b

31.3%FF

EN_READ

DTOFSAFF* DFF**

masking

100n/390n 60n/390n

1.2VTier2Tier1

‘1’

SYMMETRICOR

ADDRESSSR-LATCH

perSPAD

DTOF6b ADDR_READ01

DECISIONMAKER

in1 in2A

QUENCHING

READOUT

ACCESS&CONTROL

SERIALIZER

TDC Layer

A7A1 A2 A3 A4 A5 A6 A8

ADDR_WRITE

MEM_WRITE

DATA_WRITEMEM_READ

Σ16 10b

8 10bDEC

SHAREDTDC

DIGITALPROCESSING

DATA_ROUT

DATA_NEW

ADDR_ROUT

MeM64x21b

31.3%FF

EN_READ

DTOFSAFF* DFF**

masking

100n/390n 60n/390n

1.2VTier2Tier1

‘1’

SYMMETRICOR

ADDRESSSR-LATCH

perSPAD

DTOF6b ADDR_READ01

DECISIONMAKER

in1 in2A

QUENCHING

READOUT

ACCESS&CONTROL

SERIALIZER

A.R. Ximenes, P. Padmanabhan, M.J. Lee, Y. Yamashita, D.N. Yaung, E. Charbon, ISSCC 2018

3D-Stacked Chip Micrograph

LiDAR Demonstrator

Interference

ModulatedLaser

HistTransmitted

- Chip+FPGA

INTERFERENCE

Interferencew/omodulation

Recoveredsignal

Received

LaserSignature

X-control

Y-control

Dual-axisscanner

Waveformgenerator

Beamsplitter

TDCcode

Horizontalresolution

Verticalresolution

Distance Measurements

Backgroundlight+DCR

UnmodulatedInterference

Target

-12.6dB

-15.6dB

-18.6dB

Interference Suppression

Backgroundlight+DCR

UnmodulatedInterference

Target

-12.6dB

-15.6dB

-18.6dB

256x256 3D Image Reconstruction

Large TDC Arrays

Instead of a large VCO distributing the sync to a large array of TDCs… build a large array of continuously running VCOs Pros

–  Individual FOM improved by 10 log (M) –  Synchronization is ~1ps –  PVT robust –  Robust to local disruptions

Individual FOM improved by 10·log10 (M)

Overall constant FOM

Mutual Coupling

•  Use injection locking for coupling VCOs •  The PLL only forces the desired frequency on the VCOs

10k 100k 1M 10M 100M-160

Freq [Hz]

1 x 1 2 x 2 4 x 4 8 x 8 16 x 16

10·log10 (M)

Individual FOM improved by 10·log10 (M)

Overall constant FOM

Mutual Coupling

en enTo Left RO

To Right RO

To Bottom RO

To Top RO

Coupling Element

3D stacked technology• Only SPADs on top tier• Only processing bottom tier

IMAGERModularFlexible

enes, P. Padm

anabhan, E. C

harbon, IISW

Mutual Coupling Measurements

coupled

uncoupled

Offset Frequency (Hz)

Center Frequency = 500 MHz

uncoupled

coupled

-1401M 10M 100M

Mutual Coupling Measurements

uncoupledcoupled

uncoupled: 22 ~ 26%coupled: <0.11%

coupled

uncoupled

coupled

uncoupled

~14dBFreq

Control Voltage (V)0.65 0.6 0.55 0.5 0.45

# Oscillator0 10 20 30 40 50 60

0 10 20 30 40 50 60

Frequency variationPhase noise (3 MHz) and

integrated jitter @ 500MHz

Perspectives for 2020

•  Sub-65nm CMOS •  Large, scalable designs (Lego™ approach) •  Backside illumination (BSI) 3D IC •  Hybrid approaches (InP, GaAs, Ge, polymers) •  Cryogenic operation

Moore’s Law Will Help

1 kpixel

32 pixel

10 kpixel

100 kpixel

1 Mpixel 0.8 CMOS 0.35 CMOS

65nm CMOS

2012 2020 2015

130nm CMOS

512x256

128x128 160x128

Quantum Computing

The2012NobelPrize

Frombitstoqubits•  AquantumbitorqubitisaquantumsysteminwhichtheBooleanstates0and1arerepresentedbyapairofmutuallyorthogonalquantumstateslabeledas

•  QuantumproperAes:superposi7onandentanglement

Semiconductor quantum dots

Superconducting circuits Impurities in diamond or silicon

Semiconductor-superconductor hybrids

Source:L.Vandersypen,2017

Qbits on a Chip

QuantumComputerArchitecture

•  Carrierfrequency:100MHz–15GHz,70GHz•  Pulses:10–100ns

[DiCarlo]

[L.Vandersypen]

Control

Read-out

Quantumbits(qubits)

Quantumprocessor(≪1K)

Classicalcontroller

QuantumComputerArchitecture

•  Carrierfrequency:100MHz–15GHz,70GHz•  Pulses:10–100ns

[DiCarlo]

[L.Vandersypen]

Control

Read-out

Quantumbits(qubits)

AReal-lifeQuantumComputer

x8qubitsx8qubits

PossibleSolu7ons

•  Proposedsolu7on–  Electronicsat4K–  OnlyconnecAonsto4Kto20mKareneeded

T=20mK T=4K T=300K

ElectronicReadout&control

T=20mK T=4K

ElectronicRead-out&control

T=300K

[Ristèetal.2014-15]

5-qubitcomputer

PossibleSolu7ons

•  Proposedsolu7on–  Electronicsat4K–  OnlyconnecAonsto4Kto20mKareneeded

•  Ul7matesolu7on

–  Qubitsat4K– MonolithicintegraAon

T=20mK T=4K T=300K

ElectronicReadout&control

T=20mK T=4K

ElectronicRead-out&control

T=300K

[Ristèetal.2014-15]

5-qubitcomputer

ElectronicReadout&Control

20-100mK

1-4K 300K

QuantumProcessor

TSensorsBias/References

Digitalcontrol(ASIC/FPGA)

OPTICAL GUIDE APD

E.Charbonetal.,IEDM2016

CoolingPowerIssue

Courtesy:Oxfordinstruments

Dilu7onrefrigerator

ScalabilityIssue

•  Noisebudget…...........................................<0.1nV/√Hz•  Powerbudget(forscalability)….................<<2mW/qubit•  Physicaldimensions(forscalability)….......30nm•  Bandwidth(formulAplexing)…..................1-12GHz•  Kick-backavoidance

CryogenicElectronics

Cryo-CMOSTechnologies

Thinoxide Thickoxide

DeviceModeling(160nm)

R.M.Incandelaetal.,ESSDERC2017

Thickoxide

Thinoxide Thickoxide

Thinoxide

DeviceModeling(40nm)

R.M.Incandelaetal.,ESSDERC2017

BJTsandDTMOSinmKdomain

4K* 1K 40mK

•  BJTscanworkasbandgapreferenceatT>77K•  DTMOScanbeusedasbandgapreferenceatcryotemperatures

To be published

H. Homulle, E. Charbon, F. Sebastiano, JEDS 2018

SubstrateResis7vity

SPICEModels,Farms

•  Wecreatedmodelsfor4KcomponentsinVerilog-AMS,BSIM6,PSP

•  Wearebuildingacompletemodeltoolkitfor40nmand160nmCMOStechnologies

•  Modelsaretestedusingcryogeniccomponentfarms

CryogenicCircuits&Systems

Cryo-FPGAs

HaraldHomulle

•  Artix-7 full operation down to 4K •  Other FPGAs only limited to 30K

•  All FPGA components are working in the cryogenic environment down to 4K

•  No modifications required

FPGAfunc7onality

Component Functional Behavior IOs ✓ LVDS ✓ LUTs ✓ Delay change < 5% CARRY4 ✓ Delay change < 2% BRAM ✓ No corruption (800 kB) MMCM ✓ Jitter reduction of roughly 20% PLL ✓ Jitter reduction of roughly 20% IDELAYE2 ✓ Delay change of up to 30% DSP48E1 ✓ No corruption over 400 operations

A/DconversiononFPGA•  Principle

–  Timestampthecross-overofinputwithreferenceramp–  UseTDCforAmestamping

•  Booleneck:weareboundtotheCMOStechnologyoftheFPGAC LK /

S TART

2 .5 nsC LK /S TOP

S TART

2 .5 nsC LK /S TOP

S TART

2 .5 ns

ADConFPGA(1.2GSa/s)

Signalbandwidth:2MHz Signalbandwidth:40MHz

H.Homulleetal.,TCASI,63(11),1854-1865,2016

ADConFPGA

Signalbandwidth:2MHz Signalbandwidth:40MHz

H.Homulleetal.,TCASI,63(11),1854-1865,2016

1 2 3 4 5 610-2

Excess Bias (V)

77K120K

300K250K

200K160K

SPAD GreenSPAD Red

50 100 150 200 250 300 350

SPAD Green, Φ=12µm

SPAD Red, Φ=12µm

Temperature (K)

- depletion region

Reverse bias

VOP’

OperaAoninproporAonalandGeigermode(SPAD)

Cryo-SPADs

E.Charbonetal.,ISSCC2017

Cryo-SPADs

1 2 3 4 5 610-2

Excess Bias (V)

77K120K

300K250K

200K160K

SPAD GreenSPAD Red

50 100 150 200 250 300 350

SPAD Green, Φ=12µm

SPAD Red, Φ=12µm

Temperature (K)

180nmCMOSbulkB.Patraetal.,JSSC2018

Cryo-LNA

•  Standard160nmCMOS•  500MHzBandwidth•  0.1dBNoisefigure•  7Knoise-equivalenttemperature

E.Charbonetal.,ISSCC2017

Cryo-LNA

B.Patraetal.,JSSC2017

Buildingup

IEEESensors2016

20-100mK

1-4K 300K

QuantumProcessor

TSensorsBias/References

Digitalcontrol(ASIC/FPGA)

OPTICAL GUIDE APD

IEEEISSCC2017IEEEISSCC2017/JSSC2018

Tobepublished2018

IEEEIEDM2016

IEEEISSCC2017

2DReadoutandControl

•  UseimagingsensorreadoutasinspiraAon

•  Reducenumberoftransistors(ideallytozero)

•  Usetunnelingbarriersasselectors

•  (limited)useof3Dstacking ∂∂∂

∂20mK

PuZngThingsinContext

©H.Homulle2016

Conclusions

Take-homeMessages•  LargearraysofTDCsforTOAarenecessarytoanumberofemergingfields

•  ModularityisanimportantingredienttolargeTDCarraysbutoneneedstobeawareofsynchronizaAon,reliability,anduniformityissues

•  3D-stacking/3DintegraAonisbecomingawayoflife!

•  QuantumCompuAngwillneedthesecircuitsbutwillrequirecryogenicoperaAon

Acknowledgements

SwissNaAonalScienceFoundaAonEuropeanSpaceAgencyFP6andFP7NCCR-MICSNOW-STWNIH

h]p://aqua.epfl.ch

Design of large area, pixelated ASICs for picosecond...

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