Post on 04-Feb-2018
HOMEWORK V
CS2204 DIGITAL LOGIC & STATE MACHINE DESIGN SPRING 2014
NYU School of Engineering Page 1 of 28 Handout No : 15 April 3, 2014
DUE : April 17, 2014
READ : Related portions of Chapters III, IV, VI, VII and VIII
ASSIGNMENT : There are seven questions.
Solve all homework and exam problems as shown in class and past exam solutions.
1) Consider the vending machine controller digital system designed in class and also worked onin Homework 4. Remember that it is modified so that it accepts quarters :
Start with the feedback you received in Homework 4 about the operation diagram and the high-level state diagram. Then :
Modify the datapath.
2) Solve Problem 4.6 (b).
You will obtain the minimal SOP expression. Draw the minimal circuit, assuming that double-rail inputs are available. Remember to write down the postulate or theorem used for the expres-sion simplification, not the number of the postulate or theorem.
3) Solve Problem 4.7 (h).
Q
DG
clock
DC
RetDime
D
N
G
14 Amount Inputs
Q : Quarter is inputD : Dime is inputN : Nickel is inputG : Gum is selectedC : Chips is selected
Outputs
Amount : Value of gum and chips (35 cents) or thecoin input so far shown on two 7-segment displaysDG : Deliver GumDC : Deliver chipsRetDime : Return 10 centsRetNickel : Return 5 cents
Textual Input/Output Relationship
After receiving the necessary amount (35 cents to 50 cents) and the selection ismade deliver a gum or chips and return 5 or 10 cents if necessary
C RetNickel
NYU School of Engineering Page 2 of 28 CS2204 Handout No : 15 April 3, 2014
The order of the inputs on the truth table is important. The order is (A, B, C, D). You will showan output column for each operator (AND, OR, NOT). Note that you will assume there is noNOR gate in the circuit and will not simplify the expression in this question.
Draw the circuit of the original expression given in the textbook : (((A + B’)’ + C)’ + D)’, assum-ing that single-rail inputs are available and with AND, OR, NOT gates. How many gate levelsdoes the original expression have ? Then convert the original circuit (with AND, OR, NOT) to aminimal circuit with only NAND gates, as done in class.
4) Solve Problem 4.9 (d).
The question is asking you to obtain canonical SOP and POS expressions. Show also the missingminterm list. The order of inputs is (W, X, Y).
5) Solve Problem 4.10 (e).
Solve it for only the canonical SOP expression. Do not obtain the canonical POS expression.Show the minterm list.
The order of the inputs is (X, Y, Z). The expression in the problem has three terms, the last two ofwhich are identical. Use relevant postulates and theorems to handle that. Each term in theexpression is not canonical. Thus, they have to be expanded to include all the inputs of the func-tion as done in class.
6) Develop a non-priority 10-to-4 encoder shown below. “Non-priority” means that it is guaran-teed that at any time either all inputs are 0 or only one input is 1. Provide an output named “valid”which is 1, when an encoder input is 1. The valid output is 0, when all 10 inputs are 0.
7) Consider the black box view and input/output relationship of a BCD ADDer, a combinationalcircuit, shown below :
10-to-4
Encoder
I0I1I2I3
Y0
I4I5I6I7I8I9
Y1
Y2Y3
valid
msb
First, show the operation table of the encoder, which is a sim-plified truth-table since at any time no more than one input is1. From the operation table, you will derive the minimal equa-tions. Then, draw the corresponding gate networks for thefive outputs. Then, indicate the generic gate usage, i.e. whichgates, how many of each and the total generic gate count.
Students can take a look at the implementation of the 74LS147TTL MSI chip which is a 10-to-4 priority encoder withactive-low inputs, active-low data outputs and no valid output.
NYU School of Engineering Page 3 of 28 CS2204 Handout No : 15 April 3, 2014
Develop the BCD ADDer for a PCB. That is, implement the BCD ADDer that will be eventuallyimplemented with chips on a PCB. Use the following notes as you implement the BCD ADDer :
i) The circuit is a combinational circuit ! The Digital Product Development handout indicates thatfirst the precise input/output relationship must be obtained : the truth table ! This is impracticalfor the BCD ADDer since there are nine inputs ! Therefore, we have to obtain the operationtable. Then, we would proceed with the implementation step below.
ii) According to the Digital Product Development handout, we try to implement the BCD ADDerimmediately. We answer the following questions (from Digital Product Development) :
Í Is it implementable by using 0 or a few gates on one or few SSI chips ? No !Í Is there a single high-density chip, or a few high-density chips that implements the above
black box with the given operation table ? No !Í Any programmable chip or chips ? Yes, but for the sake of this problem, we will say “No,”Í A few SSI chips ? No !Í A custom chip implementation ? We could try it, but for the sake of this problem, we will
say “No” too,Í Since there is no immeditate implementation, we have to partition the BCD ADDer based
on the major operations on the operation table. The BCD ADDer is not very complexwhich ensures that each block is immediately implementable.
Í After the partitioning, for each block, do the following :‚ Get the input/output relationship, an operation table. Then, ask the implementation ques-
tions above. One of them will be “Yes,” so you will not partition anymore.
Again, you have three tasks : (i) you will get the operation table of the above black box, then (ii)determine the major operations and (iii) partition the black box into blocks that are immediatelyimplementable by chips that we have discussed in class ! Draw the blocks by hand and clearlylabel wires. Precisely indicate which input of a block is connected to which output of a block.Do not implement the blocks (do not implement with chips).
When you partition, you will stop, if each block is immediately implementable by the first or thirdquestions above. That is, each block is implementable by using several TTL LS chips and per-haps few SSI chips if necessary.
Hint : Try to make use of your answers to Question 2 and Question 3 in Homewrok II.
4K
SBCDADDer
4
4M
cincout
5 + 7 + 1 = (13)10
S = 3 and cout is 1
K + M + cin
For example :
NYU School of Engineering Page 4 of 28 CS2204 Handout No : 15 April 3, 2014
RELEVANT QUESTIONS AND ANSWERS
Q1) Consider the following digital system whose black-box view, datapath and high-level state diagram are
shown below :
L D
StoreA
Q
8
A
OUT
clock
8M 8
A K ; B M ; C 0
A A - 1
0
1
3
8
Done
8
Over
Done
QC
clock
D
B
StoreB 8
L
OUT
Done = 1
8K
Start
End
Start = 0
Start = 1
C C + B2
A = 0 A = 0
End = 0End = 1
8-bit 2-to-1 MUX
1 0Sel
p
8
M8
K
8-bit 2-to-1 MUX
1 0Sel
q
Q
D
C
StoreC 8
LC
clock
8-bit 2-to-1 MUX
1 0Sel
r
8-bit ADD
8
C
clock
8
To Control Unit
8
DC
ClearC
8
(-1)10
8 From Control Unit
NYU School of Engineering Page 5 of 28 CS2204 Handout No : 15 April 3, 2014
a) Consider the table below that shows the initial values of a number of signals in the datapath with respect to time :
Continue with the table until the control returns to state 0 as shown as the last row on the above table. Assume that“End” is 1 until “Done” is 1. It returns to 0, one clock period after “Done” becomes 1. K and M are 0 until “Start”becomes 1 again.
b) Draw the low-level state diagram of the digital system. Signal Over is a control signal, besides other control sig-
nals. Register A is checked by the Control Unit and so its outputs are status signals.
A1) a) The table is completed as follows :
b) The low-level state diagram of the digital system is below.
Time State Start End K M A B C OUT Done
t0 0 1 0 2 5 ? ? ? 0 0
t1 1 0 1 0 0 2 5 0 0 0
... ... 0 1 0 0 Continue ... ... ... ...
tn 0 1 0 7 4 ... ... ... ... ...
Time State Start End K M A B C OUT Done
t0 0 1 0 2 5 ? ? ? 0 0
t1 1 0 1 0 0 2 5 0 0 0
t2 2 0 1 0 0 1 NS NS 0 0
t3 1 0 1 0 0 NS NS 5 5 0
t4 2 0 1 0 0 0 NS NS 5 0
t5 3 0 1 0 0 NS NS A A 1
t6 0 1 0 7 4 NS NS NS A 0
StoreA = 1 ; StoreB = 1 ; ClearC = 1 ; p = 0
p = 1 ; q = 1 ; r = 1 ; StoreA = 1
0
1
3
Over = 1
Start = 0
Start = 1
q = 0 ; r = 0 ; StoreC = 1
2
A = 0A = 0
End = 0End = 1
NYU School of Engineering Page 6 of 28 CS2204 Handout No : 15 April 3, 2014
Q2) Consider the following digital system whose black-box view, datapath and high-level state diagram are
shown below :
a) Consider the following table that shows the values of a number signals in the datapath.
Time State K A AgtB B OUT Done
t0 0 2A ? ? ? ? ?
t1 1 3F 2A 1 00 00 0
t2 2 C2
t3 3 19
t4 4 57
t5 0 4E
L D
C
StoreA
clockQ
8
K
8-bit
A
OUT
clock
8K 2
A K ; B 00
If K > A then A K & B 01
0
1
2
3
Done = 1
2
Done
8
Over Done
B
A
AgtB
QCclock
D
B
StoreB 2
L
ENCPOS
OUT
If K > A then A K & B 10
If K > A then A K & B 11
4
Binary
Unsigned
Comparator
NYU School of Engineering Page 7 of 28 CS2204 Handout No : 15 April 3, 2014
Continue with the table.
b) Draw the low-level state diagram of the digital system. Signals Over and ENCPOS (Encoded Position) are con-
trol signals, besides other control signals. AgtB is a status signal.
A2) a) The table is completed as follows :
b) The low-level state diagram of the digital system is as follows :
t6 1 6A
t7 2 39
t8 3 1F
t9 4 74
t10 0 F1
t11 1 82
Time State K A KgtA B OUT Done
t0 0 2A ? ? ? ? 0
t1 1 3F 2A 1 00 00 0
t2 2 C2 3F 1 01 01 0
t3 3 19 C2 0 10 10 0
t4 4 57 NS 0 NS 10 1
t5 0 4E NS 0 NS 10 0
t6 1 6A 4E 1 00 00 0
t7 2 39 6A 0 01 01 0
t8 3 1F NS 0 NS 01 0
t9 4 74 NS 1 NS 01 1
t10 0 F1 6A 1 01 01 0
t11 1 82 F1 0 00 00 0
Time State K A AgtB B OUT Done
NYU School of Engineering Page 8 of 28 CS2204 Handout No : 15 April 3, 2014
Q3) Simplify the following expression by using Switching Algebra :
abc + (abc + ac)[b(a + c) + bc + a b c]
A3) = abc + (abc + ac)[ab + bc + bc + a b c] k(m + p) = km + kp
= abc + (abc + ac)[ab + c + a b c] k(m + p) = km + kp & k + k = 1 & k1 = k
= abc + (abc + ac)[ab + c + a b] k + km = k + m
= abc + (abc + ac)[a + c] k(m + p) = km + kp & k + k = 1 & k1 = k
= abc + abc + ac k(m + p) = km + kp & kk = k & k k = 0 & k + 0 = k
= abc + ac k + k = k
Q4) Consider the following switching expression :
Simplify the expression by using Switching Algebra and then draw the corresponding 2-level AND/OR gate network,assuming there are only single-rail inputs.
A4) The solution is below :
1
4Over = 1
StoreA = 1 ; StoreB = 1 ; ENCPOS = 000
ENCPOS = 01 ; If AgtB then ; StoreA = 1 ; StoreB = 1
2ENCPOS = 10 ; If AgtB then ; StoreA = 1 ; StoreB = 1
3ENCPOS = 11 ; If AgtB then ; StoreA = 1 ; StoreB = 1
f(a, b, c, d) = a(bc + bc) + (c + d) + abcd + cd(a + ac)
NYU School of Engineering Page 9 of 28 CS2204 Handout No : 15 April 3, 2014
Q5) Consider the following gate network :
Simplify the gate network to obtain a minimal SOP expression, by using Switching Algebra.
A5) We first write down the expression at the output of each gate to obtain the switching expression :
f(a, b, c, d) = a(bc + bc) + (c + d) + abcd + cd(a + ac)
= a(bc + bc) + (c + d) + abcd + acd k + km = k
= a(b(c + c)) + (c + d) + abcd + acd k(m + p) = km + kp
= ab + (c + d) + abcd + acd k + k = 1 & k1 = k
= ab + cd + abcd + acd (k + m) = k m & k = k
= ab + cd+ acd k + 1 = 1 & k1 = k
= ab + cd(1 + ab) + acd k(m + p) = km + kp
b
f(a, b, c, d) = ab + cd + acd
d
a
a
cd
c
aab
d cd
c acd
The minimal 2-level AND/OR
gate network contains seven gates
A
B
A
B
1
A
BC
f(A, B, C, D)
(logic one)
A
B
A
B
1
A
BC
f(A, B, C, D)
AB
AB
AB + AB (AB + AB) + 1
A B C
[(AB + AB) + 1] +A B C
NYU School of Engineering Page 10 of 28 CS2204 Handout No : 15 April 3, 2014
We then minimize the switching expression :
Q6) Consider the following minimal SOP expression :
i) Draw the corresponding 2-level NAND-NAND gate network, assuming single-rail inputs and as done in class.
ii) Obtain the canonical SOP expression of the function algebraically as done in class.
iii) Obtain the minterm and maxterm lists of the function.
A6) i) We know that an SOP expression is implemented by a 2-level AND-OR gate network. We also know that a2-level AND-OR gate network is immediately implemented by a 2-level NAND-NAND gate network.
ii) f(a, b, c, d) = bcd + ad= bcd(a + a) + ad(b + b)(c + c) k + k = 1 & k1 = k= abcd + abcd + ad(bc + bc + bc + b c) k(m+p) = km + kp
f(A, B, C, D) = [(A B + A B) + 1] + A B C
= [k +1] + A B C k = A B + A B
= k1 + k1 + A B C k + m = k m + km
= k + A B C 1 = 0 & m0 = 0 & m1 = m & m+0 = m
= ((AB) + (AB)) + A B C k = A B + A B
= ((A + B)(A + B)) + A B C (km) = k + m
= ((A + B)(A + B)) + A B C k = k
= A A + AB + A B + B B + A B C k(m + p) = km + kp
= AB + A B + A B C kk = 0 & k + 0 = k
= B(A + AC) + AB k(m + p) = km + kp
= B(A + C) + AB k + km = k + m
= A B + B C + AB k(m + p) = km + kp
= ((AB) (AB)) + A B C (k + m) = k m There is yet anotherminimal expression :(A B + AC + AB),which is impossible tonotice during the sim-plification. The factthat the algebra does notenable us to realizethere are multiple mini-mal expressions, is oneof main drawbacks ofusing Switching Alge-bra for circuit minimi-zation.
f(a, b, c, d) = b c d + a d
cb
ad
d f(a, b, c, d) = b c d + a d
NYU School of Engineering Page 11 of 28 CS2204 Handout No : 15 April 3, 2014
= abcd + abcd + abcd + abcd + abcd + ab cd k(m+p) = km +kp= abcd + abcd + abcd + abcd + ab cd k + k = k
iii)
Q7) Simplify the following switching expression by using Switching Algebra as shown in class :
Then, draw the minimal 2-level AND/OR gate network, assuming that there are double-rail inputs.
A7)
abcd1101
13
abcd0101
5
abcd1111
15
abcd1011
11
ab cd1001
9
f(a,b,c,d) m(5,9,11,13,15)=
f(a,b,c,d) M(0,1,2,3,4,6,7,8,10,12,14)=
f(A, B, C, D) = ((A C D) + (B C)) (A + (B D)) + A B C + (A C + A C) + (A B (C + D))
((A C D) + (B C)) (A + (B D)) + A B C + (A C + A C) + (A B (C + D))
= (A C D) (B C) (A (B D)) + A B C + ((AC) (A C)) + (A B (C D)) (k m) = k + m & (k + m) = k m
= (A C D) (B C) (A (B D)) + A B C + ((AC) (A C)) + (A B (C D)) k = k
= (A C D) (B + C) (A B D) + A B C + (A + C)(A + C) + A B C D (k m) = k + m & (k + m) = k m
= (A C D) (B + C) (A (B D) + A B C + (A + C)(A + C) + A B C D k = k
= (A B C D +A C D)(A B D)+A B C+A A+A C+A C+C C+A B C D k(m + p) = km + kp & kk = k
= (A B C D + A C D)(A B D) + A B C + A C + A C + A B C D k k = 0 & k + 0 =k
= (AABBCDD + A A BCDD) + A B C + A C + A C + A B C D k(m + p) = km + kp
= A B C + A C + A C + A B C D k k = 0 & k+0 = k & k k = k
= A B C + A C + A C k + km = k
= A C + A C k + km = k
=
C
f(A, B, C, D)
A
AC
AC
AC
AC + AC
NYU School of Engineering Page 12 of 28 CS2204 Handout No : 15 April 3, 2014
Q8) Consider the following expression :
(i) Simplify the expression to obtain the minimal SOP expression by using Switching Algebra as shown in class.
(ii) Then, draw the corresponding minimal 2-level NAND-NAND gate network, by assuming single-rail inputs.
A8) i) The simplification to obtain the minimal SOP expression :
ii) We know that an SOP expression is directly implemented by a 2-level AND-OR gate network and a 2-level AND-OR gate network can be immediately converted to a 2-level NAND-NAND gate network :
Q9) Determine if the following two functions, y(a, b, c), z(a, b, c), are equivalent :
f(a, b, c, d) = (a + b) + c(d(a + a) + (bb)) + c(ab + a + b)d
f(a, b, c, d) = (a + b) + c(d(a + a) + (bb)) + c(ab + a + b)d
= (a + b) + c(d 1 + 0) + c(ab + a + b)d k + k = 1 & kk = 0
= (a + b) + cd + c(ab + a + b)d k1 = k & k + 0 = k
= (a + b) + cd + c(b + a + b)d k + km = k + m
= (a + b) + cd + cd k + k = 1 & k1 = k
= (a b) + cd + cd (k + m) = k + m
= ab + cd + cd k = k
bf(a, b, c, d) = ab + cd + cd
a
Single-rail d
c
dc c
dinputs
a
ab
a
b
bc
y(a, b, c) z(a, b, c) = m(0, 1, 2)
NYU School of Engineering Page 13 of 28 CS2204 Handout No : 15 April 3, 2014
A9) We obtain the switching expression for the y(a, b, c) function. In order to do that we first place the term that cor-
responds to the output of each gate and the full expression for function y(a, b, c) :
The minimal SOP expression can now be converted to a canonical SOP expression :
= a b (c + c) + a c (b + b) k + k = 1 & k1 = k = a b c + a b c + a b c + a b c k(m + p) = km + kp = a b c + a b c + a b c k + k = k
The above three canonical product terms correspond to minterms 1, 0 and 2, respectively :
Q10) By using a truth table, show if the following two expressions are equivalent :
f(a, b, c) = (a + ((b+c) a) g(a, b, c) = (a + b + c)
A10)
a
y(a, b, c)
ab + a b + bc
a (ab + a b + bc)a
b
a
b
bc
ab
a b
bc
y(a, b, c) = a (a b + a b + b c)
= a (b (a + a) + b c) k(m + p) = km + kp
= a (b (1) + b c) k + k = 1
= a (b + b c) k1 = k
= a (b + c) k + km = k + m
= a b + a c k(m + p) = km + kp
a b c + a b c + a b c 0 0 1 0 0 0 0 1 0
1 0 2
y(a,b,c) m(0,1,2)=
given that
z(a,b,c) m(0,1,2)= y(a, b, c) = z(a, b, c)
3 4 1 2 5
On the output columns section, there is a columnfor each operation. The order of obtaining the out-put columns is based on the precedence rules and isshown by the numbered arrows.
Function f(a, b, c) is column 4. Function g(a, b, c)is column 5.
Since the f(a, b, c) and g(a, b, c) columnsare notequivalent, the two functions are not equivalent..
a b c (a + ((b + c) a) (a + b + c)0 0 0 1 1 0 0 00 0 1 1 1 1 0 1 0 1 0 1 1 1 0 1 0 1 1 1 1 1 0 11 0 0 0 0 0 0 1 1 0 1 0 1 1 1 1 1 1 0 0 1 1 1 1 1 1 1 0 1 1 1 1
NYU School of Engineering Page 14 of 28 CS2204 Handout No : 15 April 3, 2014
Q11) Consider the following combinational circuit with four inputs and two outputs :
(i) Obtain the truth table of the circuit based on the textual input/output relationship. (ii) Then, obtain the minterm lists of the outputs from the truth table.(iii) Then, obtain the canonical SOP expression of output y(a, b, c, d) as shown in class.
A11) The truth table and the minterm lists :
Q12) The black-box view and purpose of a special purpose comparator circuit are shown below :
i) Obtain the truth table of the function y(a, b, c, d) as done in class.
ab
cd
Ky(a, b, c, d)
y = 1 if K > (3)10
msb
z = 1 if K < (-5)10 z(a, b, c, d)
K is a 4-bit 2’s Complement Binary number
a b c d y z
0 0 0 0 0 0
0 0 0 1 0 0
0 0 1 0 0 0
0 0 1 1 0 0
0 1 0 0 1 0
0 1 0 1 1 0
0 1 1 0 1 0
0 1 1 1 1 0
1 0 0 0 0 1
1 0 0 1 0 1
1 0 1 0 0 1
1 0 1 1 0 0
1 1 0 0 0 0
1 1 0 1 0 0
1 1 1 0 0 0
1 1 1 1 0 0
y(a, b, c, d) m(4, 5, 6, 7)=
The Minterm lists :
0123
4
5
6
789
10
1112
1314
15
K K
0
1
2
3 4
5
6
7 -8
-7
-6
-5 -4
-3
-2
-1
z(a, b, c, d) m(8, 9, 10)=
The canonical SOP expression for y(a, b, c, d) :
4
0 1 0 0
a b c d
6
0 1 1 0
a b c d
5
0 1 0 1
a b c d
7
0 1 1 1
a b c d
y(a, b, c, d) = a b c d + a b c d + a b c d + a b c d
a
bKy = 1 if K is equal to 0 or 4 or 6 or
K is a 4-bit unsigned binary numbermsb
y(a, b, c, d)c
d 10 or 12 or 15
NYU School of Engineering Page 15 of 28 CS2204 Handout No : 15 April 3, 2014
ii) Obtain the minterm list of the function as done in class.
iii) Consider the following minimal SOP expression :
Prove/disprove if function f(a, b, c, d) is equivalent to function y(a, b, c, d) by first obtaining the truth table of f(a, b,c, d) as done in class and then the minterm list of f(a, b, c, d) from its truth table.
A12) Truth tables and minterm lists :
Q13) Consider the combinational circuit with four inputs and four outputs below.
(i) Obtain the truth table of the combinational circuit based on the textual input/output relationship.
In order for G to have four bits so that it has the same bits as Z, assume that G has an invisible fourth (leftmost) bitwhose value is obtained via a sign extension on G. Then perform the necessary operation on G. Name this invisibleleftmost bit as “e” and show it on your truth table.
f(a, b, c, d) = a d + a d
a b c d y(a,b,c,d) a d a d ad a d + ad0 0 0 0 1 1 1 1 0 10 0 0 1 0 1 0 0 0 00 0 1 0 0 1 1 1 0 10 0 1 1 0 1 0 0 0 00 1 0 0 1 1 1 1 0 10 1 0 1 0 1 0 0 0 00 1 1 0 1 1 1 1 0 10 1 1 1 0 1 0 0 0 01 0 0 0 0 0 1 0 0 01 0 0 1 0 0 0 0 1 11 0 1 0 1 0 1 0 0 01 0 1 1 0 0 0 0 1 11 1 0 0 1 0 1 0 0 01 1 0 1 0 0 0 0 1 11 1 1 0 0 0 1 0 0 01 1 1 1 1 0 0 0 1 1
y(a,b,c,d) m(0,4,6,10,12,15)=
The Minterm list :
The minterm list for f(a, b, c, d) :
Since the two functions do NOT
have identical minterm lists, they
are NOT equivalent to each other !
0123456789
101112131415
f(a,b,c,d) m(0,2,4,6,9,11,13,15)=
a
b
c
d
G
z3(a, b, c, d)Z is a 4-bit 2’s Complement Binary number
If a = 0 then Z = G - 1
msb
z0(a, b, c, d)
msb
Z
else Z = G + 1
z2(a, b, c, d)
z1(a, b, c, d)
G is a 3-bit 2’s Complement Binary number
NYU School of Engineering Page 16 of 28 CS2204 Handout No : 15 April 3, 2014
(ii) Then, obtain the minterm lists of the outputs from the truth table.
(iii) Then, obtain the canonical SOP expression of output z3 as shown in class.
A13) The truth table, the minterm lists and the canonical SOP expression :
Q14) Consider the following combinational circuit with four inputs and four outputs :
(i) Obtain the truth table of the circuit based on the operation table. Use sign extensions to obtain 4 bits of R from 2bits of K as done in the homework.(ii) Then, obtain the minterm lists of the outputs from the truth table.
(iii) Then, obtain the canonical SOP expression of output z(a, b, c, d) as shown in class.
a b c d e z3 z2 z1 z0
0 0 0 0 0 1 1 1 1
0 0 0 1 0 0 0 0 0
0 0 1 0 0 0 0 0 1
0 0 1 1 0 0 0 1 0
0 1 0 0 1 1 0 1 1
0 1 0 1 1 1 1 0 0
0 1 1 0 1 1 1 0 1
0 1 1 1 1 1 1 1 0
1 0 0 0 0 0 0 0 1
1 0 0 1 0 0 0 1 0
1 0 1 0 0 0 0 1 1
1 0 1 1 0 0 1 0 0
1 1 0 0 1 1 1 0 1
1 1 0 1 1 1 1 1 0
1 1 1 0 1 1 1 1 1
1 1 1 1 1 0 0 0 0
z3(a,b,c,d) m(0, 4, 5, 6, 7, 12, 13, 14)=
The Minterm lists :
0123
4
5
6
789
10
11
121314
15
G
G Z
0 -1
1 0
2 1
3 2 -4 -5
-3 -4
-2 -3
-1 -2 0 1
1 2
2 3
3 4 -4 -3
-3 -2
-2 -1
-1 0
Z
z0(a,b,c,d) m(0, 2, 4, 6, 8, 10, 12, 14)=
z2(a,b,c,d) m(0, 5, 6, 7, 11, 12, 13, 14)=
z1(a,b,c,d) m(0, 3, 4, 7, 9, 10, 13, 14)=
The canonical SOP expression for z3 :
0
0 0 0 0
a b c d
4
0 1 0 0
a b c d
6
0 1 1 0
a b c d
5
0 1 0 1
a b c d
7
0 1 1 1
a b c d
12
1 1 0 0
a b c d
13
1 0 1 1
a b c d
14
1 1 1 0
a b c d
z3(a, b, c, d) = a b c d + a b c d + a b c d + a b c d + a b c d + a b c d + a b c d + a b c d
a
b
c
d
y(a, b, c, d)
z(a, b, c, d)
K & R are 2’s
Kmsb
w(a, b, c, d)
Complement
numbersBinary R
a b Operation0 0 R = - K (negate K)0 1 R = 2 * K (two times K)1 0 R = 4 * K (four times K)1 1 R = K * K (K times K)
x(a, b, c, d)
msb
NYU School of Engineering Page 17 of 28 CS2204 Handout No : 15 April 3, 2014
A14) The truth table and the minterm lists :
Since input K has two bits and output R has 4 bits, we sign extend input K by two bits. These new leftmost two bitsof K are “e” and “f” and their values are shown on the truth table above.
Q15) Consider the combinational circuit with four inputs and three outputs below :
(i) Obtain the truth table of the circuit based on the operation table.
(ii) Then, obtain the minterm lists of the outputs from the truth table.
(iii) Then, obtain the canonical SOP expression of output z(a, b, c, d) as shown in class.
A15) The truth table and the minterm lists :
a b c d e f w x y z
0 0 0 0 0 0 0 0 0 0
0 0 0 1 0 0 1 1 1 1
0 0 1 0 1 1 0 0 1 0
0 0 1 1 1 1 0 0 0 1
0 1 0 0 0 0 0 0 0 0
0 1 0 1 0 0 0 0 1 0
0 1 1 0 1 1 1 1 0 0
0 1 1 1 1 1 1 1 1 0
1 0 0 0 0 0 0 0 0 0
1 0 0 1 0 0 0 1 0 0
1 0 1 0 1 1 1 0 0 0
1 0 1 1 1 1 1 1 0 0
1 1 0 0 0 0 0 0 0 0
1 1 0 1 0 0 0 0 0 1
1 1 1 0 1 1 0 1 0 0
1 1 1 1 1 1 0 0 0 1
y(a, b, c, d) m(1, 2, 5, 7)=
The Minterm lists :
0123
4
5
6
789
10
1112
1314
15
K
K
0 1
-2
0 1
-2 -1 0
1 -2
-1 0 1 -2
-1
z(a, b, c, d) m(1, 3, 13, 15)=
The canonical SOP expression for z(a, b, c, d) :
13
1 1 0 1
a b c d
z(a, b, c, d) = a b c d + a b c d + a b c d + a b c d
w(a, b, c, d) m(1, 6, 7, 10, 11)=
3
0 0 1 1
a b c d
15
1 1 1 1
a b c d
1
0 0 0 1
a b c d
x(a, b, c, d) m(1, 6, 7, 9, 11, 14)=
-1
a
b
c
d
y(a, b, c, d)
z(a, b, c, d)
K & R are 2’s
Kmsb
valid(a, b, c, d)Complement
numbersBinary
R
a b Operation0 0 R = K + 1 ; valid = 0 if overflow0 1 R = K - 1 ; valid = 0 if overflow1 0 y = d ; z = c ; valid = 11 1 y = d ; z = 0 ; valid = 1
msb
NYU School of Engineering Page 18 of 28 CS2204 Handout No : 15 April 3, 2014
Q16) Consider Block 6, the Machine Play Block, of the term project. Assume that the machine player has the fol-lowing playing strategy :
a) Assume that the code is 58. The table below shows the random digit, position displays before and after themachine player plays, if the machine player is ahead (P2GTP1 = Yes) before the play, whether the random digit isplayed directly or added, the number of adjacencies, the points earned by the machine player and if the machineplayer plays again. Complete the rows of the table. You will circle the position played :
RDDisplays before playPD3 PD2 PD1 PD0
P2GTP1Displays after play
PD3 PD2 PD1 PD0D/A Adjacency
Reward Points(Decimal)
Plays Again ?
5 0 7 0 0 Yes
2 8 C 0 0 No
6 8 E 6 0 No
3 A E 6 3 Yes
7 F E 8 3 No
a b c d valid y z
0 0 0 0 1 0 1
0 0 0 1 0 1 0
0 0 1 0 1 1 1
0 0 1 1 1 0 0
0 1 0 0 1 1 1
0 1 0 1 1 0 0
0 1 1 0 0 0 1
0 1 1 1 1 1 0
1 0 0 0 1 0 0
1 0 0 1 1 1 0
1 0 1 0 1 0 1
1 0 1 1 1 1 1
1 1 0 0 1 0 0
1 1 0 1 1 1 0
1 1 1 0 1 0 0
1 1 1 1 1 1 0
y(a, b, c, d) m(1, 2, 4, 7, 9, 11, 13, 15)=
The Minterm lists :
0123
4
5
6
789
10
1112
1314
15
K
K
0 1
-2
0 1
-2 -1 0
1 -2
-1 0 1 -2
-1
z(a, b, c, d) m(0, 2, 4, 6, 10, 11)=
The canonical SOP expression for z(a, b, c, d) :
40 1 0 0
a b c d
6
0 1 1 0
a b c d
10
1 0 1 0
a b c d
z(a, b, c, d) = a b c d + a b c d + a b c d + a b c d + a b c d + a b c d
valid(a, b, c, d) m(0, 2, 3, 4, 5, 7, 8, 9, 10, 11, 12, 13, 14, 15)=
20 0 1 0
a b c d
11
1 0 1 1
a b c d
00 0 0 0
a b c d
-1
Play on the (rightmost)largest display position with an addition
NYU School of Engineering Page 19 of 28 CS2204 Handout No : 15 April 3, 2014
b) Assume that the above machine player is modified to have a different strategy. The datapath of the circuit thatimplements the modified machine player for the new playing strategy is below :
In the figure, M2 is Macro 2 of Block 6, as designed in the lab. P2GTP1 means P2PT > P1PT. This is the case beforethe play. P2canplay is 1 in the last Player 2 state. RD3 and RD 2 are the leftmost two bits of the random digit.
i) Draw the flowchart of the playing strategy of the modified machine player.
ii) How many clock periods does the machine player take to play ? Explain.
iii) Assume again that the code is 58.
The table below shows the same values as the table above : The random digit, position displays before and after themachine player plays, if the machine player is ahead (P2GTP1 = Yes) before the play, whether the random digit isplayed directly or added, the number of adjacencies, the points earned by the machine player and if the machineplayer plays again.
P2SEL3
P2SEL2
P2SEL1
P2SEL0
Test3
Test2
Test1
Test0
Play
Y1
Y0LRDP1
LRDP0
A1
A0
B1
B0
Sel
2-bi
t 2-t
o-1
MU
X
Rightmost
LRDP1
LRDP0
Largest
Display
Position
Circuit
.
.
.
.
.
(M2)
DISP15
DISP0
RD3
RD2 RDLT4
P2GTP1
Y3
Y2
Y1
Y0
I1
I0 2-to
-4 D
CD
8
P2PT8
P1PT
8-bit
UnsignedBinary
Comparator
P2GTP1
AGtB
B
A P2skip
1 P2add
P2playedPlay
Rightmost
LRRP1
LRRP0
Largest
Regular
Reward
Position
.
.
.
.
.
Circuit
LRRP1
LRRP0
P2canplay
P2canplay
Play
RDLT4
P2GTP1 PlayP2canplay
NYU School of Engineering Page 20 of 28 CS2204 Handout No : 15 April 3, 2014
Complete the rows of the table. You will circle the position played :
A16) a) The table is completed as follows :
b) i)
ii) The machine player takes five clock periodto play. It does only additions, hence it takes four clock periods to col-lect the four regular reward points and then one clock period to play.
RDDisplays before playPD3 PD2 PD1 PD0
P2GTP1Displays after play
PD3 PD2 PD1 PD0D/A Adjacency
Reward Points(Decimal)
Plays Again ?
5 0 7 0 0 Yes
2 8 C 0 0 No
6 8 E 6 0 No
3 A E 6 3 Yes
7 F E 8 3 No
RDDisplays before playPD3 PD2 PD1 PD0
P2GTP1Displays after play
PD3 PD2 PD1 PD0D/A Adjacency
Reward Points(Decimal)
Plays Again ?
5 0 7 0 0 Yes 0 C 0 0 A 0 12 N
2 8 C 0 0 No 8 E 0 0 A 0 14 N
6 8 E 6 0 No 8 4 6 0 A 0 4 N
3 A E 6 3 Yes A 1 6 3 A 0 1 N
7 F E 8 3 No 6 E 8 3 A 0 6 N
P2PT > P1PT
Play on the (rightmost) larg-est regular reward pointsposition with an addition.
N Y
Skip
RD < 4
N Y
Play on the (rightmost) largestdisplay position with an adition
NYU School of Engineering Page 21 of 28 CS2204 Handout No : 15 April 3, 2014
iii) The table is completed as follows :
Q17) Consider Block 6, the Machine Play Block, of the term project. Assume that its strategy is as follow :
The datapath of the circuit that implements the above strategy is shown below :
In the figure, RLAPadd is 1 if an addition is needed to play on the rightmost largest adjacency position. Play is 1 inthe last Player 2 state.
a) i) Assume that the code is A7.
The table below shows the random digit, position displays before and after the machine player plays, whether therandom digit is played directly or added, the number of adjacencies, the points earned by the machine player and ifthe machine player plays again. Complete the rows of the table. You will circle the position played :
RDDisplays before playPD3 PD2 PD1 PD0
P2GTP1Displays after play
PD3 PD2 PD1 PD0D/A Adjacency
Reward Points(Decimal)
Plays Again ?
5 0 7 0 0 Yes 0 7 0 0 Skip Skip Skip Skip
2 8 C 0 0 No 8 E 0 0 A 0 14 N
6 8 E 6 0 No E E 6 0 A 1 28 Y
3 A E 6 3 Yes D 1 6 3 A 0 1 N
7 F E 8 3 No F E F 3 A 0 15 N
Play on the (rightmost) largest adjacency position (directly if equal)
P2SEL3
P2SEL2
P2SEL1
P2SEL0
Test3
Test2
Test1
Test0Play
RLAP1
RLAP0
Y3
Y2
Y1
Y0
I1
I0 2-to
-4 D
CD
P2skip
P2add
P2playedPlay
Rightmost RLAP1
RLAP0Largest
Adjacency
Position
.
.
.
.
.
Circuit
RLAPadd
0
RLAPaddTestaddPlay(RLAP)
LRGADJ1
LRGADJ0
NYU School of Engineering Page 22 of 28 CS2204 Handout No : 15 April 3, 2014
ii) How many clock periods does the machine player take to play ? Explain.
b) i) Assume that the above machine player is modified to have the following new strategy :
Assume again that the code is A7. The table below shows the random digit, position displays before and after themachine player plays, whether the random digit is played directly or added, the number of adjacencies, the pointsearned by the machine player and if the machine player plays again. Complete the rows of the table. You will circlethe position played :
ii) Modify the above circuit (the datapath) to implement the new strategy (two rectangles and one oval).You can justshow the modified portion of the circuit, not the whole circuit.
A17) a) i) The table is completed below :
RDDisplays before playPD3 PD2 PD1 PD0
Displays after playPD3 PD2 PD1 PD0
D/A AdjacencyReward Points
(Decimal)Plays
Again ?
8 F F F F
6 F 5 5 5
4 6 A 6 7
7 0 0 0 0
3 1 E 8 E
RDDisplays before playPD3 PD2 PD1 PD0
Displays after playPD3 PD2 PD1 PD0
D/A AdjacencyReward Points
(Decimal)Plays
Again ?
8 F F F F
6 F 5 5 5
4 6 A 6 7
7 0 0 0 0
3 1 E 8 E
Play on the (rightmost) largest adjacencyposition (directly if equal)
The largest adjacency is 0 ?
YN
Play directly either on position 0 if the random digit iseven and on position 1 if the random digit is odd
NYU School of Engineering Page 23 of 28 CS2204 Handout No : 15 April 3, 2014
The strategy does not check for code digits and so misses to earn code reward points when the random digit is 8.However, it earns code reward points by coincidence when the random digit is 4 and 7.ii) The machine player takesnine clock periodto play. It does direct playing and additions, hence it takes eight clock periods to collect the eightadjacencies and then one clock period to play.
b) i) The table is completed as follows :
The strategy also does not check for code digits and so again misses to earn code reward points when the randomdigit is 8. It also misses to earn code reward points when the random digit is 7. However, it again earns code rewardpoints by coincidence when the random digit is 4.
ii) We know that the Rightmost Largest Adjacency circuit keeps the largest adjacency when it determines which posi-tion has it. The largest adjacency lines, LRGADJ1 and LRGADJ0 are used to determine if the adjacency is 0 :
RDDisplays before playPD3 PD2 PD1 PD0
Displays after playPD3 PD2 PD1 PD0
D/A AdjacencyReward Points
(Decimal)Plays
Again ?
8 F F F F F F F 8 D 0 8 N
6 F 5 5 5 5 5 5 5 A 3 40 Y
4 6 A 6 7 6 A A 7 A 1 187 Y
7 0 0 0 0 0 0 0 7 D 0 63 N
3 1 E 8 E 1 1 8 E A 1 2 Y
RDDisplays before playPD3 PD2 PD1 PD0
Displays after playPD3 PD2 PD1 PD0
D/A AdjacencyReward Points
(Decimal)Plays
Again ?
8 F F F F F F F 8 D 0 8 N
6 F 5 5 5 5 5 5 5 A 3 40 Y
4 6 A 6 7 6 A A 7 A 1 187 Y
7 0 0 0 0 0 0 7 0 D 0 7 N
3 1 E 8 E 1 1 8 E A 1 2 Y
NYU School of Engineering Page 24 of 28 CS2204 Handout No : 15 April 3, 2014
Q18) Consider the following digital system whose black-box view and high-level state diagram are shown below :
The “Clr” input is an asynchronous input that forces the system to return to state 0 from any state at any time andkeeps it at state 0 as long as “Clr” is active.
a) Consider Block 6, the Machine Play Block, of the term project. Assume that the digital system above is used for
the machine player as shown below.
Rightmost RLAP1
RLAP0Largest
Adjacency
Position
.
.
.
.
.
Circuit
RLAPadd
(RLAP)LRGADJ1
LRGADJ0
Y0
Y1
RD0
0
A0
B0
A1
B1
Sel
2-bi
t 2-t
o-1
MU
X
RLAP1
RLAP0
Adj
P2SEL3
P2SEL2
P2SEL1
P2SEL0
Test3
Test2
Test1
Test0Play
Y3
Y2
Y1
Y0
I0
I1
2-to
-4 D
CD
P2skip
P2add
P2playedPlay
0
TestaddPlay
RLAPadd
Adj
Y
clock
4
2
K
Go
Clr
Valid
Z
4
Y = 0001 ; W = A ; Valid = 0 ; Z = 0 ; A K ; B 0001
Y = 0010 ; W = A ; Valid = 0 ; Z = 0 ; If K > A then {A K ; B 0010}
0
1
2
3
Y = 0100 ; W = A ; Valid = 0 ; Z = 0 ; If K > A then {A K ; B 0100}
Y = 1000 ; W = A ; Valid = 0 ; Z = 0 ; If K > A then {A K ; B 1000}
4Y = 0000 ; W = A ; Valid = 1 ; Z = B
GoGoW
2
NYU School of Engineering Page 25 of 28 CS2204 Handout No : 15 April 3, 2014
The table below shows the random digit, position displays before and after the machine player plays, whether therandom digit is played directly or added, the number of adjacencies, the points earned by the machine player and ifthe machine player plays again.
The meaning of D/A is Direct/Add which is whether the machine player plays the random digit directly on a positionor by adding to a position. Note that the cases on the table are independent of each other. That is, they do not fol-low each other with respect to time.
Complete the rows of the table below. You will circle the position played. Assume that the code is 93.
b) Assume that the above machine player is modified to have a new strategy shown below :
RDDisplays before playPD3 PD2 PD1 PD0
Displays after playPD3 PD2 PD1 PD0
D/A AdjacencyReward Points
(Decimal)Plays
Again ?
8 4 4 C 4
3 F C 6 3
9 E 5 9 9
1 2 1 1 1
4 6 2 2 6
P2SEL0
P2SEL1
P2SEL2
P2SEL3
P2skip
P2add0
NSD
P2played
Y
clock
4
2
K
Go
Clr
Valid
Z
4
P2sturn
Clearp2ffs
P2clk
Y0
Y1
Y2
Y3
Valid
Z0
Z1
Z2
Z3
Valid
0
W
2
NYU School of Engineering Page 26 of 28 CS2204 Handout No : 15 April 3, 2014
Design the modified machine player to implement the new strategy. Use the digital system on the second page andthe Rightmost Largest Display Position circuit designed in Experiment 4 as well as other circuits. Describe the newsignals you use. Draw your design below.
How many clock periods does the machine player take to play ? Explain.
YN
Play on the (rightmost) largest
There is an adjacency ?
Play on the (rightmost) largest adjacencyposition directlydisplay with an addition
P2SEL0
P2SEL1
P2SEL2
P2SEL3
P2skip
P2add
P2played
RightmostDPOS0
DPOS1
DPOS2
DPOS3
Largest
Display
Position
Circuit
z
y
2-to-4
DCDmsb
I0
I1
Y0
Y1
Y2
Y3
16
DISP
Y
clock
4
2
K
Go
Clr
Valid
Z
4
W
2
NYU School of Engineering Page 27 of 28 CS2204 Handout No : 15 April 3, 2014
A18) a) The table is completed as shown below :
The strategy does not check for code digits and so misses to earn code reward points when RD is 3 and 9.
b) The modified machine player is shown below.
There are no new signals.
The machine player takes five clock periods to play since the digital system takes 4 clock periods to collect informa-tion and one clock period to play.
RDDisplays before playPD3 PD2 PD1 PD0
Displays after playPD3 PD2 PD1 PD0
D/A AdjacencyReward Points
(Decimal)Plays
Again ?
8 4 4 C 4 4 4 C 8 D 0 8 N
3 F C 6 3 F C 3 3 D 1 6 Y
9 E 5 9 9 E 9 9 9 D 2 36 Y
1 2 1 1 1 1 1 1 1 D 3 8 Y
4 6 2 2 6 6 2 2 4 D 0 4 N
NYU School of Engineering Page 28 of 28 CS2204 Handout No : 15 April 3, 2014
P2SEL0
P2SEL1
P2SEL2
P2SEL3
P2skip
P2add
P2played
RightmostDPOS0
DPOS1
DPOS2
DPOS3
Largest
Display
Position
Circuit
z
y
2-to-4
DCDmsb
I0
I1
Y0
Y1
Y2
Y3
16
DISP
Y0
Y1
Y2
Y3
Valid
Valid
0
Y0
Y1
Y2
Y3
DPOS0
DPOS1
DPOS2
DPOS3
Z0
Z1
Z2
Z3
A0
B0
A1
B1
A2
B2
A3
B3
Sel
4-bi
t 2-t
o-1
MU
X
W0
W1
E
NSD
Y
clock
4
2
K
Go
Clr
Valid
Z
4
P2sturn
Clearp2ffs
P2clk
W
2
Adj
Adj
Valid