US006862223B1

(12) United States Patent (10) Patent N0.: US 6,862,223 B1 Lee et al. (45) Date of Patent: Mar. 1, 2005

(54) MONOLITHIC, COMBO NONVOLATILE 6,307,781 B1 10/2001 Shum .................. .. 365/185.17 6,326,661 B1 12/2001 Dormans et a1. ......... .. 257/315

BLOCK WRITE WITH NO DISTURB AND 6,370,081 B1 4/2002 Sakui et a1. ........... .. 365/238.5 _ 6,400,603 B1 * 6/2002 Blyth et a1. 365/185.12

gglggligggggvgglgggggggggmn B2 .................. .. 6,618,789 B1 * 9/2003 Okaue et a1. 711/103

A 2001/0016040 A1 * 8/2001 Imura ....................... .. 379/354 DECODER AND LAYOUT

(75) Inventors: Peter W. Lee, Saratoga, CA (US); Fu-Chang Hsu, San Jose, CA (US); Hsing-Ya Tsao, San Jose, CA (US); Han-Rei Ma, Los Altos, CA (US); Koucheng Wu, San Jose, CA (US)

(73) Assignee: Aplus Flash Technology, Inc., San Jose, CA (US)

* Notice: Sub'ect to an disclaimer, the term of this J y patent is extended or adjusted under 35 USC 154(b) by 0 days.

(21) (22)

Appl. No.: 10/223,208

Filed: Aug. 19, 2002

Related US. Application Data Provisional application No. 60/394,202, ?led on Jul. 5, 2002.

Int. Cl.7 .............................................. .. G11C 16/04

US. Cl. .......................... .. 365/185.33; 365/185.05;

365/185.17 Field of Search ..................... .. 365/185.33, 185.05,

365/185.17, 185.18, 185.11, 185.12, 185.01, 63, 438/257

(60)

(51) (52)

(58)

(56) References Cited

U.S. PATENT DOCUMENTS

5,748,538 A 6,174,759 B1 6,212,102 B1 6,266,274 B1

5/1998 Lee et a1. ............ .. 365/185.06

1/2001 Verhaar et al. ........... .. 438/201

4/2001 Georgakos et a1. 365/185.18 7/2001 Pockrandt et a1. 365/185.17

OTHER PUBLICATIONS

U.S. Appl. No. 09/852,247 ?led May 9, 2001, “A Novel 3—Step Write Operation Nonvolatile Semiconductor One— Transistor, NOR—Type Flash EEPROM Memory Cell,” AP—01—001.1. U.S. Appl. No. 09/891,782 ?led Jun. 27, 2001, “A Novel 3—Step Write Operation Nonvolatile Semiconductor One— Transistor Flash EEPROM Memory,” AP 01—001.2.

* cited by examiner

Primary Examiner—Gene N. Auduong (74) Attorney, Agent, or F irm—George O. Saile; Stephen B. Ackerman; Rosemary L.S. Pike

(57) ABSTRACT

A novel FLASH-based EEPROM cell, decoder, and layout scheme are disclosed to eliminate the area-consuming divided triple-Well in cell array and alloWs byte-erase and byte-program for high P/E cycles. Furthermore, the process compatible FLASH cell for EEPROM part can be integrated With FLASH and ROM parts so that a superior combo, monolithic, nonvolatile memory is achieved. Unlike all previous arts, the novel combo nonvolatile memory of the present invention of ROM, EEPROM and FLASH or com bination of any tWo is made of one uni?ed, fully compatible, highly-scalable BN+cell and uni?ed process. In addition, its cell operation schemes have Zero array overhead and Zero disturbance during P/E operations. The novel combo non volatile memory is designed to meet the need in those markets requiring ?exible Write siZe in units of bytes, pages and blocks at a loWer cost.

28 Claims, 51 Drawing Sheets

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U.S. Patent Mar. 1,2005 Sheet 4 0f51 US 6,862,223 B1

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